TW202308096A - 包括在邊緣區的埋入式介電圖案的半導體晶片及包括其的半導體封裝 - Google Patents
包括在邊緣區的埋入式介電圖案的半導體晶片及包括其的半導體封裝 Download PDFInfo
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- TW202308096A TW202308096A TW111110877A TW111110877A TW202308096A TW 202308096 A TW202308096 A TW 202308096A TW 111110877 A TW111110877 A TW 111110877A TW 111110877 A TW111110877 A TW 111110877A TW 202308096 A TW202308096 A TW 202308096A
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Abstract
一種半導體晶片、一種包括所述半導體晶片的半導體封裝及一種製造所述半導體晶片的方法,半導體晶片包括:基板,包括裝置區及邊緣區;裝置層與配線層,依序堆疊於基板上;輔助圖案,在邊緣區上位於配線層上;第一頂蓋層,覆蓋輔助圖案的側壁、配線層的頂表面及配線層的側壁,第一頂蓋層包括上部外側壁及下部外側壁,下部外側壁與上部外側壁偏置開;以及埋入式介電圖案,與第一頂蓋層的下部外側壁接觸且與第一頂蓋層的上部外側壁間隔開。
Description
實施例是有關於一種在半導體晶片的邊緣區處包括埋入式介電圖案的半導體晶片、一種包括半導體晶片的半導體封裝及一種製造半導體晶片的方法。
[相關申請案的交叉參考]
本申請案主張優先於在2021年8月4日在韓國智慧財產局提出申請的韓國專利申請案第10-2021-0102574號,所述韓國專利申請案的內容特此全文併入供參考。
包括半導體裝置的晶圓可包括上面形成多個單元的晶片區及將晶片彼此劃分開的切割道(scribe lane)。多個半導體裝置(例如電晶體、電阻器及電容器)可形成於晶片區上且可不形成於切割道上。可沿著切割道對晶圓進行鋸切,以完成各半導體裝置(或半導體晶片)或將各半導體裝置(或半導體晶片)分隔。
實施例可藉由提供一種半導體晶片而達成,所述半導體晶片包括:基板,包括裝置區及邊緣區;裝置層與配線層,依序堆疊於所述基板上;輔助圖案,在所述邊緣區上位於所述配線層上;第一頂蓋層,覆蓋所述輔助圖案的側壁、所述配線層的頂表面及所述配線層的側壁,所述第一頂蓋層包括上部外側壁及下部外側壁,所述下部外側壁與所述上部外側壁偏置開;以及埋入式介電圖案,與所述第一頂蓋層的所述下部外側壁接觸且與所述第一頂蓋層的所述上部外側壁間隔開。
實施例可藉由提供一種半導體晶片而達成,所述半導體晶片包括:基板,包括裝置區及邊緣區;裝置層與配線層,依序堆疊於所述基板上;分隔介電圖案,在與所述裝置區和所述邊緣區之間的邊界相鄰的同時穿透所述配線層;輔助圖案,在所述邊緣區上位於所述配線層上;接墊圖案,在所述裝置區上位於所述配線層上;鈍化層,覆蓋所述接墊圖案及所述輔助圖案;第一頂蓋層,覆蓋所述輔助圖案的側壁及所述配線層的側壁;以及埋入式介電圖案,與所述第一頂蓋層的下部外側壁接觸,其中所述埋入式介電圖案的頂表面形成自所述鈍化層的頂表面延伸的階狀區,所述配線層包括依序堆疊的下部介電堆疊與上部介電堆疊,所述下部介電堆疊中包含的介電材料具有較所述上部介電堆疊中包含的介電材料的介電常數小的介電常數,所述輔助圖案包括測試圖案或對準標記(alignment key),且所述第一頂蓋層的密度大於所述埋入式介電圖案的密度。
實施例可藉由提供一種半導體封裝而達成,所述半導體封裝包括:第一半導體晶片;第二半導體晶片,堆疊於所述第一半導體晶片上;以及模具層,覆蓋所述第二半導體晶片的側向表面及所述第一半導體晶片的頂表面,其中各所述第二半導體晶片包括第二基板及位於所述第二基板下方的電路結構,所述第二基板包括裝置區及環繞所述裝置區的邊緣區,所述電路結構包括:裝置層與配線層,依序堆疊於所述第二基板下方;輔助圖案,在所述邊緣區上位於所述配線層下方;接墊圖案,在所述裝置區上位於所述配線層下方;鈍化層,覆蓋所述接墊圖案的底表面及所述輔助圖案的底表面;第一頂蓋層,覆蓋所述輔助圖案的側壁及所述配線層的側壁;以及埋入式介電圖案,與所述第一頂蓋層的上部外側壁接觸,所述埋入式介電圖案的底表面形成自所述鈍化層的底表面延伸的階狀區,且所述模具層對所述階狀區進行填充。
實施例可藉由提供一種製造半導體晶片的方法而達成,所述方法包括:在基板上形成配線層,所述基板包括多個裝置區及位於裝置區之間的切割道區;對配線層進行蝕刻以形成與裝置區交疊的多個主配線結構及與切割道區交疊的多個邊緣配線結構;形成分隔介電圖案及埋入式介電圖案,使得分隔介電圖案位於主配線結構及邊緣配線結構之中的一對鄰近的主配線結構與邊緣配線結構之間,且埋入式介電圖案位於鄰近的邊緣配線結構之間;形成覆蓋主配線結構、邊緣配線結構、分隔介電圖案及埋入式介電圖案的鈍化層;自切割道區的中心移除鈍化層,以形成暴露出埋入式介電圖案的溝渠;以及對埋入式介電圖案及埋式介電圖案下面的基板進行劃切以形成彼此分隔的多個晶片。
圖1示出根據一些實施例的半導體裝置的平面圖。圖2示出沿著圖1所示線A-A'截取的剖視圖。
參照圖1及圖2,根據本實施例的半導體晶片100可包括基板1及電路結構CS。基板1可包含例如半導體材料。基板1可為單晶矽基板。基板1可包括裝置區DR及環繞裝置區DR的邊緣區ER。基板1可具有彼此相對的第一表面1a與第二表面1b。電路結構CS可位於基板1的第一表面1a上。電路結構CS可包括依序堆疊的裝置層DL、配線層IL及接墊層PL。
電晶體TR可在裝置區DR上位於基板1的第一表面1a上。在實施方式中,裝置區DR上的第一表面1a可包括淺隔離圖案、記憶單元、電容器等。基板1的第一表面1a可覆蓋有裝置層間介電層3。裝置層間介電層3可具有包含例如氧化矽、氮化矽或氮氧化矽的單層結構或多層結構。在裝置區DR上,裝置層間介電層3中可包括連接至電晶體TR的接觸插塞5c。在邊緣區ER上,裝置層間介電層3可包括第一防護環圖案5g。如本文中所使用,用語「或」不是排他性用語,例如「A或B」將包括A、B或者A及B。
接觸插塞5c與第一防護環圖案5g可包含相同的材料,例如鎢。在實施方式中,接觸插塞5c及第一防護環圖案5g可在其側向表面及底表面上覆蓋有障壁金屬。障壁金屬可包含例如鈦、氮化鈦、鉭、氮化鉭或氮化鎢。接觸插塞5c及第一防護環圖案5g可穿透裝置層間介電層3。裝置層DL可由電晶體TR、裝置層間介電層3、接觸插塞5c及第一防護環圖案5g構成。
類似地,以下將參照圖1論述的第五防護環圖案14g,當在平面圖中觀察時,各第一防護環圖案5g可具有環繞裝置區DR的環形狀。第一防護環圖案5g可保護裝置區DR上的裝置層DL免受濕氣或物理裂紋的影響。
下部配線層LI可位於裝置層間介電層3上。下部配線層LI可包括彼此間隔開的主下部介電堆疊7m與邊緣下部介電堆疊7e。主下部介電堆疊7m及邊緣下部介電堆疊7e可各自包括多個下部金屬間介電層10。下部金屬間介電層10可包含具有較氧化矽的介電常數小的介電常數的低k介電材料。在實施方式中,下部金屬間介電層10可為多孔介電層。各下部金屬間介電層10可具有較裝置層間介電層3的機械強度小的機械強度。在實施方式中,在下部金屬間介電層10之間可插入有蝕刻停止層。蝕刻停止層可包含例如氮化矽、氮氧化矽或碳氮化矽。
主下部介電堆疊7m可覆蓋裝置區DR及邊緣區ER的與裝置區DR相鄰的一部分。當在如圖1中所示的平面圖中觀察時,邊緣下部介電堆疊7e可位於邊緣區ER上且可環繞主下部介電堆疊7m。
下部配線層LI可包括在裝置區DR上位於主下部介電堆疊7m中的多個下部配線圖案9,且亦可包括將下部配線圖案9連接至彼此的下部通孔圖案11。下部配線層LI更可包括在邊緣區ER上位於主下部介電堆疊7m中的下部防護環結構GS1。下部防護環結構GS1可包括第二防護環圖案9g及將第二防護環圖案9g連接至彼此的第三防護環圖案11g。第二防護環圖案9g可處於與下部配線圖案9的高度(水平)相同的高度(水平)處且可包含與下部配線圖案9的材料相同的材料。第三防護環圖案11g可位於與下部通孔圖案11的高度(水平)相同的高度(水平)處且可包含與下部通孔圖案11的材料相同的材料。當在平面圖中觀察時,第二防護環圖案9g及第三防護環圖案11g可各自具有環繞裝置區DR的輪狀形狀或閉環形狀。下部防護環結構GS1可有助於保護裝置區DR上的下部配線層LI免受濕氣或物理裂紋的影響。
下部配線層LI可包括位於邊緣下部介電堆疊7e中或與邊緣下部介電堆疊7e相鄰的第一輔助圖案結構SS1。第一輔助圖案結構SS1可包括第一輔助圖案9s及將第一輔助圖案9s連接至彼此的第一輔助通孔圖案11s。第一輔助圖案9s可位於與下部配線圖案9的高度(水平)相同的高度(水平)處且可包含與下部配線圖案9的材料相同的材料。第一輔助通孔圖案11s可位於與下部通孔圖案11的高度(水平)相同的高度(水平)處且可包含與下部通孔圖案11的材料相同的材料。第一輔助圖案結構SS1可為例如測試圖案、對準標記或上覆標記。
下部配線層LI可由主下部介電堆疊7m、邊緣下部介電堆疊7e、下部配線圖案9、下部通孔圖案11、下部防護環結構GS1及第一輔助圖案結構SS1構成或包括主下部介電堆疊7m、邊緣下部介電堆疊7e、下部配線圖案9、下部通孔圖案11、下部防護環結構GS1及第一輔助圖案結構SS1。
上部配線層UI可位於下部配線層LI上。上部配線層UI可包括彼此間隔開的主上部介電堆疊20m與邊緣上部介電堆疊20e。主上部介電堆疊20m與邊緣上部介電堆疊20e可各自包括依序堆疊的第一上部金屬間介電層13、第二上部金屬間介電層15、氫阻擋層17及第三上部金屬間介電層19。第一上部金屬間介電層13、第二上部金屬間介電層15及第三上部金屬間介電層19可各自包含具有較下部金屬間介電層10的介電常數的大的介電常數的介電材料。第一上部金屬間介電層13、第二上部金屬間介電層15及第三上部金屬間介電層19可各自具有較下部金屬間介電層10的機械強度大的機械強度。第一上部金屬間介電層13、第二上部金屬間介電層15及第三上部金屬間介電層19可各自包含例如氧化矽、正矽酸四乙酯(tetraethylorthosilicate,TEOS)或高密度電漿(high-density plasma,HDP)氧化物。
在實施方式中,蝕刻停止層可位於第一上部金屬間介電層13、第二上部金屬間介電層15及第三上部金屬間介電層19中的相鄰層之間。氫阻擋層17可包含具有低氫滲透性的材料。在實施方式中,氫阻擋層17可包含例如氧化鋁(AlO
x)、氧化鎢(WO
x)或氮化矽(SiN
x)。
第一上部通孔圖案12、子接墊14及第二上部通孔圖案22可在裝置區DR上位於主上部介電堆疊20m中。在實施方式中,上部配線圖案及上部通孔圖案亦可在裝置區DR上位於主上部介電堆疊20m中。第一上部通孔圖案12可穿透第一上部金屬間介電層13,且可將下部配線圖案9中的一者連接至子接墊14。當在平面圖中觀察時,子接墊14可具有接墊形狀,且子接墊14可被第二上部金屬間介電層15覆蓋。第二上部通孔圖案22可穿透第三上部金屬間介電層19、氫阻擋層17及第二上部金屬間介電層15,藉此接觸子接墊14。
上部防護環結構GS2可在裝置區DR上位於主上部介電堆疊20m中。上部防護環結構GS2可包括第四防護環圖案12g及第五防護環圖案14g。第四防護環圖案12g可穿透第一上部金屬間介電層13且可具有與第一上部通孔圖案12的高度及材料相同的高度及材料。第五防護環圖案14g可具有與子接墊14的高度及材料相同的高度及材料,且可被第二上部金屬間介電層15覆蓋。如圖1中所示,第四防護環圖案12g及第五防護環圖案14g可環繞裝置區DR。上部防護環結構GS2可有助於保護裝置區DR上的上部配線層UI免受濕氣或物理裂紋的影響。
第二輔助圖案結構SS2可位於邊緣上部介電堆疊20e中。第二輔助圖案結構SS2可包括第二輔助通孔圖案12s及第三輔助通孔圖案22s以及位於第二輔助通孔圖案12s與第三輔助通孔圖案22s之間的第二輔助圖案14s。第二輔助圖案14s可具有與子接墊14的材料及高度相同的高度及材料,且可被第二上部金屬間介電層15覆蓋。第二輔助通孔圖案12s可穿透第一上部金屬間介電層13,且可具有與第一上部通孔圖案12的高度及材料相同的高度及材料。第三輔助通孔圖案22s可穿透第三上部金屬間介電層19、氫阻擋層17及第二上部金屬間介電層15,藉此接觸第二輔助圖案14s。第二輔助圖案結構SS2可為例如測試圖案、對準標記或上覆標記。
主上部介電堆疊20m可具有與主下部介電堆疊7m的側壁對準(例如共面)的側壁。邊緣上部介電堆疊20e可具有與邊緣下部介電堆疊7e的側壁對準的側壁。
分隔介電圖案27s可將配線層IL分隔成主配線結構ILM及邊緣配線結構ILE。主配線結構ILM與邊緣配線結構ILE之間的空間可被界定為第一溝渠TR1。當在平面圖中觀察時,分隔介電圖案27s可環繞裝置區DR。第一頂蓋層25可位於分隔介電圖案27s與主配線結構ILM之間、分隔介電圖案27s與邊緣配線結構ILE之間、以及分隔介電圖案27s與裝置層DL之間。
分隔介電圖案27s及第一頂蓋層25可各自包含具有較下部金屬間介電層10的介電常數及機械強度大的介電常數及機械強度的介電材料。第一頂蓋層25(例如,形成第一頂蓋層25的材料)可具有較分隔介電圖案27s(例如,形成分隔介電圖案27s的材料)的密度大的密度。在實施方式中,第一頂蓋層25可包含例如高密度電漿(HDP)氧化物,且分隔介電圖案27s可包含例如正矽酸四乙酯(TEOS)。
在一些情形中,下部配線層LI可包括機械強度低的下部金屬間介電層10,且物理裂紋可容易地沿著下部金屬間介電層10傳播至裝置區DR。在實施方式中,第一溝渠TR1及其中的分隔介電圖案27s以及第一頂蓋層25可有助於防止物理裂紋自邊緣區ER朝向裝置區DR傳播。在一些情形中,當下部金屬間介電層10包含多孔介電材料時,濕氣可容易地被引入至半導體晶片100中。在實施方式中,第一溝渠TR1及其中的分隔介電圖案27s以及第一頂蓋層25可有助於防止濕氣自半導體晶片100的最外側被引入至裝置區DR中。因此,半導體晶片100可表現出增加的可靠性。
主配線結構ILM可覆蓋裝置區DR及邊緣區ER的與裝置區DR相鄰的一部分。邊緣配線結構ILE可位於邊緣區ER上。裝置層DL的頂表面可暴露於主配線結構ILM的側上及邊緣配線結構ILE的側上或者主配線結構ILM的側處及邊緣配線結構ILE的側處。
主配線結構ILM可包括主下部介電堆疊7m、下部配線圖案9、下部通孔圖案11、下部防護環結構GS1、主上部介電堆疊20m、第一上部通孔圖案12及第二上部通孔圖案22、子接墊14以及上部防護環結構GS2。邊緣配線結構ILE可包括邊緣下部介電堆疊7e、第一輔助圖案結構SS1、邊緣上部介電堆疊20e及第二輔助圖案結構SS2。
接墊層PL可位於配線層IL上。接墊層PL可包括位於裝置區DR上的接墊圖案21p及位於邊緣區ER上的第三輔助圖案21s。第三輔助圖案21s可為測試圖案或對準標記。在實施方式中,如圖1中所示,第三輔助圖案21s可被設置成多個,且所述多個第三輔助圖案21s可線性地佈置於邊緣區ER上。
接墊圖案21p可藉由第二上部通孔圖案22電性連接至子接墊14。第三輔助圖案21s可電性連接至第二輔助圖案結構SS2。配線層IL的頂表面可暴露於接墊圖案21p及第三輔助圖案21s中的每一者的相對的側上或者接墊圖案21p及第三輔助圖案21s中的每一者的相對的側處。
硬罩幕圖案23可覆蓋配線層IL的頂表面且亦可覆蓋接墊圖案21p的側壁及頂表面以及第三輔助圖案21s的側壁及頂表面。硬罩幕圖案23可包含例如高密度電漿(HDP)氧化物、未經摻雜的矽酸鹽玻璃(undoped silicate glass,USG)、正矽酸四乙酯(TEOS)、SiN、SiO
2、SiOC、SiON或SiCN。
第一頂蓋層25可共形地形成於硬罩幕圖案23上。第一頂蓋層25的一部分可穿透配線層IL且接觸裝置層DL。在邊緣區ER的最外側上,第一頂蓋層25可覆蓋第三輔助圖案21s的側壁、邊緣配線結構ILE的側壁及裝置層DL的頂表面。
埋入式介電層27可位於第一頂蓋層25上。如上所述,埋入式介電層27的一部分可插置至第一溝渠TR1中,以構成分隔介電圖案27s。埋入式介電層27可包含例如正矽酸四乙酯(TEOS)。
在邊緣區ER的最外側上,第一頂蓋層25可具有彼此偏置開(例如,不連續或不對準)的上部外側壁25us與下部外側壁25bs。上部外側壁25us可被暴露出。下部外側壁25bs可與埋入式介電圖案27b接觸。埋入式介電層27的一部分可為埋入式介電圖案27b,且埋入式介電層27與埋入式介電圖案27b可包含相同的材料。埋入式介電圖案27b可具有較第一頂蓋層25的密度小的密度。埋入式介電圖案27b的頂表面27bu可位於與第一頂蓋層25的上部外側壁25us的底端25use的水平實質上相同的水平處。
無論位置如何,第一頂蓋層25可具有幾乎恆定的厚度。在實施方式中,第一頂蓋層25可具有分隔介電圖案27s下方的第一厚度T1及埋入式介電圖案27b下方的第二厚度T2。第二厚度T2可與第一厚度T1幾乎相同。在實施方式中,第二厚度T2可為第一厚度T1的約0.9倍至約1.1倍。
第二頂蓋層29可位於埋入式介電層27上。第二頂蓋層29可包含例如氮化矽。上部鈍化層35可位於第二頂蓋層29上。上部鈍化層35可包括依序堆疊的第一上部鈍化層31與第二上部鈍化層33。第一上部鈍化層31可包含例如高密度電漿(HDP)氧化物、未經摻雜的矽酸鹽玻璃(USG)、正矽酸四乙酯(TEOS)、SiN、SiO
2、SiOC、SiON或SiCN。第二上部鈍化層33可包含例如SiCN。
在裝置區DR上,第一上部鈍化層31的一部分可穿透第二頂蓋層29、埋入式介電層27、第一頂蓋層25及硬罩幕圖案23,藉此接觸接墊圖案21p。在邊緣區ER上,第一上部鈍化層31的另一部分可穿透第二頂蓋層29、埋入式介電層27、第一頂蓋層25及硬罩幕圖案23,藉此接觸第三輔助圖案21s。
在裝置區DR上,上部結合接墊37可穿透第二上部鈍化層33及第一上部鈍化層31,藉此接觸接墊圖案21p。上部結合接墊37可具有與第二上部鈍化層33的頂表面33u共面的頂表面。
第二上部鈍化層33的頂表面33u與埋入式介電圖案27b的頂表面27bu可形成階梯差或階狀區SDR(例如,第二上部鈍化層33的頂表面33u可位於較埋入式介電圖案27b的頂表面27bu高的水平處,以形成階梯結構,階狀區SDR)。當在如圖1所示的平面圖中觀察時,階狀區SDR可沿著半導體晶片100的邊緣形成。階狀區SDR可環繞裝置區DR。
第二上部鈍化層33、第一上部鈍化層31、第二頂蓋層29及埋入式介電層27可具有與第一頂蓋層25的上部外側壁25us對準的側壁。埋入式介電圖案27b、埋入式介電圖案27b下面的裝置層間介電層3以及基板1可具有彼此對準的側壁。
在實施方式中,半導體晶片100可具有被第一頂蓋層25及埋入式介電圖案27b阻擋或覆蓋的最外表面,此可有利於防止水平裂紋及濕氣吸收。
接墊層PL可包括第二上部鈍化層33、第一上部鈍化層31、第二頂蓋層29、埋入式介電層27、第一頂蓋層25及硬罩幕圖案23。
基板1的第二表面1b可覆蓋有下部鈍化層44。下部鈍化層44可包括依序堆疊於基板1的第二表面1b上的第一下部鈍化層40與第二下部鈍化層42。第一下部鈍化層40可包含例如氧化矽或氮化矽。第二下部鈍化層42可包含例如SiCN。
裝置區DR可包括穿透裝置層間介電層3、基板1及第一下部鈍化層40的貫穿電極TSV。貫穿電極TSV可與下部配線圖案9中的一者接觸。貫穿介電層TL可位於貫穿電極TSV與基板1之間。貫穿介電層TL可包含例如氧化矽。
下部結合接墊46可位於第二下部鈍化層42中且可與貫穿電極TSV接觸。下部結合接墊46可具有與第二下部鈍化層42的底表面共面的底表面。
圖3示出根據一些實施例的半導體封裝的剖視圖。
參照圖3,根據本實施例的半導體封裝1000可包括依序堆疊的第一半導體晶片100a至第五半導體晶片100e。第一半導體晶片100a可具有與第二半導體晶片100b至第五半導體晶片100e不同的類型。第一半導體晶片100a可為例如邏輯電路晶片。第二半導體晶片100b至第五半導體晶片100e可為相同的(例如,相同結構的)記憶體晶片。在實施方式中,記憶體晶片可為例如動態隨機存取記憶體(dynamic random access memory,DRAM)、反及快閃、靜態隨機存取記憶體(static random access memory,SRAM)、磁性隨機存取記憶體(magnetic random access memory,MRAM)或相變隨機存取記憶體(phase-change random access memory,PRAM)。在實施方式中,封裝可具有以下結構:其中堆疊有一個邏輯電路晶片及四個記憶體晶片,或者邏輯電路晶片的數目及記憶體晶片的數目可不同地改變。第一半導體晶片100a可具有較第二半導體晶片100b至第五半導體晶片100e的寬度大的寬度。半導體封裝1000可為高頻寬記憶體(high bandwidth memory,HBM)晶片。
模具層MD可覆蓋第一半導體晶片100a的頂表面及第二半導體晶片100b至第五半導體晶片100e的側向表面。模具層MD可包含介電樹脂,例如環氧模製化合物(epoxy molding compound,EMC)。模具層MD可更包含填料,且填料可分散於介電樹脂中。填料可包括例如氧化矽(SiO
2)。模具層MD可具有與第五半導體晶片100e中所包括的基板1的第二表面1b共面的頂表面。
第一半導體晶片100a至第五半導體晶片100e中的每一者可具有與參照圖1及圖2論述的半導體晶片100的特性相同或相似的特性。在實施方式中,半導體封裝1000可具有此種結構:在所述結構中,圖1及圖2所示半導體晶片100被設置成多個,且在所述結構中,圖1及圖2所示所述多個半導體晶片100被上下顛倒並且堆疊。與圖1及圖2所示半導體晶片100相同或相似,第一半導體晶片100a至第五半導體晶片100e中的每一者可包括位於基板1的第一表面1a上的電路結構CS。在圖1及圖2中已闡述電路結構CS,且可省略其重複說明。在下文中,由於半導體晶片100處於上下顛倒的狀態,因此基於闡述圖2的觀點,用語「上部」與「下部」是可互換的。
第一半導體晶片100a至第五半導體晶片100e中的下伏的一者的下部結合接墊46可與上覆晶片的上部結合接墊37接觸。在實施方式中,下伏晶片的下部鈍化層44可與上覆晶片的上部鈍化層35接觸。
第一半導體晶片100a至第五半導體晶片100e中的每一者可在其邊緣區處具有階狀區SDR。第二半導體晶片100b至第五半導體晶片100e的階狀區SDR可填充有模具層MD。模具層MD可覆蓋第二半導體晶片100b至第五半導體晶片100e中的每一者中所包括的埋入式介電圖案27b以及第一頂蓋層25的被暴露出的外側壁。
第一半導體晶片100a可包括與接墊圖案21p接觸的結合接墊BP。外部連接端子SB可結合至第一半導體晶片100a的結合接墊BP。外部連接端子SB可包括例如導電凸塊、導電柱或焊料層。外部連接端子SB可包含例如銅、鎳、錫、鉛或銀。
位於頂部位置處的第五半導體晶片100e可既不包括貫穿電極TSV亦不包括下部結合接墊46。其他配置可與參照圖1及圖2論述的配置相同或相似。
根據本實施例的半導體封裝1000可包括可靠性得到改善的半導體晶片100a至100e,如參照圖1及圖2所論述,且因此可提高可靠性。
圖4示出顯示晶圓的平面圖。圖5A至圖5L示出製造具有圖2所示橫截面的半導體晶片的方法中的階段的剖視圖。圖5A至圖5L示出沿著圖5所示線A-A'截取的製程橫截面。
參照圖4及圖5A,可在晶圓W上佈置多個裝置區DR。裝置區DR可各自被稱為晶片區。切割道區SR可位於裝置區DR之間。晶圓W可與圖5A所示基板1對應。可實行普通程序以在基板1的第一表面1a上形成裝置層DL。可對裝置層DL及基板1進行蝕刻以形成用於貫穿電極的孔洞,且可在孔洞中形成貫穿電極TSV及貫穿介電層TL。
可實行普通程序以在裝置層DL上形成配線層IL。配線層IL可包括下部配線層LI及上部配線層UI。下部配線層LI可包括下部介電堆疊7,下部介電堆疊7包括多個下部金屬間介電層10,如圖2中所示。下部介電堆疊7中可設置有下部配線圖案9、下部通孔圖案11、下部防護環結構GS1及第一輔助圖案結構SS1。上部配線層UI可包括上部介電堆疊20。上部介電堆疊20中可設置有子接墊14、上部防護環結構GS2及第二輔助圖案結構SS2。可在上部介電堆疊20的第三上部金屬間介電層19上形成含金屬層21。含金屬層21可包含例如鋁。
參照圖5A及圖5B,可對含金屬層21進行蝕刻以在裝置區DR上形成接墊圖案21p且在切割道區SR上形成第三輔助圖案21s。可在上部介電堆疊20的第三上部金屬間介電層19上共形地形成硬罩幕層23L。硬罩幕層23L可包含例如正矽酸四乙酯(TEOS)。
在實施方式中,參照圖5B及圖5C,可在硬罩幕層23L上形成罩幕圖案。罩幕圖案可包括例如光阻圖案或旋塗硬罩幕(spin-on-hard mask,SOH)圖案。罩幕圖案可用作蝕刻罩幕,以依序對硬罩幕層23L、位於硬罩幕層23L之下的上部介電堆疊20的第三上部金屬間介電層19、氫阻擋層17及第二上部金屬間介電層15進行蝕刻,且因此可形成初步溝渠PTR1及PTR2以暴露出第一上部金屬間介電層13。初步溝渠PTR1及PTR2可包括位於上部防護環結構GS2與和上部防護環結構GS2相鄰的第二輔助圖案結構SS2之間的第一初步溝渠PTR1,且亦可包括位於第二輔助圖案結構SS2之間的第二初步溝渠PTR2。在此步驟中,可對硬罩幕層23L進行蝕刻以形成硬罩幕圖案23。可移除罩幕圖案。
參照圖5C及圖5D,可將硬罩幕圖案23用作對第一上部金屬間介電層13及下部介電堆疊7實行的蝕刻製程的蝕刻罩幕,且因此可將配線層IL劃分成主配線結構ILM及邊緣配線結構ILE。主配線結構ILM可包括依序堆疊的主下部介電堆疊7m與主上部介電堆疊20m。邊緣配線結構ILE可包括依序堆疊的邊緣下部介電堆疊7e與邊緣上部介電堆疊20e。蝕刻製程可在主配線結構ILM與和主配線結構ILM相鄰的邊緣配線結構ILE之間形成第一溝渠TR1且在鄰近的邊緣配線結構ILE之間形成第二溝渠TR2。蝕刻製程可減小硬罩幕圖案23的厚度。在實施方式中,可將硬罩幕圖案23全部移除以暴露出配線層IL的頂表面。
參照圖5E,可在基板1的第一表面1a上共形地形成第一頂蓋層25。可在第一頂蓋層25上形成埋入式介電層27。埋入式介電層27可由例如正矽酸四乙酯(TEOS)形成。埋入式介電層27可對第一溝渠TR1及第二溝渠TR2進行填充。可將分隔介電圖案27s界定成指示埋入式介電層27的對第一溝渠TR1進行填充的部分。在實施方式中,可將埋入式介電圖案27b界定成指示埋入式介電層27的對第二溝渠TR2進行填充的部分。
可對埋入式介電層27實行平坦化製程。因此,埋入式介電層27可在接墊圖案21p及第三輔助圖案21s上具有相對小的厚度及平整的頂表面。可在埋入式介電層27上形成第二頂蓋層29。第二頂蓋層29可包含例如氧化矽。自第一溝渠TR1及第二溝渠TR2轉移的第一轉移溝渠RTR1及第二轉移溝渠RTR2(例如,經填充的第一溝渠TR1及第二溝渠TR2的剩餘部分)可形成於第二頂蓋層29的頂表面上或所述頂表面處。
參照圖5F,可依序對第二頂蓋層29、埋入式介電層27、第一頂蓋層25及硬罩幕圖案23進行蝕刻,以形成分別暴露出接墊圖案21p及第三輔助圖案21s的第一開口OP1及第二開口OP2。
當第三輔助圖案21s是測試圖案時,可藉由第二開口OP2執行測試製程。在實施方式中,測試製程可以此種方式完成:即探針卡的探針可接觸第三輔助圖案21s的暴露於第二開口OP2的表面,且然後可施加測試訊號。測試製程可對半導體裝置的電性性質進行量測,以判斷每一製程是否正常實行且確定單元裝置(unit device)的特性,例如電晶體、金屬配線電阻、通孔電阻等。
參照圖5G,可在第二頂蓋層29上依序堆疊第一上部鈍化層31與第二上部鈍化層33。第一上部鈍化層31可對第一開口OP1及第二開口OP2進行填充。
參照圖5H,可對第一上部鈍化層31及第二上部鈍化層33進行蝕刻以形成暴露出接墊圖案21p的第三開口OP3。第三開口OP3可被形成為與第一開口OP1交疊且具有較第一開口OP1的寬度小的寬度。在實施方式中,第一開口OP1的形成可移除接墊圖案21p上的硬罩幕圖案23、第一頂蓋層25、埋入式介電層27及第二頂蓋層29,且當形成第三開口OP3時,僅對第一上部鈍化層31及第二上部鈍化層33進行蝕刻便足夠。在實施方式中,與其中硬罩幕圖案23、第一頂蓋層25、埋入式介電層27及第二頂蓋層29位於接墊圖案21p上而未形成第一開口OP1的情形相比,可容易地形成第三開口OP3。
可形成晶種層,且可實行鍍覆製程以形成對第三開口OP3進行填充的導電層,且之後可執行化學機械研磨(chemical mechanical polishing,CMP)製程以形成上部結合接墊37且暴露出第二上部鈍化層33。CMP製程可減小第二上部鈍化層33的厚度。
參照圖5I,可在第二上部鈍化層33上形成保護層39。保護層39可包含例如正矽酸四乙酯(TEOS)、SiN、SiO
2、高密度電漿(HDP)氧化物、SiON或SiCN。保護層39可覆蓋及保護上部結合接墊37。
參照圖5I及圖5J,在斷裂區BR上在與第二溝渠TR2交疊的位置上或者在切割道區SR的中心上,可藉由對保護層39、第二上部鈍化層33、第一上部鈍化層31、第二頂蓋層29及埋入式介電層27進行蝕刻來形成第三溝渠TR3。第一頂蓋層25的上部外側壁可暴露於第三溝渠TR3的側壁。埋入式介電圖案27b的頂表面可暴露於第三溝渠TR3的底板上。保護層39可覆蓋且保護上部結合接墊37免受蝕刻製程中的蝕刻損壞。
參照圖5J及圖5K,基板1的第二表面1b可經歷背面研磨製程,以暴露出貫穿介電層TL的底表面。可進一步局部地移除基板1的第二表面1b,以暴露出貫穿介電層TL的側向表面。可在基板1的第二表面1b上堆疊第一下部鈍化層40,且然後可實行化學機械研磨(CMP)以暴露出貫穿電極TSV的底表面。可在第一下部鈍化層40上形成第二下部鈍化層42。可在第二下部鈍化層42上形成下部結合接墊46,下部結合接墊46接觸貫穿電極TSV。
參照圖5K及圖5L,可使用雷射(例如,隱形雷射)來實行鋸切製程,以對在斷裂區BR上暴露於第三溝渠TR3的底板處的中心上的埋入式介電圖案27b進行劃切,且亦依序對位於埋入式介電圖案27b之下的第一頂蓋層25、裝置層間介電層3、基板1及下部鈍化層44進行劃切。因此,圖2所示半導體晶片100可彼此分隔。切割道區SR的一部分可為圖2所示邊緣區ER。
例如,由於邊緣下部介電堆疊7e的下部金屬間介電層10在鋸切製程中不會被暴露,因此不會出現物理裂紋。即使出現物理裂紋,分隔介電圖案27s亦可有助於防止物理裂紋傳播至裝置區DR。在實施方式中,埋入式介電圖案27b與分隔介電圖案27s可雙重地(例如,一起)有助於防止物理側向裂紋。在實施方式中,埋入式介電圖案27b、分隔介電圖案27s以及防護環結構GS1及GS2可三重(例如,一起)有助於防止濕氣吸收。據以,可減少半導體晶片的缺陷,以有助於增加良率且改善半導體晶片的可靠性。
若在鋸切製程中使用刀片代替雷射,則剖切區域可變寬,以局部地移除與第三輔助圖案21s對應的對準標記或測試圖案。在此種情形中,由於結合空隙或短路缺陷,因此結合良率可降低,在結合空隙或短路缺陷中,在隨後的結合製程中,由於對輔助圖案進行剖切而產生的金屬毛刺與相鄰的引線接觸。
對於在半導體晶片被劃切之前的晶圓結構,斷裂區BR亦可在上面設置有由多孔介電材料或低k介電材料形成的下部金屬間介電層10。此種材料特性可能導致難以使用雷射對下部金屬間介電層10進行剖切,且因此半導體晶片可能不會被劃分而導致碎裂或剝離故障。
相反,根據實施例,斷裂區BR可不包括下部金屬間介電層10,且可包括埋入式介電圖案27b及第一頂蓋層25,埋入式介電圖案27b及第一頂蓋層25中的每一者由能夠容易地使用雷射束進行剖切的材料形成,結果半導體晶片可沒有不完整或沒有劃切。據以,可防止碎裂或剝離故障或者將碎裂或剝離故障最小化。
此外,根據實施例,第三溝渠TR3的形成可有助於移除否則將被雷射束移除的大量部分或材料,且因此可有助於減輕鋸切製程的負擔。此外,可將藉由雷射束移除的部分最小化,以使得測試圖案或對準標記能夠完美地或令人滿意地保留而不被移除。在實施方式中,與其中使用刀片的情形相比,當使用雷射束時,切割表面可能不粗糙而是平滑的。
作為總結及回顧,切割道可包括上面用於曝光製程的對準標記或者可包括用於在晶片區上對半導體裝置的電性性質及缺陷圖案進行監控以檢查製程是否正常實行的測試圖案。
對於根據一些實施例的半導體晶片,最外表面(或剖切表面)可被第一頂蓋層及埋入式介電圖案阻擋,且因此可能可有助於防止濕氣吸收或側向裂紋(來自剖切表面)。另外,分隔介電圖案可與主下部介電堆疊及邊緣下部介電堆疊間隔開,且因此可能可更有效地防止側向裂紋及濕氣吸收。據以,可達成具有增加的可靠性的半導體晶片及半導體封裝。
在根據實施例的製造半導體晶片的方法中,可防止側向裂紋及非劃切問題二者,以有助於提高良率。
一或多個實施例可提供一種具有增加的可靠性的半導體晶片。
一或多個實施例可提供一種具有增加的可靠性的半導體封裝。
一或多個實施例可提供一種能夠提高良率的半導體晶片製造方法。
在本文中已揭露示例性實施例,且儘管採用了特定用語,然而使用這些用語僅是為了自一般性及說明性的意義加以解釋而非用於限制目的。在一些情況中,在提出本申請案時對此項技術中具有通常知識者而言將顯而易見,除非另外具體地指明,否則結合具體實施例闡述的特徵、特性及/或元件可單獨使用或與結合其他實施例闡述的特徵、特性及/或元件組合使用。據以,熟習此項技術者應理解,在不背離以下申請專利範圍中所述本發明的精神及範圍的條件下可作出形式及細節上的各種改變。
1:基板
1a:第一表面
1b:第二表面
3:裝置層間介電層
5c:接觸插塞
5g:第一防護環圖案
7:下部介電堆疊
7e:邊緣下部介電堆疊
7m:主下部介電堆疊
9:下部配線圖案
9g:第二防護環圖案
9s:第一輔助圖案
10:下部金屬間介電層
11:下部通孔圖案
11g:第三防護環圖案
11s:第一輔助通孔圖案
12:第一上部通孔圖案
12g:第四防護環圖案
12s:第二輔助通孔圖案
13:第一上部金屬間介電層
14:子接墊
14g:第五防護環圖案
14s:第二輔助圖案
15:第二上部金屬間介電層
17:氫阻擋層
19:第三上部金屬間介電層
20:上部介電堆疊
20e:邊緣上部介電堆疊
20m:主上部介電堆疊
21:含金屬層
21p:接墊圖案
21s:第三輔助圖案
22:第二上部通孔圖案
22s:第三輔助通孔圖案
23:硬罩幕圖案
23L:硬罩幕層
25:第一頂蓋層
25bs:下部外側壁
25us:上部外側壁
25use:底端
27:埋入式介電層
27b:埋入式介電圖案
27bu、33u:頂表面
27s:分隔介電圖案
29:第二頂蓋層
31:第一上部鈍化層
33:第二上部鈍化層
35:上部鈍化層
37:上部結合接墊
39:保護層
40:第一下部鈍化層
42:第二下部鈍化層
44:下部鈍化層
46:下部結合接墊
100:半導體晶片
100a:第一半導體晶片/半導體晶片
100b:第二半導體晶片/半導體晶片
100c:第三半導體晶片/半導體晶片
100d:第四半導體晶片/半導體晶片
100e:第五半導體晶片/半導體晶片
1000:半導體封裝
A-A':線
BP:結合接墊
BR:斷裂區
CS:電路結構
DL:裝置層
DR:裝置區
ER:邊緣區
GS1:下部防護環結構/防護環結構
GS2:上部防護環結構/防護環結構
IL:配線層
ILE:邊緣配線結構
ILM:主配線結構
LI:下部配線層
MD:模具層
OP1:第一開口
OP2:第二開口
OP3:第三開口
PL:接墊層
PTR1:第一初步溝渠/初步溝渠
PTR2:第二初步溝渠/初步溝渠
RTR1:第一轉移溝渠
RTR2:第二轉移溝渠
SB:外部連接端子
SDR:階狀區
SR:切割道區
SS1:第一輔助圖案結構
SS2:第二輔助圖案結構
T1:第一厚度
T2:第二厚度
TL:貫穿介電層
TR:電晶體
TR1:第一溝渠
TR2:第二溝渠
TR3:第三溝渠
TSV:貫穿電極
UI:上部配線層
W:晶圓
藉由參照附圖詳細闡述示例性實施例,特徵對於熟習此項技術者而言將顯而易見,在附圖中:
圖1示出根據一些實施例的半導體裝置的平面圖。
圖2示出沿著圖1所示線A-A'截取的剖視圖。
圖3示出根據一些實施例的半導體封裝的剖視圖。
圖4示出晶圓的平面圖。
圖5A至圖5L示出製造圖2所示半導體晶片的方法中的階段的剖視圖。
1:基板
1a:第一表面
1b:第二表面
3:裝置層間介電層
5c:接觸插塞
5g:第一防護環圖案
7e:邊緣下部介電堆疊
7m:主下部介電堆疊
9:下部配線圖案
9g:第二防護環圖案
9s:第一輔助圖案
10:下部金屬間介電層
11:下部通孔圖案
11g:第三防護環圖案
11s:第一輔助通孔圖案
12:第一上部通孔圖案
12g:第四防護環圖案
12s:第二輔助通孔圖案
13:第一上部金屬間介電層
14:子接墊
14g:第五防護環圖案
14s:第二輔助圖案
15:第二上部金屬間介電層
17:氫阻擋層
19:第三上部金屬間介電層
20e:邊緣上部介電堆疊
20m:主上部介電堆疊
21p:接墊圖案
21s:第三輔助圖案
22:第二上部通孔圖案
22s:第三輔助通孔圖案
23:硬罩幕圖案
25:第一頂蓋層
25bs:下部外側壁
25us:上部外側壁
25use:底端
27:埋入式介電層
27b:埋入式介電圖案
27bu、33u:頂表面
29:第二頂蓋層
31:第一上部鈍化層
33:第二上部鈍化層
35:上部鈍化層
37:上部結合接墊
40:第一下部鈍化層
42:第二下部鈍化層
44:下部鈍化層
46:下部結合接墊
A-A':線
CS:電路結構
DL:裝置層
DR:裝置區
ER:邊緣區
GS1:下部防護環結構/防護環結構
GS2:上部防護環結構/防護環結構
IL:配線層
ILE:邊緣配線結構
ILM:主配線結構
LI:下部配線層
PL:接墊層
RTR1:第一轉移溝渠
SDR:階狀區
SS1:第一輔助圖案結構
SS2:第二輔助圖案結構
T1:第一厚度
T2:第二厚度
TL:貫穿介電層
TR:電晶體
TR1:第一溝渠
TSV:貫穿電極
UI:上部配線層
Claims (10)
- 一種半導體晶片,包括: 基板,包括裝置區及邊緣區; 裝置層與配線層,依序堆疊於所述基板上; 輔助圖案,在所述邊緣區上的所述配線層上; 第一頂蓋層,覆蓋所述輔助圖案的側壁、所述配線層的頂表面及所述配線層的側壁,所述第一頂蓋層包括上部外側壁及下部外側壁,所述下部外側壁與所述上部外側壁偏置開;以及 埋入式介電圖案,與所述第一頂蓋層的所述下部外側壁接觸且與所述第一頂蓋層的所述上部外側壁間隔開。
- 如請求項1所述的半導體晶片,其中所述埋入式介電圖案的頂表面處於與所述上部外側壁的底端的水平相同的水平處。
- 如請求項1所述的半導體晶片,其中: 所述配線層包括依序堆疊的下部介電堆疊與上部介電堆疊, 所述下部介電堆疊包括下部介電層, 所述上部介電堆疊包括上部介電層, 各所述下部介電層包含具有較氧化矽的介電常數小的介電常數的介電材料,且 各所述上部介電層包括具有較各所述下部介電層中包含的所述介電材料的所述介電常數大的介電常數的介電材料。
- 如請求項3所述的半導體晶片,其中: 所述下部介電堆疊包括: 主下部介電堆疊,覆蓋所述裝置區及所述邊緣區的與所述裝置區相鄰的一部分;以及 邊緣下部介電堆疊,在所述邊緣區上且與所述主下部介電堆疊間隔開,且 所述上部介電堆疊包括: 主上部介電堆疊,在所述主下部介電堆疊上;以及 邊緣上部介電堆疊,在所述邊緣下部介電堆疊上且與所述主上部介電堆疊間隔開。
- 如請求項4所述的半導體晶片,更包括在所述邊緣區上的在所述主下部介電堆疊中的防護環結構, 其中,當在平面圖中觀察時,所述防護環結構環繞所述裝置區。
- 如請求項4所述的半導體晶片,更包括在所述主下部介電堆疊與所述邊緣下部介電堆疊之間以及在所述主上部介電堆疊與所述邊緣上部介電堆疊之間的分隔介電圖案, 其中所述分隔介電圖案包含具有較各所述下部介電層中包含的所述介電材料的所述介電常數大的介電常數的介電材料。
- 如請求項1所述的半導體晶片,其中所述第一頂蓋層包含具有較所述埋入式介電圖案中包含的材料的密度大的密度的材料。
- 一種半導體晶片,包括: 基板,包括裝置區及邊緣區; 裝置層與配線層,依序堆疊於所述基板上; 分隔介電圖案,在與所述裝置區和所述邊緣區之間的邊界相鄰的同時穿過所述配線層; 輔助圖案,在所述邊緣區上的所述配線層上; 接墊圖案,在所述裝置區上的所述配線層上; 鈍化層,覆蓋所述接墊圖案及所述輔助圖案; 第一頂蓋層,覆蓋所述輔助圖案的側壁及所述配線層的側壁;以及 埋入式介電圖案,與所述第一頂蓋層的下部外側壁接觸, 其中: 所述埋入式介電圖案的頂表面形成自所述鈍化層的頂表面延伸的階狀區, 所述配線層包括依序堆疊的下部介電堆疊與上部介電堆疊, 所述下部介電堆疊中包含的介電材料具有較所述上部介電堆疊中包含的介電材料的介電常數小的介電常數, 所述輔助圖案包括測試圖案或對準標記,且 所述第一頂蓋層的密度大於所述埋入式介電圖案的密度。
- 如請求項8所述的半導體晶片,更包括在所述分隔介電圖案與所述配線層之間以及在所述分隔介電圖案與所述裝置層之間的第二頂蓋層, 其中所述第二頂蓋層包含與所述第一頂蓋層的材料相同的材料且具有與所述第一頂蓋層的厚度相同的厚度。
- 一種半導體封裝,包括: 第一半導體晶片; 第二半導體晶片,堆疊於所述第一半導體晶片上;以及 模具層,覆蓋所述第二半導體晶片的側向表面及所述第一半導體晶片的頂表面, 其中: 所述第二半導體晶片中的每一者包括第二基板及在所述第二基板下方的電路結構, 所述第二基板包括裝置區及環繞所述裝置區的邊緣區, 所述電路結構包括: 裝置層與配線層,依序堆疊於所述第二基板下方; 輔助圖案,在所述邊緣區上的所述配線層下方; 接墊圖案,在所述裝置區上的所述配線層下方; 鈍化層,覆蓋所述接墊圖案的底表面及所述輔助圖案的底表面; 第一頂蓋層,覆蓋所述輔助圖案的側壁及所述配線層的側壁;以及 埋入式介電圖案,與所述第一頂蓋層的上部外側壁接觸, 所述埋入式介電圖案的底表面形成自所述鈍化層的底表面延伸的階狀區,且 所述模具層對所述階狀區進行填充。
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