TWI540616B - 晶圓級晶片陣列及其製造方法 - Google Patents

晶圓級晶片陣列及其製造方法 Download PDF

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TWI540616B
TWI540616B TW103114054A TW103114054A TWI540616B TW I540616 B TWI540616 B TW I540616B TW 103114054 A TW103114054 A TW 103114054A TW 103114054 A TW103114054 A TW 103114054A TW I540616 B TWI540616 B TW I540616B
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wafer
wafers
epitaxial
semiconductor wafer
line
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TW103114054A
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TW201442067A (zh
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張峻維
陳瑰瑋
鄭家明
林佳昇
陳鍵輝
劉滄宇
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精材科技股份有限公司
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Description

晶圓級晶片陣列及其製造方法
本發明係關於一種晶片陣列及其製造方法，且特別是有關於一種晶圓級晶片陣列及其製造方法。
晶圓級封裝(Wafer Level Packaging；WLP)是IC封裝方式的一種，係指晶圓上所有晶片生產完成後，直接對整片晶圓上所有晶片進行封裝製程及測試，完成之後才切割製成單顆晶片封裝體的晶片封裝方式。如第1A圖所示，在半導體晶圓10上製作完成各晶片之封裝製程後，再沿著各晶片封裝體100交界處之切割道SL，將各晶片所製作完成之各晶片封裝體100分割開來。進一步參照第1A圖之局部放大之第1B圖，以及第1B圖中沿AA’線剖面之第1C圖所示，半導體晶圓10上彼此相鄰之二晶片封裝體100，晶片封裝體100之間交界處具有晶片間溝槽106，以供切割道SL通過以分割兩晶片封裝體100，一般而言，於切割道SL通過區域，即晶片間溝槽106，係由半導體晶圓10背面向正面蝕刻後的空曠區域，以便後續切割刀下刀並將彼此相鄰之二晶片封裝體100順利分割開來。然而，在現今晶片內部線路集成度不斷提高的趨勢下，晶片封裝體100中可配線的區域亦應對應增加，否則將帶來內部線路集成度過高而造成的訊 號干擾或是晶片內部線路短路等問題。
本發明係提供一種晶圓級晶片陣列、一種晶片封裝體以及一種晶圓級晶片加工之製造方法，各晶片之間的晶片間溝槽具有特殊的地形(topography)，在不影響後續晶片分割製程的前提之下，使各晶片內部有一部分線路得以配線於晶片邊緣處的晶片間溝槽並被妥善保護起來，以爭取單一晶片內更多的可配線空間，避免上述因應內部線路集成度過高，可能造成的訊號干擾或是短路等問題。
本發明之一態樣係提出一種晶圓級晶片陣列，包含一半導體晶圓以及至少一外延線保護塊，該半導體晶圓具有至少二晶片相鄰排列以及一承載層，各該晶片具有一上表面及一下表面，且包含至少一電子元件於該上表面，該承載層覆蓋於各該晶片之上表面；該至少一外延線保護塊係配置於該承載層之下且位於該至少二晶片之間，其中，該外延線保護塊內部具有至少一外延線。
在本發明之一實施例中，該外延線之一部分通過該承載層與該電子元件電性連接。
在本發明之一實施例中，該外延線係一獨立線路不與該電子元件電性連接。
在本發明之一實施例中，該晶圓級晶片陣列進一步包含至少一切割道於該至少二晶片之間，其中，該切割道不經過該外延線。
在本發明之一實施例中，各該晶片進一步包含一連接墊結構、複數個孔洞、一絕緣層、一導電層以及一封裝層，該連接墊結構電性連接於該電子元件；該些孔洞自該晶片之 該下表面朝該上表面延伸，接觸該連接墊結構且露出該連接墊結構之一部分；該絕緣層自該半導體晶片之該下表面朝該上表面延伸，部分的該絕緣層位於該些孔洞之中；該導電層位於該絕緣層下且自該半導體晶片之該下表面朝該上表面延伸，部分的該導電層位於該些孔洞之中，其中，位於該些孔洞內的該導電層係透過該連接墊結構電性連接該電子元件；該封裝層形成於該導電層之下。
在本發明之一實施例中，該外延線保護塊的厚度與該晶片的厚度比係0.05~0.1。
本發明之另一態樣係提出一種晶片封裝體，其包含一承載層、一半導體晶片、複數個孔洞、一絕緣層、一導電層、一封裝層、至少一外延線保護塊、至少一外延線，該承載層具有一中央區以及一周邊區，該中央區係由該周邊區所圈繞；該半導體晶片對應於該中央區並配置於該承載層下方，具有一上表面及一下表面，且具有至少一電子元件設置於該上表面且為該承載層所覆蓋、以及至少一連接墊結構電性連接於該電子元件；該些孔洞自該半導體晶片之該下表面朝該上表面延伸，接觸該連接墊結構且露出該連接墊結構之一部分；該絕緣層自該半導體晶片之該下表面朝該上表面延伸，部分的該絕緣層位於該些孔洞之中；該導電層位於該絕緣層下且自該半導體晶片之該下表面朝該上表面延伸，部分的該導電層位於該些孔洞之中，其中，位於該些孔洞內的該導電層係透過該連接墊結構電性連接該電子元件；該封裝層，形成於該導電層之下；該至少一外延線保護塊對應於該周邊區配置於該承載層下方；而該至少一外延線配置於該外延線保護塊內。
本發明之又一態樣係提出晶圓級晶片加工之製造方法，包含提供一半導體晶圓，其上具有彼此相鄰之至少二晶片以及一承載層覆蓋該至少二晶片，各該晶片具有至少一電子元件以及至少一外延線，該外延線配置於該半導體晶圓內之至少一外延線保護區；微影蝕刻該半導體晶圓的背面，以在該至少二晶片之間形成至少兩個凹部；以及全面蝕刻該半導體晶圓的背面，使在該至少二晶片之間之該至少兩個凹部擴大並彼此結合成一晶片間溝槽，以使該外延線保護區暴露出來形成至少一外延線保護塊。
在本發明之一實施例中，在全面蝕刻該半導體晶圓的背面步驟之後，進一步包含依序形成一絕緣層、一導電層以及至少一焊球於該半導體晶圓的背面，以完成該至少二晶片之封裝體；以及沿該至少二晶片之間之一切割道於該半導體晶圓的背面切割，以分離該至少二晶片之封裝體，其中，該切割道不經過該外延線。
在本發明之一實施例中，微影蝕刻該半導體晶圓的背面之步驟係在該至少二晶片之間形成兩個該凹部；在全面蝕刻該半導體晶圓的背面之步驟則係形成一個該外延線保護塊；而在沿該至少二晶片之間之一切割道於該半導體晶圓的背面切割之步驟中，該切割道通過該外延線保護塊。
在本發明之另一實施例中，微影蝕刻該半導體晶圓的背面之步驟係在該至少二晶片之間形成三個該凹部，在全面蝕刻該半導體晶圓的背面之步驟中形成二個該外延線保護塊，在沿該至少二晶片之間之一切割道於該半導體晶圓的背面切割之步驟中，該切割道由該二個外延線保護塊之間通過而不通過任一該外延線保護塊。
10‧‧‧半導體晶圓
100‧‧‧晶片陣列
102‧‧‧半導體晶圓
102a‧‧‧晶片
102a1‧‧‧電子元件
102a3‧‧‧連接墊結構
102a4‧‧‧孔洞
102a5‧‧‧絕緣層
102a6‧‧‧導電層
102a7‧‧‧封裝層
102a8‧‧‧焊球
102a9‧‧‧焊線
104‧‧‧外延線保護塊
102b‧‧‧承載層
104a‧‧‧外延線
104’‧‧‧外延線保護區
106‧‧‧晶片間溝槽
108‧‧‧凹部
112‧‧‧承載基板
206‧‧‧晶片間溝槽
800‧‧‧晶片陣列
802‧‧‧半導體晶圓
802a‧‧‧晶片
802a1‧‧‧電子元件
804a‧‧‧外延線
802b‧‧‧承載層
804‧‧‧外延線保護塊
804’‧‧‧外延線保護區
806‧‧‧晶片間溝槽
808‧‧‧凹部
US‧‧‧上表面
812‧‧‧承載基板
SL‧‧‧切割道
DS‧‧‧下表面
本發明之上述和其他態樣、特徵及其他優點參照說明書內容並配合附加圖式得到更清楚的了解，其中：第1A圖顯示半導體晶圓上晶片陣列排列以及各晶片之間切割道SL相對位置。
第1B圖顯示第1A圖的局部。
第1C圖顯示第1B圖中沿AA’線之剖面圖。
第2A圖顯示本發明第一實施例之晶圓級晶圓陣列的局部。
第2B圖顯示第2A圖中沿AA’線之剖面圖。
第2C圖顯示本發明另一實施例之剖面圖。
第2D圖顯示本發明又一實施例之剖面圖。
第2E圖顯示本發明另一實施例之剖面圖。
第2F圖顯示本發明另一實施例之剖面圖。
第2G圖顯示本發明另一實施例之剖面圖。
第2H圖顯示本發明另一實施例之剖面圖。
第3圖顯示本發明第一實施例之單一晶片(封裝體)的局部。
第4圖至第7圖係本發明第一實施例的晶圓級晶片加工之製造方法示意圖。
第8A圖顯示本發明第二實施例之晶圓級晶圓陣列的局部。
第8B圖顯示第8A圖中沿AA’線之剖面圖。
第9圖顯示本發明第二實施例之單一晶片(封裝體)的局部。
第10圖至第13圖係本發明第二實施例的晶圓級晶片加工之製造方法示意圖。
請同時參照第2A圖以及第2B圖，第2A圖係本發明第一實施例的晶圓級晶片陣列100局部上視圖，而第2B圖係第2A圖中AA’線之剖面示意圖。
在本發明第一實施例的晶圓級晶片陣列100中，包含半導體晶圓102以及至少一外延線保護塊104，如第2A圖中本實施例晶圓級晶片陣列100的局部上視圖所示，半導體晶圓102具有至少二個彼此相鄰排列的晶片102a，而外延線保護塊104係位於上述彼此相鄰排列的晶片102a之間，進一步參照第2A圖中沿AA’線剖面之第2B圖所示，半導體晶圓102尚具有承載層102b，而各晶片102a具有一上表面US及一下表面DS，各晶片102a包含電子元件102a1位於各晶片102a之上表面US處，且由承載層102b所覆蓋。其中，承載層102b覆蓋於各晶片102a的上表面US以保護各晶片102a內所有元件，所使用的材料例如可以是氧化矽(silicon oxide)、氮化矽(silicon nitride)或氮氧化矽(silicon ox/nitride)等絕緣材料，並提供隔絕空氣或是應力緩衝等功能，但不以此為限；電子元件102a1例如可以是積體電路元件、光電元件、微機電(micro-electromechanical)元件或一表面聲波(SAW)元件，但亦不以此為限。同時參照第2A圖以及第2B圖所示，外延線保護塊104係位於相鄰的兩晶片102a之間，即晶片102a的邊緣處，值得注意的是，外延線保護塊104內部具有一條或複數條外延線104a，依不同設計需求，外延線104a可以是不與電子元件102a1電性連接之獨立線路，或者與電子元件102a1電性連接。如第2B圖所示，外延線104a係完整包覆於外延線保護塊104中而不暴露出來，而外延線104a所使用的材料例如可以是鋁 (aluminum)、銅(copper)或鎳(nickel)或其他合適的導電材料，但不以此為限。
請繼續參照第2A圖以及第2B圖所示，在本發明之第一實施例中，位於晶片102a之間的切割道SL係經過外延線保護塊104但不經過外延線104a，換言之，即可切割位於晶片102a之間的外延線保護塊104，以將相鄰之晶片102a分割，同時外延線104a仍被包覆於分割後分屬兩側之外延線保護塊104中而不暴露出來，其中，為使此晶片分割順利進行，外延線保護塊104的厚度h1例如可以僅有晶片102a厚度h2的二十分之一至十分之一，如此便使切割刀可輕易沿切割道SL將外延線保護塊104一分為二，而形成如第3圖所示之單一晶片102a以及部分的外延線保護塊104，其中外延線保護塊104內部具有外延線104a。
此外，各晶片102a例如可以封裝成為第3圖中所例示之晶片封裝體100，其中晶片102a進一步包含連接墊結構102a3、複數個孔洞102a4、絕緣層102a5、導電層102a6、封裝層102a7以及焊球102a8，但不以此為限，其中，連接墊結構102a3電性連接電子元件102a1且連接墊結構102a3係自晶片102a的上表面US朝晶片102的下表面DS延伸。如第2B圖所示，連接墊結構102a3與電子元件102a1之間具有電性連接，連接墊結構102a3例如可以是內連線結構(interconnection structure)，由晶片102a的上表面US朝晶片102a的下表面DS延伸連接至位於晶片102a之內部，使位於晶片102a之上表面US的電子元件102a1和晶片102a內部藉由連接墊結構102a3而具有電性導通，但不以此方式為限。請繼續參照第2B圖，複數個孔洞102a4係自晶片102a 的下表面DS朝晶片102a的上表面US延伸而接觸位於晶片102a內部之連接墊結構102a3，並且使晶片102a內部之連接墊結構102a3具有一部分之露出，換言之，複數個孔洞102a4係直通矽晶穿孔(Through-Silicon Via,TSV)待後續導電層102a6填入後，作為晶片102a的下表面DS至晶片102a之上表面US的電子元件102a1之垂直電性導通路徑。請繼續參照第2B圖，於晶片102a的下表面DS覆蓋有絕緣層102a5，所使用的材料可以是氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(silicon ox/nitride)或其它合適之絕緣材料，絕緣層102a5除覆蓋晶片102a的下表面DS，尚自晶片102a的下表面DS之複數個孔洞102a4的開口，朝晶片102a的上表面US延伸，使部分絕緣層102a5位於複數個孔洞102a4的孔壁上。導電層102a6位於絕緣層102a5下方，所使用的材料例如是鋁(aluminum)、銅(copper)或鎳(nickel)或其他合適的導電材料，導電層102a6具有特殊的圖案(pattern)，即在上述導電材料沉積後，會再以微影蝕刻的方式圖案化，於絕緣層102a5下方僅留下對應於複數個孔洞102a4以及晶片102a下表面DS的金屬走線設計等位置上之導電層102a6，導電層102a6亦自晶片102a之下表面DS朝上表面US延伸，使部分的導電層102a6位於複數個孔洞102a4中，並將複數個孔洞102a4填滿，位於複數個孔洞102a4中的導電層102a6因接觸位於晶片102a內部的連接墊結構102a3之露出部分，故可藉由連接墊結構102a3電性導通電子元件102a1。如第2B圖所示，封裝層102a7係形成於導電層102a6下方，其中，封裝層102a7所使用的材料可以是於半導體晶片封裝技術中所常用的綠漆(solder mask)， 封裝層102a7具有開口以露出部分導電層102a6，使露出之部分導電層102a6和後續形成之焊球102a8接觸而具有電性導通，封裝層102a7可以避免焊球102a8彼此接觸而短路，同時亦具有保護導電層102a6的功能。最後，至少一焊球102a8設置於封裝層102a7的下方，並透過前述封裝層102a7之開口接觸露出部分之導電層102a6，使露出之部分導電層102a6和焊球102a8接觸而具有電性導通，焊球102a8所使用的材料例如可以是錫(Sn)、或其他適合焊接之導電材料。此外在本發明另一些實施例中，亦可如第2C圖至第2H所示，晶片102a進一步包含的連接墊結構102a3配置於切割道SL通過之周邊區域，由配置於切割道SL通過周邊區域之孔洞102a4暴露出來，搭配絕緣層102a5、導電層102a6以及封裝層102a7，再由焊球102a8(如第2C圖、第2D圖以及第2G圖)或是焊線102a9(如第2E圖、第2F圖以及第2H圖)作為對外之電性連接。
如前所述，一般而言於切割道SL通過之周邊區域，即第1C圖中晶片間溝槽206，係由半導體晶圓10背面向正面蝕刻後的空曠區域，以便後續切割刀下刀並將相鄰兩晶片102a順利分割開來，然而在現今晶片內部線路集成度不斷提高的趨勢下，晶片中可配線的區域亦應對應增加，在本發明第一實施例中，各晶片102a之間的晶片間溝槽206具有特殊的地形，即在各晶片102a之間尚具有一厚度較薄的外延線保護塊104，在不影響後續晶片分割製程的前提之下，使一部分線路，即外延線104a得以配線於晶片邊緣處的晶片間溝槽的外延線保護塊104內，並被妥善保護起來。以外延線104a與電子元件102a1具有電性連接的情況來說，如 此可以爭取更多的可配線空間，避免上述因線路集成度過高，可能造成的訊號干擾或是短路等問題；或以外延線104a不與電子元件102a1具有電性連接的情況來說，可視需求單獨設計外延線104a其他的特殊功能。
請繼續參照第4圖至第7圖，第4圖至第7圖係本發明第一實施例的晶圓級晶片加工之製造方法，其中各步驟中所形成結構之示意圖，為清楚說明並方便與前文對照，第4圖至第7圖均如同第2A圖與第2B圖，以相鄰兩片晶片102a作為例示說明單位，但不以此為限，即以下如第4圖至第7圖中的結構示意圖，可視需求類推適用至整片晶圓中所有晶片102a之間。
首先請參照第4圖，在第4圖中顯示本發明第一實施例100之局部側視圖(可對照第2A圖中本實施例晶圓級晶片陣列100的局部上視圖)，提供一半導體晶圓102，半導體晶圓102具有至少二個彼此相鄰排列的晶片102a，亦如同第2A圖中沿AA’線剖面之第2B圖所示，半導體晶圓102尚具有承載層102b，而各晶片102a具有一上表面US及一下表面DS，在各晶片102a包含電子元件102a1以及外延線104a，電子元件102a1以及外延線104a均位於各晶片102a之上表面US處且均由承載層102b所覆蓋，外延線104a例如可以電性連接電子元件102a1或是不與電子元件102a1電性連接之獨立線路，如第4圖所示，外延線104a位於二晶片102a之間，換言之，外延線104a係配置於切割道SL附近，其中值得注意的是，兩晶片102a各自之外延線104a均配置於外延線保護區104’內部且各自之外延線104a不超過各晶片102a之預定邊界(即切割道SL)，外延線保護區104’ 具有一寬度w2，w2的實際寬度可視外延線104a在半導體晶圓102內佈線範圍需求不同而做適度的設計調整，此外，可選擇性地貼附承載基板112於承載層102b上以作為後續製作過程中，半導體晶圓102中各晶片102a位置固定及支撐，其中承載基板112例如可以是玻璃基板，但不以此為限。接著，微影蝕刻該半導體晶圓的背面，以在二相鄰晶片102a之間形成兩個凹部108，如第4圖所示，所形成之兩個凹部108的距離為w1，其中，w1實質上大於w2，w1的實際寬度係配合前述w2的設計，以微影蝕刻的方式做精準的調控，即可製得第4圖中所顯示的本發明第一實施例之局部。
接著請參照第5圖，全面蝕刻第4圖中所顯示的本發明第一實施例之局部半導體晶圓102的背面，使在兩晶片102a之間原本的兩個凹部108擴大並彼此結合成一個晶片間溝槽206，並且使該外延線保護區104’完全暴露出來，形成一外延線保護塊104，其中值得注意的是，外延線104a在經過此一全面蝕刻步驟後，仍完整包覆於承載層102b以及外延線保護塊104之內部而不暴露出來，其中，晶片102a經本步驟之全面蝕刻後的厚度係h2，而外延線保護塊104經本步驟之全面蝕刻後的厚度則係h1，為求後續分割各晶片102a能順利進行，h1可以製作為h2的十分之一到二十分之一，其製作細節包括選定適當的蝕刻製程參數，包含蝕刻劑以及蝕刻時間等，針對不同設計可採取不同的全面蝕刻方式對應之，本發明第一實施例之製造方法的特徵在於，藉由前述之微影蝕刻搭配本步驟的全面蝕刻，即可使本發明第一實施例之晶片間溝槽206中形成特殊的地形(h2大於 h1)，一般而言，形成此一具有高低差溝槽通常需要兩步驟的微影蝕刻製程搭配方可完成，然而在本發明第一實施例的製造方法中，卻是利用蝕刻製程常見的負載效應(loading effect)製作出如第5圖所示之晶片間溝槽206中具有高低差的地形。所謂負載效應(loading effect)是指當被蝕刻材質裸露在反應氣體電漿或溶液時，裸露面積較大者蝕刻速率較裸露面積較小者為慢的情形，如同第4圖所示，本發明第一實施例之製造方法先以微影蝕刻的方式，在兩相鄰晶片102a之間形成了兩個凹部108，即造成位於兩個凹部108之間的半導體晶圓102背面裸露面積，大於位於兩個凹部108之外的半導體晶圓102背面裸露面積，據此，於本步驟的全面蝕刻製程中，位於兩個凹部108之間的半導體晶圓102背面被蝕刻的速度會快於位於兩個凹部108之外的半導體晶圓102背面，如此便可形成如同前述h2大於h1的特殊地形，而不需要另一道微影蝕刻製程，據此，本發明第一實施例之製造方法較傳統兩道微影蝕刻的方式，不但製程更為簡便，同時亦省去傳統兩步驟的微影蝕刻製程中，另一道光罩之龐大成本。
此外，本發明第一實施例之製造方法亦可進一步將各晶片102a製作為晶片封裝體，如第6圖所示，其中在全面蝕刻半導體晶圓102的背面以形成第5圖之結構之後，進一步依序形成絕緣層102a5、導電層102a6、封裝層102a7以及至少一焊球102a8於半導體晶圓102的背面，以完成二晶片102a之封裝體，而上述各層之相對位置以及連結關係已如前述，在此即不重複且晶片封裝體的結構亦不以此為限。在半導體晶圓102上各晶片102a均完成晶片封裝體結 構後，沿二晶片102a之間之切割道SL於該半導體晶圓102的背面切割，以分離二晶片之封裝體，其中值得注意的是，切割道SL不經過外延線104a，換句話說，分割完成後的各晶片封裝體所具有的外延線104a仍被完整的包覆於分割後外延線保護塊104內部。
請繼續參照第8A圖以及第8B圖，第8A圖係本發明第二實施例之晶圓級晶片陣列的局部放大上視圖，而第8B圖係第8A圖中AA’線之剖面示意圖。
在本發明第二實施例的晶圓級晶片陣列800中，包含半導體晶圓802以及至少一外延線保護塊804，如第8A圖中本實施例晶圓級晶片陣列800的局部上視圖所示，半導體晶圓802具有至少二個彼此相鄰排列的晶片802a，而外延線保護塊804係位於上述彼此相鄰排列的晶片802a之間，再參照第8B圖所示，半導體晶圓802尚具有承載層802b，而各晶片802a具有一上表面US及一下表面DS，在各晶片802a包含電子元件802a1位於各晶片802a之上表面US處且由承載層802b所覆蓋。其中，承載層802b覆蓋於各晶片802a的上表面US以保護各晶片802a內所有元件，所使用的材料例如可以是氧化矽(silicon oxide)、氮化矽(silicon nitride)或氮氧化矽(silicon ox-nitride)等絕緣材料，並提供隔絕空氣或是應力緩衝等功能，但不以此為限；電子元件802a1例如可以是積體電路元件、光電元件、一微機電(micro-electromechanical)元件或一表面聲波(SAW)元件，但亦不以此為限。
參照第8A圖以及第8B圖所示，兩塊外延線保護塊804係位於相鄰的兩晶片802a之間，即晶片802a的邊緣處， 值得注意的是，外延線保護塊804內部具有一條或複數條外延線804a，依不同需求可設計為不與電子元件802a1電性連接的獨立電路，或者是與電子元件802a1電性連接，如第8B圖所示，外延線804a係位於二晶片802a之間，換言之，外延線804a係配置於切割道SL附近之晶片802a的邊緣，且為外延線保護塊804完整包覆而不暴露出來。外延線804a所使用的材料例如可以是鋁(aluminum)、銅(copper)或鎳(nickel)或其他合適的導電材料，但不以此為限。
請繼續參照第8A圖以及第8B圖所示，在本發明之第二實施例中，位於晶片802a之間的切割道SL係由兩塊外延線保護塊804之間通過，換言之，本實施例係在不切割到外延線保護塊804的情況下，即可將相鄰之晶片102a分割，據此，各外延線804a被包覆於各自之外延線保護塊804中而不暴露出來，然而，雖然本實施例不須切割到外延線保護塊804，為使分割刀順利下刀，外延線保護塊804的厚度h1例如可以僅有晶片802a厚度h2的二十分之一至十分之一，如此便可使切割刀有足夠空間下刀，在不傷害到外延線保護塊804的情況下，沿切割道SL分割兩晶片802a，而形成如第9圖所示之單一晶片802a以及外延線保護塊804。
此外，各晶片802a亦可以是第8B圖以及第9圖中所例示之晶片封裝體，其進一步包含連接墊結構102a3、複數個孔洞102a4、絕緣層102a5、導電層102a6、封裝層102a7以及焊球102a8，但不以此為限，其中上述各元件之標號、材料以及連接關係同前本發明第一實施例所述，在此即不重複說明。
一般而言，於切割道SL通過之周邊區域，即第8A 圖中晶片間溝槽806，係由半導體晶圓10背面向正面蝕刻後的空曠區域，以便後續切割刀下刀並將兩相鄰晶片封裝體802a順利分割開來，然而在現今晶片內部線路集成度不斷提高的趨勢下，晶片中可配線的區域亦應對應增加，在本發明第二實施例中，各晶片802a之間的晶片間溝槽806具有特殊的地形，即在各晶片802a之間具有兩塊厚度較薄的外延線保護塊804，且此兩塊外延線保護塊804的位置避開切割道所經之處，如此便可在不影響後續晶片分割製程的前提之下，使外延線804a得以配線於晶片間溝槽806之外延線保護塊804並被妥善保護起來，以外延線804a與電子元件802a1具有電性連接的情況來說，如此可爭取單一晶片內更多的可配線空間，避免上述因內部線路集成度過高，可能造成的訊號干擾或是短路等問題；或以外延線804a不與電子元件802a1具有電性連接的情況來說，可視需求單獨設計外延線804a其他的特殊功能。
請繼續參照第10圖至第13圖，第10圖至第13圖係本發明第二實施例的晶圓級晶片加工之製造方法，其中各步驟中所形成結構之示意圖，為清楚說明並方便與前文對照，第10圖至第13圖均如同第8A圖與第8B圖，以相鄰兩片晶片802a作為例示說明單位，但不以此為限，即以下如第10圖至第13圖中的結構示意圖，可視需求類推適用至整片晶圓中所有晶片802a之間。
首先請參照第10圖，在第10圖中顯示本發明第二實施例之局部(如同第8A圖中本實施例晶圓級晶片陣列800的局部上視圖所示)，提供一半導體晶圓802，半導體晶圓802具有至少二個彼此相鄰排列的晶片802a，亦如同第8A 圖中沿AA’線剖面之第8B圖所示，半導體晶圓802尚具有承載層802b，而各晶片802a具有一上表面US及一下表面DS，在各晶片802a包含電子元件802a1以及外延線804a，電子元件802a1以及外延線804a均位於各晶片802a之上表面US處且均由承載層802b所覆蓋，外延線804a係電性連接電子元件802a1之晶片802a內部線路的一部分，如第10圖所示，外延線804a通過承載層802b向二晶片802a之間延伸，換言之，外延線804a係由晶片802a中電子元件802a1往切割道SL附近之晶片802a的邊緣延伸之導線，此外，可選擇性地貼附承載基板812於承載層802b上以作為後續製作過程中，半導體晶圓802中各晶片802a位置固定及支撐，其中承載基板812例如可以是玻璃基板，但不以此為限。其中值得注意的是，兩晶片802a各自之外延線804a係各自延伸至半導體晶圓802內之兩個外延線保護區804’內部且各自之外延線804a不延伸超過各該晶片802a之預定邊界(即切割道SL)，外延線保護區804’具有一寬度w3，w3的實際寬度可視外延線804a在半導體晶圓802內佈線範圍需求不同而做適度的設計調整。接著，微影蝕刻該半導體晶圓的背面，以在二相鄰晶片802a之間形成三個凹部808，如第10圖所示，所形成之三個凹部808兩兩之間的距離為w4，其中，w4實質上大於w3，w4的實際寬度係配合前述w3的設計，以微影蝕刻的方式做精準的調控，即可製得第10圖中所顯示的本發明第一實施例之局部。此外為便於說明，本實施例所例示係對稱於切割道SL之兩塊大小相同之外延線保護塊804，但不限於此，即可視實際應用需求做對應之不對稱設計，只需搭配適當的微影蝕刻製程調整即可。
接著請參照第11圖，全面蝕刻第10圖中所顯示的本發明第二實施例之局部半導體晶圓802的背面，使在兩晶片802a之間原本的三個凹部808擴大並彼此結合成一個晶片間溝槽806，並且使兩個外延線保護區804’完全暴露出來，形成兩塊外延線保護塊804，其中值得注意的是，各晶片802a之外延線804a在經過此一全面蝕刻步驟後，仍各自完整包覆於承載層802b以及各自之外延線保護塊804之內部而不暴露出來，其中，晶片802a經本步驟之全面蝕刻後的厚度係h2，而外延線保護塊804經本步驟之全面蝕刻後的厚度則係h1，本發明第二實施例和前述之第一實施例不同之處在於：藉由微影蝕刻先形成三個凹部，即可在下一步驟之全面蝕刻完成後，形成兩塊獨立彼此不接觸的外延線保護塊804，如此便使後續切割製程中的切割道由外延線保護塊804之間通過，而不切割到任一外延線保護塊804。然而為求後續分割各晶片102a能順利進行，h1還是可以製作為h2的十分之一到二十分之一，以使切割刀有充足空間下刀進行切割，其製作細節包括選定適當的蝕刻製程參數，包含蝕刻劑以及蝕刻時間等，針對不同設計可採取不同的全面蝕刻方式對應之。而本發明第二實施例之製造方法和前述之第一實施例具有相同特徵，即藉由前述之微影蝕刻搭配本步驟的全面蝕刻，即可使本發明第二實施例之晶片間溝槽806中形成特殊的地形(h2大於h1)，一般而言，形成此一具有高低差溝槽通常需要兩步驟的微影蝕刻製程搭配方可完成，然而在本發明第二實施例的製造方法中，卻是利用蝕刻製程常見的負載效應(loading effect)製作出如第11圖所示之晶片間溝槽806中具有高低差的地形。所謂負載效應(loading effect)是指當被蝕刻材質裸露在反應氣體電漿或溶液時，裸露面積較大者蝕刻速率較裸露面積較小者為慢的情形，如同第10圖所示，本發明第二實施例之製造方法先以微影蝕刻的方式，在兩相鄰晶片802a之間形成了三個凹部808，即造成位於三個凹部808兩兩之間的半導體晶圓102背面裸露面積，大於其他部分的半導體晶圓102背面裸露面積，據此，於本步驟的全面蝕刻製程中，位於三個凹部808兩兩之間的半導體晶圓102背面被蝕刻的速度會快於其他部分的半導體晶圓102背面，如此便可形成如同前述h2大於h1的特殊地形，而不需要另一道微影蝕刻製程，據此，本發明第二實施例之製造方法較傳統兩道微影蝕刻的方式，不但製程更為簡便，同時亦省去傳統兩步驟的微影蝕刻製程中，另一道光罩之龐大成本。
此外，本發明第二實施例之製造方法亦可進一步將各晶片802a製作為晶片封裝體，如第12圖所示，其中在全面蝕刻半導體晶圓802的背面以形成第11圖之結構之後，進一步依序形成絕緣層102a5、導電層102a6、封裝層102a7以及至少一焊球102a8於半導體晶圓102的背面，以完成二晶片102a之封裝體，而上述各層之相對位置以及連結關係如同前述，故在此使用相同元件符號亦不重複描述。在半導體晶圓802上各晶片802a均完成晶片封裝體結構後，沿二晶片802a之間之切割道SL於該半導體晶圓802的背面切割，以分離二晶片之封裝體，其中值得注意的是，切割道SL係由外延線保護塊804之間經過，如此更可確保外延線804a於切割製程中不至損傷，換句話說，分割完成後的各晶片封裝體所具有的外延線804a仍被完整包覆於外延線保 護塊804內部。
最後要強調的是，本發明所揭示晶圓級晶片陣列、晶片封裝體以及晶圓級晶片加工之製造方法，各晶片之間的晶片間溝槽具有特殊的地形，使各晶片內部有一部分線路得以配線於晶片邊緣處的晶片間溝槽，並由該處晶圓經蝕刻後所形成之厚度較薄的保護塊妥善保護起來，以爭取單一晶片內更多的可配線空間，避免上述因應內部線路集成度過高，可能造成的訊號干擾或是短路等問題，同時，因為保護塊厚度較薄，所以能在不影響後續分割製程的前提之下，順利分割晶圓內之各晶片或是各晶片封裝體，且在製造方法上應用微影蝕刻搭配全面蝕刻，即可完成上述具有保護塊的晶片間溝槽特殊地形，具有製程簡化以及成本低廉之功效。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧晶圓級晶片陣列
102a‧‧‧晶片
102‧‧‧半導體晶圓
102a4‧‧‧孔洞
102a1‧‧‧電子元件
102a6‧‧‧導電層
102a3‧‧‧連接墊結構
102a8‧‧‧焊球
102a5‧‧‧絕緣層
104‧‧‧外延線保護塊
102a7‧‧‧封裝層
104a‧‧‧外延線
102b‧‧‧承載層
US‧‧‧上表面
206‧‧‧晶片間溝槽
DS‧‧‧下表面

Claims (23)

  1. 一種晶圓級晶片加工之製造方法，包含：提供一半導體晶圓，其上具有彼此相鄰之至少二晶片以及一承載層覆蓋該至少二晶片，各該晶片具有至少一電子元件以及至少一外延線配置於該半導體晶圓內之至少一外延線保護區；微影蝕刻該半導體晶圓的背面，以在該至少二晶片之間形成至少兩個凹部；以及全面蝕刻該半導體晶圓的背面，使在該至少二晶片之間之該至少兩個凹部擴大並彼此結合成一晶片間溝槽，以使該外延線保護區暴露出來形成至少一外延線保護塊。
  2. 如請求項1的晶圓級晶片加工之製造方法，其中在全面蝕刻該半導體晶圓的背面步驟之後，進一步包含：依序形成一絕緣層、一導電層、一封裝層以及至少一焊球於該半導體晶圓的背面，以完成該至少二晶片之封裝體；以及沿該至少二晶片之間之一切割道於該半導體晶圓的背面切割，以分離該至少二晶片之封裝體，其中，該切割道不經過該外延線。
  3. 如請求項2的晶圓級晶片加工之製造方法，其中在微影蝕刻該半導體晶圓的背面之步驟中，在該至少二晶片之間形成兩個該凹部，在全面蝕刻該半導體晶圓的背面之步驟中形成一個該外延線保護塊，在沿該至少二晶片之間之一切割道於該半導體晶圓的背面切割之步驟中，該切割道通過該 外延線保護塊。
  4. 如請求項2的晶圓級晶片加工之製造方法，其中在微影蝕刻該半導體晶圓的背面之步驟中，在該至少二晶片之間形成三個該凹部，在全面蝕刻該半導體晶圓的背面之步驟中形成二個該外延線保護塊，在沿該至少二晶片之間之一切割道於該半導體晶圓的背面切割之步驟中，該切割道由該二個外延線保護塊之間通過而不通過任一該外延線保護塊。
  5. 如請求項1的晶圓級晶片加工之製造方法，其中該外延線保護塊的厚度與該晶片的厚度比係0.05~0.1。
  6. 如請求項1的晶圓級晶片加工之製造方法，其中在提供一半導體晶圓之步驟和微影蝕刻該半導體晶圓的背面之步驟之間，進一步包含：貼附一承載基板於該承載層上。
  7. 如請求項6的晶圓級晶片加工之製造方法，其中該承載基板係一玻璃基板。
  8. 如請求項1的晶圓級晶片加工之製造方法，其中該電子元件包括一積體電路元件、一光電元件、一微機電(micro-electromechanical)元件或一表面聲波(SAW)元件。
  9. 如請求項1的晶圓級晶片加工之製造方法，其中該 承載層包括氧化矽、氮化矽或氮氧化矽。
  10. 一種晶圓級晶片陣列，包含：一半導體晶圓，具有至少二晶片相鄰排列以及一承載層，各該晶片具有一上表面及一下表面，且包含至少一電子元件於該上表面，該承載層覆蓋各該晶片之上表面；以及至少一外延線保護塊，配置於該承載層之下且位於該至少二晶片之間，該外延線保護塊之厚度小於該晶片之厚度，其中，該外延線保護塊內部具有至少一導電外延線。
  11. 如請求項10的晶圓級晶片陣列，其中該導電外延線之一部分通過該承載層與該電子元件電性連接。
  12. 如請求項10的晶圓級晶片陣列，其中該導電外延線係一獨立線路不與該電子元件電性連接。
  13. 如請求項10的晶圓級晶片陣列，進一步包含：至少一切割道於該至少二晶片之間，其中，該切割道不經過該導電外延線。
  14. 如請求項10的晶圓級晶片陣列，其中各該晶片進一步包含：一連接墊結構電性連接於該電子元件；複數個孔洞，自該晶片之該下表面朝該上表面延伸，該些孔洞接觸該連接墊結構且露出該連接墊結構之一部分；一絕緣層，自該半導體晶片之該下表面朝該上表面延 伸，部分的該絕緣層位於該些孔洞之中；一導電層，位於該絕緣層下且自該半導體晶片之該下表面朝該上表面延伸，部分的該導電層位於該些孔洞之中，其中，位於該些孔洞內的該導電層係透過該連接墊結構電性連接該電子元件；以及一封裝層，形成於該導電層之下。
  15. 如請求項10的晶圓級晶片陣列，其中該外延線保護塊的厚度與該晶片的厚度比係0.05~0.1。
  16. 如請求項10的晶圓級晶片陣列，其中該電子元件包括一積體電路元件、一光電元件、一微機電(micro-electromechanical)元件或一表面聲波(SAW)元件。
  17. 如請求項10的晶圓級晶片陣列，其中該承載層包括氧化矽、氮化矽或氮氧化矽。
  18. 一種晶片封裝體，包含：一承載層具有一中央區以及一周邊區，該中央區係由該周邊區所圈繞；一半導體晶片對應於該中央區並配置於該承載層下方，具有一上表面及一下表面，且具有至少一電子元件設置於該上表面且為該承載層所覆蓋、以及至少一連接墊結構電性連接於該電子元件；複數個孔洞，該些孔洞自該半導體晶片之該下表面朝該 上表面延伸，該些孔洞接觸該連接墊結構且露出該連接墊結構之一部分；一絕緣層，自該半導體晶片之該下表面朝該上表面延伸，部分的該絕緣層位於該些孔洞之中；一導電層，位於該絕緣層下且自該半導體晶片之該下表面朝該上表面延伸，部分的該導電層位於該些孔洞之中，其中，位於該些孔洞內的該導電層係透過該連接墊結構電性連接該電子元件；一封裝層，形成於該導電層之下；至少一外延線保護塊對應於該周邊區配置於該承載層下方；以及至少一導電外延線配置於該外延線保護塊內。
  19. 如請求項18的晶片封裝體，其中該導電外延線之一部分通過該承載層與該電子元件電性連接。
  20. 如請求項18的晶片封裝體，其中該導電外延線係一獨立線路不與該電子元件電性連接。
  21. 如請求項18的晶片封裝體，其中該外延線保護塊的厚度與該晶片的厚度比係0.05~0.1。
  22. 如請求項18的晶片封裝體，其中該電子元件包括一積體電路元件、一光電元件、一微機電(micro-electromechanical)元件或一表面聲波(SAW)元件。
  23. 如請求項18的晶片封裝體，其中該承載層包括氧化矽、氮化矽或氮氧化矽。
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