TW201714259A - 半導體封裝結構及其形成方法 - Google Patents

半導體封裝結構及其形成方法 Download PDF

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TW201714259A
TW201714259A TW105128083A TW105128083A TW201714259A TW 201714259 A TW201714259 A TW 201714259A TW 105128083 A TW105128083 A TW 105128083A TW 105128083 A TW105128083 A TW 105128083A TW 201714259 A TW201714259 A TW 201714259A
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semiconductor body
molding compound
layer
insulating layer
semiconductor
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TW105128083A
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TWI614850B (zh
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劉乃瑋
林子閎
彭逸軒
蕭景文
黃偉哲
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聯發科技股份有限公司
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Abstract

本發明提供了一種半導體封裝結構及其形成方法。該半導體封裝結構包括：一半導體主體；一互連結構，設置在該半導體主體的表面上；一模塑料，圍繞該半導體主體及該互連結構；以及一重分佈層結構，設置在該互連結構及該模塑料上。其中，該模塑料的一部分在該重分佈層結構及該半導體主體之間延伸，並且該部分的模塑料係位於該半導體主體的表面的正下方。

Description

半導體封裝結構及其形成方法
本發明涉及半導體封裝結構，特別係涉及一種封裝上封裝(Package-on-Package，PoP)結構及其形成方法。
半導體封裝不僅能夠為封裝於其中的半導體晶粒提供免受環境污染的保護，而且也能夠提供該半導體晶粒與印刷電路板之間的電連接。例如，半導體晶粒封閉於封裝材料中，並且線路(trace)電性連接至該半導體晶粒及該印刷電路板。
但是，半導體晶粒與封裝材料之間的黏合性差。 可以輕易引起兩種材料的界面處(諸如半導體晶粒與封裝材料之間的界面)的脫層。另外，集中於兩種材料的界面處的應力可能導致線路破裂。
如此，期望一種創新的半導體封裝結構及其形成方法。
因此，本發明之主要目的即在於提供一種半導體封裝結構及其形成方法，可以提高半導體封裝結構的可靠性。
根據本發明至少一個實施例的半導體封裝結構， 包括：一半導體主體；一互連結構，設置在該半導體主體的第一表面上；一模塑料，圍繞該半導體主體及該互連結構；以及一重分佈層結構，設置在該互連結構及該模塑料上；其中，其中，該模塑料的一部分在該重分佈層結構及該半導體主體之間延伸，並且該部分的模塑料係位於該半導體主體的表面的正下方。
根據本發明至少一個實施例的一種半導體封裝結構，包括：一半導體主體；一導電墊，設置在該半導體主體的一表面的下方；一重分佈層結構，設置在該半導體主體的下方；一導電結構，位於該導電墊及該重分佈層結構之間，其中該半導體主體的該表面面向該重分佈層結構；一絕緣層，位於該半導體主體的該表面與該重分佈層結構之間，其中該表面的部分從該絕緣層中露出；以及一模塑料，圍繞該半導體主體並且覆蓋該一表面的該部分。
根據本發明至少一個實施例的一種形成半導體封裝結構的方法，包括：提供一晶粒，其中該晶粒包括：一半導體主體；一導電結構，設置在該半導體主體的一表面上；以及一絕緣層，圍繞該導電結構，其中該表面的一部分從該絕緣層中露出；形成一模塑料，以圍繞該半導體主體及覆蓋該表面的露出的部分；以及在該模塑料及該絕緣層上形成一重分佈層結構。
根據本發明至少一個實施例的一種形成半導體封裝結構的方法，包括：提供一晶粒，其中該晶粒包括：一半導體主體；一介電層，設置在該半導體主體的表面上；以及一絕 緣層，設置在該介電層的表面上，其中該介電層位於該半導體主體與該絕緣層之間，該介電層的表面的一部分從該絕緣層中露出；形成一模塑料，以圍繞該半導體主體及覆蓋該介電層的表面的露出的部分；以及在該模塑料及該絕緣層上形成一重分佈層結構。
本發明實施例，部分的模塑料在重分佈層結構與半導體主體之間的延伸並且該部分的模塑料係位於半導體主體的正下方，因此該部分的模塑料可以作為釋放應力的緩沖層，以提高半導體封裝接結構的可靠性。
100‧‧‧半導體主體
110‧‧‧晶片區
100a、100b‧‧‧表面
120‧‧‧導電墊
130‧‧‧介電層
140、280、410‧‧‧導電結構
150‧‧‧絕緣層
160‧‧‧第一開口
170‧‧‧第二開口
180、190‧‧‧晶粒
L‧‧‧長度
200‧‧‧載體基底
210‧‧‧導電通孔結構
220‧‧‧黏合層
230、460‧‧‧模塑料
230a‧‧‧延伸部
240、310、300‧‧‧重分佈層結構
250、320‧‧‧IMD層
260、330‧‧‧導電線路
270‧‧‧UBM層
290‧‧‧BSF
300‧‧‧開口
400‧‧‧半導體封裝
420‧‧‧基底
450‧‧‧接合線
430、440‧‧‧半導體晶粒
431、441‧‧‧接墊
通過閱讀接下來的詳細描述以及參考所附的圖式的例子，可以更全面地理解本發明，其中：第1A~1G圖為根據本發明一些實施例的形成半導體封裝結構的方法中的各階段的橫截面示意圖；第2A~2B圖為根據本發明一些實施例的形成半導體封裝結構的方法中的各階段的橫截面示意圖；第3圖為根據本發明一些實施例的半導體封裝結構的橫截面示意圖；第4圖為根據本發明一些實施例的半導體封裝結構的橫截面示意圖。
以下描述為實現本發明的較佳預期模式。該描述僅係出於說明本發明一般原理的目的，而不應視為限制。本發 明的範圍可參考所附的申請專利範圍來確定。
參考特定實施例與參考確定的圖式來描述本發明，但是本發明不限制於此，並且本發明僅由申請專利範圍來限定。描述的圖式僅是示意圖而非限制。在圖式中，出於說明目的而誇大了某些元件的尺寸，並且某些元件的尺寸並非按比例繪制。圖示中的尺寸及相對尺寸不對應本發明實踐中的真實尺寸。
第1A~1G圖為根據本發明一些實施例的形成半導體封裝結構的方法中的各階段的橫截面示意圖。在第1A~1G圖中描述的階段之前、期間及/或之後，可以提供額外的操作。對於不同實施例，可以替換或者取消描述的該等階段中的部分。額外的特徵(如結構)可以添加至該半導體封裝結構。對於不同的實施例，可以替換或者取消以下描述的特徵中的部分。為了簡化圖形，在第1A~1G圖中僅繪示了半導體封裝結構的部分。
如第1A圖所示，提供了一半導體主體100。在一些實施例中，該半導體主體100可以為一晶圓或者一面板(panel)。該半導體主體100可以包括：一個或複數個晶片區110。在一些實施例中，該半導體主體100包括：一半導體材料，諸如矽或者另一合適的半導體材料。
一互連結構形成於該半導體主體100的一表面100a，該表面100a可被稱為一主動面。在一些實施例中，該互連結構包括：複數個導電墊120及一介電層130。如第1A圖所示，該等導電墊120位於每個晶片區110中的表面100a 上。介電層130位於表面100a上並且覆蓋每個導電墊120的部分。
該互連結構可以進一步包括：一條或複數條導電線路，一層間介電(Interlayer Dielectric，ILD)層，以及金屬間介電(Inter-Metal Dielectric，IMD)層，位於導電墊120及介電層130的下面。例如，導電墊120為互連結構中的最上層的導電線路。介電層130為互連結構中的最上層的介電層並且可被稱為“鈍化層”。為了簡化圖形，此中僅描繪了導電墊120與介電層130作為示例。
如第1A圖所示，該互連結構可以進一步包括：複數個導電結構140形成於介電層130的複數個開口中，其中開口露出對應的導電墊120的部分。導電結構140伸出介電層130。換言之，介電層130僅圍繞導電結構140的底部。
在一些實施例中，導電結構140可以為凸塊或者柱。在一些實施例中，導電結構140可以包括：銅或者另一合適的導電材料。
如第1A圖所示，該互連結構可以進一步包括：一絕緣層150，形成於該介電層130上。該絕緣層150圍繞導電結構140的頂部。絕緣層150為保護導電結構140的緩沖層。絕緣層150也被稱為用於在半導體主體100上提供平坦表面的平坦化層(flattening layer)。
在一些實施例中，絕緣層150包括：一聚合物或者另一合適的絕緣材料。在一些實施例中，通過沈積製程來形成絕緣層150，諸如塗佈(coating)製程、物理氣相沈積製程、 化學氣相沈積製程或者另一合適的製程。
在一些實施例中，沈積的絕緣層150覆蓋導電結構140。接著，在沈積的絕緣層150上執行減薄製程(thinning process)，諸如蝕刻製程、銑銷製程(milling process)、磨光製程或者拋光製程。如此，導電結構140的頂面從減薄的絕緣層150中露出。在一些實施例中，絕緣層150的頂面與導電結構140的頂面大致共平面。
如第1B圖所示，在半導體主體100的相對於表面100a的表面100b上執行減薄製程。如此，降低半導體主體100的厚度。
接著，一個或複數個第一開口160形成於絕緣層150及介電層130中。如此，半導體主體100的一部分的表面100a通過第一開口160從絕緣層150和介電層130中露出。如上所述，介電層130與半導體主體100之間可以存在其他的介電層；第一開口160可以進一步穿透這些介電層以露出表面100a。
每個第一開口160位於兩個相鄰的晶片區110之間並且延伸進晶片區110中。換言之，將第一開口160設置在晶片區110的邊緣並且將其延伸到晶片區110之外。
在一些實施例中，第一開口160沿晶片區110延伸。在一些實施例中，第一開口160連續地圍繞晶片區域110的中心。例如，從俯視圖來看，第一開口160連續地圍繞導電墊120及導電結構140。
在一些實施例中，在絕緣層150及介電層130上 執行鐳射開槽製程來形成第一開口160。在一些實施例中，通過合適的刀片切割絕緣層150及介電層130以形成第一開口160。在一些實施例中，在絕緣層150與介電層130上執行微影與蝕刻製程以形成第一開口160。蝕刻製程可以為乾式蝕刻製程、濕式蝕刻製程、電漿蝕刻製程、反應離子(reactive ion)蝕刻製程或者另一合適的製程。
在其他的一些實施例中，絕緣層150包括：一光敏材料，並且在絕緣層150上執行一微影製程。對絕緣層150的一些部分曝光並顯影以移除這些部分。如此，在絕緣層150中形成沒有延伸進介電層130的第一開口160。如上所述，在介電層130與半導體主體100之間可以存在其他的介電層。可以在絕緣層150中形成沒有延伸進這些介電層的第一開口160。
如第1C圖所示，在半導體主體100中形成一個或複數個第二開口170。第二開口170沿第一開口160及晶片區110延伸。每個第二開口170可與第一開口160連通。如此，半導體主體100中對應晶片區110的部分彼此隔開。相應地，形成複數個晶片或晶粒180。在一些實施例中，使用合適的刀片來切割半導體主體100以形成晶粒180。
在一些實施例中，第一開口160寬於第二開口170。相應地，開口160露出每個晶粒180中的半導體主體100的表面100a的一部分。換言之，半導體主體100寬於絕緣層150及介電層130，如第1C圖所示。
每個晶粒180中的表面100a的露出部分具有長度 L。在一些實施例中，長度L的範圍大約從1μm至200μm，例如從10μm至200μm。在一些實施例中，第一開口160與第二開口170之間的寬度差大致等於2倍的長度L(即2L)，如第1C圖所示。在一些實施例中，半導體主體100與絕緣層150(或介電層130)之間的寬度差大致等於2倍的長度L(即2L)，如第1C圖所示。
如第1D圖所示，提供一載體基底200。在一些實施例中，載體基底200為一晶圓或者一面板。載體基底200可以包括：玻璃或者其他的支撐材料。
接著，在載體基底200上形成複數個導電通孔結構210。導電通孔結構210可以為穿過插入層的通孔(through interposer vias，TIV)。在一些實施例中，導電通孔結構210為柱或者其他合適的導電結構。在一些實施例中，導電通孔結構210包括：銅或者另一合適的導電材料。在一些實施例中，通過電鍍製程或者另一合適的製程形成導電通孔結構210。
本發明實施例不限制於此。在其他的一些實施例中，在形成導電通孔結構210之前，可以在載體基底200上形成RDL結構。接著，在載體基底200上的RDL結構上形成導電通孔結構210。
如第1D圖所示，含有部分露出的表面100a的晶粒180接合至載體基底200上。在一些實施例中，晶粒180中的半導體主體100的表面100b經由一黏合層220附著至載體基底200。在一些實施例中，黏合層220包括：膠水或者另一合適的黏性材料。在其他的一些的實施例中，複數個含有部分 露出的表面100a的晶粒180接合至載體基底200上。
在一些實施例中，晶粒180為主動設備。例如，晶粒180可以為一邏輯晶粒，該邏輯晶粒包括：中央處理單元(Central Processing Unit，CPU)、圖形處理單元(Graphics Processing Unit，GPU)、DRAM控制器或者他們的任意組合。在其他的一些的實施例中，一個或複數個被動設備也可以接合至該載體基底200上。被動設備可以包括或者不包括部分露出的表面，類似於部分露出的表面100a。
在一些實施例中，晶粒180設置在兩個導電通孔結構210之間。在一些實施例中，從俯視圖來看，導電通孔結構210圍繞晶粒180。
如第1E圖所示，在載體基底200上形成一模塑料230。該模塑料230圍繞並鄰接半導體主體100的側壁、介電層130的側壁、絕緣層150的側壁及黏合層220的側壁。模塑料230也圍繞並鄰接導電通孔結構210。
根據本發明的一些實施例，模塑料230的一部分230a從半導體主體100的側壁沿其表面100a橫向地延伸至絕緣層150的側壁及介電層130的側壁。如此，模塑料230的延伸的部分230a(以下稱為“延伸部230a”)覆蓋表面100a露出的部分。其中，該延伸部230a位於該半導體主體100的表面100a的正下方，其中正下方可以是係指半導體主體100正對RDL結構240的方向。
在一些實施例中，模塑料230的延伸部230a的延伸長度(即長度L)的範圍為11μm~200μm，例如為10μm~200 μm。
在一些實施例中，模塑料230的延伸部230a的側壁鄰接絕緣層150的側壁及介電層130的側壁，並且與半導體主體100的側壁不共平面。模塑料230的延伸部230a堆疊在半導體主體100上，例如延伸部230a與半導體主體100在俯視方向上重疊。在一些實施例中，從俯視圖來看，模塑料230的延伸部230a連續地圍繞絕緣層150及介電層130。
在一些實施例中，模塑料230的延伸部230a直接接觸表面100a露出的部分。在其他的一些實施例中，模塑料230的延伸部230a不直接接觸表面100a的露出的部分。
在一些實施例中，半導體主體100的邊緣部分夾在黏合層220與模塑料230的延伸部230a之間。在一些實施例中，如第1E圖所示，模塑料230中位於導電通孔結構210和絕緣層150(或者介電層130)之間的部分寬於模塑料230中位於導電通孔結構210與半導體主體210之間的部分。
如上所述，在其他的一些實施例中，含有部分露出的表面的一個或複數個被動設備也接合至載體基底200上。模塑料230的延伸部230a也覆蓋該被動設備的該表面的露出部分。
在一些實施例中，模塑料230包括：一非導電材料，諸如環氧樹脂、樹脂、可塑聚合物或者另一合適的模塑料。在一些實施例中，該模塑料230可以在實質為液體時應用，然後通過化學反應固化。在其他的一些實施例中，模塑料230可以為紫外(ultraviolet，UV)或者熱固化並且應用為凝膠或者 可塑固體的聚合物，接著通過UV或者熱固化製程固化該聚合物。模塑料230可以按照模型(未示出)來固化。
在一些實施例中，模塑料230的材料可以不同於絕緣層150的材料。在一些實施例中，絕緣層150的材料具有好的間隙填充(gap-filling)能力。例如，絕緣層150的材料比模塑料230的材料，更容易填充導電結構140之間的空間。相比於模塑料230的材料，當由絕緣層150的材料來覆蓋半導體主體100的表面100a時，可以更容易地執行缺陷測試及/或對准步驟。
在一些實施例中，沈積的模塑料230覆蓋導電通孔結構210的頂面、絕緣層150的頂面及導電結構140的頂面。接著，執行研磨製程來使沈積的模塑料230變薄。堆疊在半導體主體100之上的模塑料230的延伸部230a也變薄。如此，變薄了的模塑料230露出導電通孔結構210的頂面，絕緣層150的頂面及導電結構140的頂面。
在一些實施例中，模塑料230的上表面與導電通孔結構210的上表面大致共平面。在一些實施例中，模塑料230的上表面與絕緣層150及導電結構140的頂面也大致共平面。
如第1F圖所示，在模塑料230及絕緣層150上形成一重分佈層(Redistribution Layer，RDL)結構240。在一些實施例中，RDL結構240包括：一個或複數個IMD層250及一條或複數條導電線路260。導電線路260設置在IMD層250中並且被IMD層250圍繞。導電線路260的接墊部分從RDL結構240的頂面露出。需要注意的是，圖中所示的IMD 層250及導電線路260的數量和組態僅是一些示例而不是對本發明的限制。
導電墊120通過導電結構140電性連接至RDL結構240的導電線路260。導電通孔結構210直接電性連接至RDL結構240的導電線路260。
在一些實施例中，如第1F圖所示，模塑料230的延伸部230a夾在RDL結構240與半導體主體100之間。更具體地，模塑料230的延伸部230a夾在最底層的IMD層250和表面100a的露出的部分之間。
如第1F圖所示，在RDL結構240上形成一個或複數個導電結構280。例如，導電結構280形成在導電線路260的接墊部分上。在一些實施例中，導電結構280為接合球(諸如焊料球)或者另一合適的導電結構。
在一些實施例中，在一個導電結構280與導電線路260的一個接墊部分之間存在一凸塊下金屬(Under-Bump Metallurgy，UBM)層270。該UBM層270可以包括：單層或者複數層，諸如阻擋層和晶種層。此中描繪了含有單層的UBM層270作為示例。
如第1G圖所示，移除載體基底200。如此，露出附著至半導體主體100的表面100b的黏合層220。在一些實施例中，消除黏合層220的黏性以使載體基底200脫層。
接著，在黏合層220及模塑料230上形成一背面膜(backside film，BSF)290。BSF290和半導體主體100位於黏合層220的兩相對側。在一些實施例中，通過BSF290來 防止形成的半導體封裝的翹曲。在其他的一些實施例中，可以省略BSF290。
在一些實施例中，如第1G圖所示，在BSF290中形成一個或複數個開口300。在一些實施例中，通過鐳射鑽孔製程或者另一合適的製程形成開口300。
為了進一步電連接，開口300露出導電通孔結構210的遠離RDL結構240的表面。例如，晶片/晶粒可以接合在BSF290上并通過開口300電性連接至導電通孔結構210。可選地，一封裝可堆疊在BSF290上並且通過開口300電性連接至導電通孔結構210。例如，該封裝可以為一記憶體封裝或者另一合適的封裝，諸如DRAM封裝。
根據本發明的一些實施例，在形成BSF290之後，可以執行分離製程。例如，切割RDL結構240、模塑料230及BSF290。如此形成複數個半導體封裝結構。
可以對本發明實施例做出許多變化及/或修改。第2A至2B圖為根據本發明實施例的形成半導體封裝結構的方法的各階段的橫截面示意圖。第2A~2B圖與第1A~1G圖中，相同的元件使用相同的參考符號，並且出於簡潔而不再描述。
如第2A圖所示，提供了一晶片或者晶粒190。該晶粒190的結構類似於第1C~1G圖中的晶粒180的結構。形成晶粒190的方法也類似於形成晶粒180的方法，如第1A~1C圖所示。晶粒180與190之間的差別在於：晶粒180的第一開口160穿透絕緣層150及介電層130，而晶粒190的第一開口160僅穿透絕緣層150。如此，如第2A圖所示，絕緣層150 通過第一開口160露出介電層130的表面的邊緣部分。相應地，介電層130和半導體主體100均寬於絕緣層150。
在一些實施例中，絕緣層150包括：一光敏材料，並且在絕緣層150上執行微影製程。對絕緣層150的一些部分進行曝光和顯影以移除這些部分。如此，在絕緣層150中形成沒有延伸進介電層130的第一開口160。如上所述，在介電層130與半導體主體100之間可以有其他介電層。在一些實施例中，第一開口160沒有延伸進入這些介電層。
如第2A圖所示，RDL結構310，類似於RDL結構240，形成於載體基底200上。在一些實施例中，RDL結構310包括：一個或者複數個IMD層320以及一條或者複數條導電線路330。導電線路330設置在IMD層320中，並且由IMD層320圍繞。導電線路330的接墊部分自RDL結構310的頂面露出。
接著，在RDL結構310上形成複數個導電通孔結構210。接著，含有第一開口160的晶粒190接合至RDL結構310上。在一些實施例中，在晶粒190中的半導體主體100的表面100b通過黏合層220附著至RDL結構310。在其他的一些實施例中，複數個含有第一開口160的晶粒190接合至RDL結構310上。
如第2B圖所示，模塑料230圍繞並且鄰接半導體主體100的側壁、介電層130的側壁、絕緣層150的側壁及黏合層220的側壁。模塑料230也圍繞並且鄰接導電通孔結構210。
根據本發明的一些實施例，模塑料230的延伸部230a從半導體主體100的側壁橫向延伸至絕緣層150的側壁。由於晶粒190的第一開口160穿透絕緣層150但沒有延伸進介電層130中，因此第2B圖所示的延伸部230a薄於第1G圖所示的延伸部230a。
在一些實施例中，模塑料230的延伸部230a的側壁鄰接絕緣層150的側壁，並且與半導體主體100及介電層130的側壁不共平面。模塑料230的延伸部230a堆疊在半導體主體100及介電層130上。在一些實施例中，從俯視圖來看，模塑料230的延伸部230a連續地圍繞絕緣層150。在一些實施例中，模塑料230的延伸部230a直接接觸介電層130的遠離RDL結構310的表面。
在一些實施例中，如第2B圖所示，模塑料230的延伸部230a夾在介電層130與RDL結構240之間。特別地，模塑料230的延伸部230a夾在介電層130的邊緣部分與RDL結構240的IMD層250之間。
如第2B圖所示，移除第2A圖所示的載體基底200。如此，露出RDL結構310的一個IMD層320。接著，在RDL結構310上形成BSF290。在BSF290中形成一個或複數個開口300並且該一個或複數個開口300延伸進入RDL結構310的一個IMD層320。如此，通過開口300露出RDL結構310的一條導電線路330，以用於進一步的電連接。
根據本發明的一些實施例，在形成BSF290之後，執行分離製程。例如，切割RDL結構240，模塑料230，RDL 結構310及BSF290。如此，形成複數個半導體封裝。
如上所述，半導體封裝可以堆疊在BSF290上並且通過開口300電性連接至導電通孔結構210。例如，如第3圖所示，半導體封裝400垂直地堆疊在第2B圖所示的半導體封裝結構上。如此，提供了一封裝上封裝(PoP)結構。
第3圖為根據本發明一些實施例的半導體封裝結構的橫截面示意圖。在第3圖與第1A~1G及第2A~2B圖中，相同的元件使用相同的參考符號，並且出於簡潔而不再描述。需要注意的是，第3圖所示的半導體封裝400的結構僅是示例而不是對本發明的限制。
半導體封裝400安裝於RDL結構310上並且通過導電結構410電性連接至RDL結構310。導電結構410位於開口300中並且從BSF290中伸出。在一些實施例中，導電結構410可以為導電凸塊(諸如微凸塊(micro bump))，導電柱，導電膏結構，或者另一合適的導電結構。導電結構410可以包括：銅、焊料、或者另一合適的導電材料。在其他的一些實施例中，底部填充材料可以圍繞導電結構410。
在一些實施例中，半導體封裝400包括：一基底420，至少一個半導體晶粒(如兩個垂直堆疊的半導體晶粒430與440)，一接合線450及一模塑料460。在一些實施例中，基底420可以為一PCB並且由PP或者另一合適的材料形成。基底420通過導電結構410電性連接至RDL結構310。
半導體晶粒430通過黏合層(諸如膠水或者另一合適的黏性材料)附著至基底420。半導體晶粒430通過其接 墊431及接合線450電性連接至基底420。在一些實施例中，半導體晶粒430為一記憶體晶粒或者另一合適的半導體晶粒。半導體晶粒440通過黏合層(諸如膠水或者另一合適的黏性材料)附著至半導體晶粒430。半導體晶粒440通過其接墊441及接合線450電性連接至基底420。在一些實施例中，半導體晶粒440為一記憶體晶粒或者另一合適的半導體晶粒。在一些實施例中，半導體晶粒430與440均為DRAM晶粒。
模塑料460覆蓋基底420及圍繞半導體晶粒430與440。接合線450嵌入於模塑料460中。在一些實施例中，模塑料460由非導電材料形成，諸如環氧樹脂、樹脂、可塑聚合物或另一合適的模塑材料。
可以對本發明實施例做出許多的變形及/或修改。第4圖為根據本發明一些實施例的半導體封裝結構的橫截面示意圖。在第4圖與第1A~1G圖中，相同的元件使用相同的參考符號，並且出於簡潔而不再描述。
第4圖的半導體封裝結構類似於第1G圖的半導體封裝結構。兩者之間的差異在於：在第1G圖中存在複數個由模塑料230封閉的導電通孔結構210，而在第4圖中，在模塑料230中沒有導電通孔結構。另外，在第1G圖中的BSF290包括：露出導電通孔結構210的開口300，而在第4圖中，在BSF290中沒有開口300。
根據本發明實施例的半導體封裝結構及其形成方法提供了各種優勢。該半導體封裝結構包括：一晶粒。該晶粒包括：一位於一半導體主體上的絕緣層。在絕緣層中形成一開 口使得絕緣層的側壁相對半導體主體的側壁縮進。晶粒可由模塑料圍繞。如此，模塑料包括：填充上述開口的延伸部。相應地，模塑料的側壁與半導體主體的側壁不共平面，使得模塑料可以作為用於釋放應力的緩沖層。
具有延伸部(堆疊在半導體主體上)的模塑料可以阻止應力拉伸或者撕扯導電線路，諸如在模塑料上的RDL結構中的導電線路。因此，可以阻止由於應力集中而導致的導電線路的缺陷或者破裂。也可以緩和或者消除兩種材料界面處的脫層，諸如半導體主體與模塑料之間的界面處的脫層。顯著地改善半導體封裝結構的質量和可靠性。
可以對本發明實施例做出許多變化及/或修改。根據本發明實施例的半導體封裝結構及其形成方法可以用於形成三維(three-dimensional，3D)封裝，2.5D封裝，扇出封裝，或者另一合適的封裝。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
100‧‧‧半導體主體
100a、100b‧‧‧表面
120‧‧‧導電墊
130‧‧‧介電層
140、280‧‧‧導電結構
150‧‧‧絕緣層
160‧‧‧第一開口
180‧‧‧晶片或晶粒
210‧‧‧導電通孔結構
220‧‧‧黏合層
230‧‧‧模塑料
230a‧‧‧延伸部
240‧‧‧重分佈層結構
270‧‧‧UBM層
290‧‧‧BSF
300‧‧‧開口

Claims (17)

  1. 一種半導體封裝結構，包括：一半導體主體；一互連結構，設置在該半導體主體的表面上；一模塑料，圍繞該半導體主體及該互連結構；以及一重分佈層結構，設置在該互連結構及該模塑料上；其中，該模塑料的一部分在該重分佈層結構及該半導體主體之間延伸，並且該部分的模塑料係位於該半導體主體的表面的正下方。
  2. 如申請專利範圍第1項所述的半導體封裝結構，其中，該互連結構露出該半導體主體的表面的一部分，該部分的模塑料直接接觸該半導體主體的表面的露出的部分。
  3. 如申請專利範圍第1項所述的半導體封裝結構，其中，該互連結構包括：一介電層，設置在該半導體主體的表面上；一絕緣層，設置在該介電層的表面上，並且該介電層位於該半導體主體與該絕緣層之間；以及一導電結構，耦接至該重分佈層結構，並且該介電層圍繞該導電結構的底部，該絕緣層圍繞該導電結構的頂部。
  4. 如申請專利範圍第3項所述的半導體封裝結構，其中，該介電層完全覆蓋該半導體主體的表面，該絕緣層露出該介電層的表面的部分；其中，該部分的模塑料夾在該重分佈層結構和該介電層的表面的露出的部分之間。
  5. 如申請專利範圍第3項所述的半導體封裝結構，其中，該 半導體主體的長度大於該絕緣層的長度；或者，該部分的模塑料堆疊在該半導體主體的表面上；或者，該部分的模塑料的側壁與該半導體主體的側壁不共平面；或者，該部分的模塑料圍繞該絕緣層。
  6. 一種半導體封裝結構，包括：一半導體主體；一導電墊，設置在該半導體主體的表面的下方；一重分佈層結構，設置在該半導體主體的下方；一導電結構，位於該導電墊及該重分佈層結構之間，其中該半導體主體的該表面面向該重分佈層結構；一絕緣層，位於該半導體主體的該表面與該重分佈層結構之間，其中該表面的部分從該絕緣層中露出；以及一模塑料，圍繞該半導體主體並且覆蓋該表面的該部分。
  7. 如申請專利範圍第6項所述的半導體封裝結構，其中，該模塑料從該半導體主體的側壁橫向地延伸至該絕緣層的側壁。
  8. 如申請專利範圍第7項所述的半導體封裝結構，其中，該模塑料的延伸長度介於1μm~200μm之間。
  9. 如申請專利範圍第6項所述的半導體封裝結構，其中，該模塑料的鄰接該絕緣層的側壁與該半導體主體的側壁不共平面；或者，覆蓋該表面的該部分的模塑料夾在該重分佈層結構與該半導體主體之間。
  10. 如申請專利範圍第6項所述的半導體封裝結構，其中，進一步包括：一導電通孔結構，耦接至該重分佈層結構；其中，該模塑料的一第一部分位於該導電通孔結構與該絕緣層之間，該模塑料的一第二部分位於該導電通孔結構與該半導體主體之間，並且該模塑料的第一部分的寬度大於該模塑料的第二部分的寬度。
  11. 如申請專利範圍第6項所述的半導體封裝結構，其中，進一步包括：一黏合層，其中，該半導體主體的一部分位於該黏合層與該絕緣層之間以及另一部分位於該黏合層與該模塑料之間。
  12. 一種形成半導體封裝結構的方法，包括：提供一晶粒，其中該晶粒包括：一半導體主體；一導電結構，設置在該半導體主體的一表面上；以及一絕緣層，圍繞該導電結構，其中該表面的一部分從該絕緣層中露出；形成一模塑料，以圍繞該半導體主體及覆蓋該表面的露出的部分；以及在該模塑料及該絕緣層上形成一重分佈層結構。
  13. 如申請專利範圍第12項所述的形成半導體封裝結構的方法，其中，形成該晶粒的步驟包括：在該絕緣層中形成一第一開口，以露出該表面的該部分；以及在該半導體主體中形成沿該第一開口方向的一第二開口。
  14. 如申請專利範圍第13項所述的形成半導體封裝結構的方法，其中該第一開口寬於該第二開口。
  15. 如申請專利範圍第13項所述的形成半導體封裝結構的方法，其中，該第一開口與該第二開口連通。
  16. 如申請專利範圍第12項所述的形成半導體封裝結構的方法，其中，在形成該模塑料之後，該方法進一步包括：對該模塑料執行減薄製程。
  17. 一種形成半導體封裝結構的方法，包括：提供一晶粒，其中該晶粒包括：一半導體主體；一介電層，設置在該半導體主體的表面上；以及一絕緣層，設置在該介電層的表面上，其中該介電層位於該半導體主體與該絕緣層之間，該介電層的表面的一部分從該絕緣層中露出；形成一模塑料，以圍繞該半導體主體及覆蓋該介電層的表面的露出的部分；以及在該模塑料及該絕緣層上形成一重分佈層結構。
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