TW201630147A - 在孔穴中具有由可模造材料所囊封的電路模組的插入物及製造方法 - Google Patents

在孔穴中具有由可模造材料所囊封的電路模組的插入物及製造方法 Download PDF

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TW201630147A
TW201630147A TW104140292A TW104140292A TW201630147A TW 201630147 A TW201630147 A TW 201630147A TW 104140292 A TW104140292 A TW 104140292A TW 104140292 A TW104140292 A TW 104140292A TW 201630147 A TW201630147 A TW 201630147A
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substrate
layer
circuit
layers
bottom wall
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TW104140292A
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TWI685079B (zh
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虹 沈
亮 王
拉傑許 卡特卡爾
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英帆薩斯公司
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Abstract

堆疊的晶粒(110)係由可模造材料所形成的多個囊封層(524)而被囊封在一個插入物的孔穴(304)之中。導電路徑(520,623)係將該等晶粒連接到該孔穴的底壁部(304B)，且透過通過該底壁部的基板穿孔(TSV)而連接到該插入物之下的一個導體。該等導電路徑可被形成在其之每一個為形成在個別的囊封層中的一個通孔(514)之中的諸段。各段係可藉由電鍍而被形成在一個較低的段上；電鍍電流係可透過該等TSV與稍早形成的諸段而從該插入物之下所提供。其他特徵亦被提供。

Description

在孔穴中具有由可模造材料所囊封的電路模組的插入物及製造方法 【相關申請案之交互參照】
本申請案係主張西元2014年3月12日提出之美國臨時專利申請案第61/952,066號的優先權，該件美國臨時專利申請案係以參照方式而納入本文。
本發明係關於半導體技術，且尤指用於半導體積體電路與其他構件之互連的輔助基板之使用。
半導體積體電路(IC,integrated circuit)係具有極小的接觸墊之小型裝置，該等接觸墊必須被連接到其他的IC或非IC構件。到其他構件之連接係藉由諸如印刷電路板(PCB,printed circuit board)的輔助基板或插入物所促成。圖1係說明IC 110為透過一個插入物120而連接到一個PCB 114。IC 110具有一個接觸墊112，其被附接到在插入物120的頂部上之接觸墊120C.T。該附接是經由連接140，其可為例如：焊接、黏著劑、或熱壓縮。該插入物的底部接觸墊120C.B被附接到該PCB的接觸墊114C(藉由適當的連接140)。在插入物120之中的互連線路120L提供在插入物的接觸墊120C (即：120C.T與120C.B)之間的期望連接。該PCB的互連線路114L提供在該PCB的接觸墊114C之間的期望連接。其他的插入物、IC、或其他電路可被連接到該PCB。
為了提供小尺寸、高操作速度、低功率消耗、與低製造成本，各個構件110、114、120可具有密集封裝電路，其具有對應密集封裝的接觸墊112、114C、120C與較佳為短的互連線路(“接線”)114L、120L。尤其，插入物120應為薄以縮短線路120L的垂直段。薄的插入物可由有機或陶瓷材料而便宜地製造。然而，一個薄的插入物可能為脆弱且可撓曲，且可能容易受到諸如由熱膨脹所引起的熱應力之機械應力而扭曲或斷裂。熱應力是在其具有不同熱膨脹係數(CTE,coefficients of thermal expansion)的材料之存在時而特別有害。舉例來說，矽具有較其常用在PCB與插入物中的有機或陶瓷材料為低的CTE，且此對於使用其具有矽基IC之有機或陶瓷PCB與插入物而言為一個嚴重的問題。熱應力可能損壞該等連接140且使得組件為不可操作。此外，熱應力造成扭曲，其使得組裝過程為複雜。
因此，期望為使該插入物加強以防扭曲而且使用導熱材料，其使局部產生的熱量散佈且將此等熱量傳導到周圍。
圖2係說明一種已知的陶瓷或有機插入物120，一個蓋子210係位在一個晶粒(die)110之上(一個晶粒是一種IC，其被製造為一個半導體晶圓(wafer)的部分者且接著為從該晶圓所分開；晶圓可含有同時製造的多個晶粒)。該插入物係將晶粒110連接到底部接觸墊120C.B；線路120L未被顯示。蓋子210係藉由環氧樹脂220而被附接到插入物120。蓋子210係使該插入物加強且平坦，並且作用如同一種散熱片(heat spreader)：由晶粒110所 產生的熱量係透過熱油脂230而被傳導到蓋子210且接著到周圍。參閱：西元2006年6月13日所頒發給Eghan等人之美國專利第7,061,102號。
為了降低在加強件210與插入物120之間的介面的熱應力，該加強件與插入物可被作成在單一個基板120S，如在圖3所示且在Eghan專利中所描述。基板120S具有一個孔穴304，其容納晶粒110；該晶粒是由基板的“周邊壁部”304P所圍繞。該種組件可藉由在該晶粒與插入物之間的底部填充劑(underfill)310而進一步強化；該底部填充劑是由環氧樹脂所作成，其將該晶粒黏合到插入物且因此減輕在連接140之上的應力。另外，該底部填充劑可為導熱性以散熱。此外，導熱性的囊封物320係填充在該晶粒與壁部304P之間的空間以保護該晶粒且有助於散熱。該囊封物可能或可能未覆蓋該晶粒，且一個另外的散熱片(未顯示)可被提供在頂部上。
圖4係說明一種有機(模造的環氧樹脂或塑膠)插入物120，其支撐一種堆疊的三個晶粒110.1、110.2、110.3，如在美國專利第6,492,726號(Quek等人，西元2002年12月10日)所述。在此，插入物孔穴304具有階梯狀的側壁，不同的晶粒110.1、110.2、110.3被安裝在個別不同的階梯410.1、410.2、410.3(410.1為孔穴的底部)。對於各個階梯，接觸結構420是從個別的“接觸球”140朝下延伸通過該插入物，其中，接觸結構420可從該插入物之下方而進入。此外，參閱：美國專利第7,977,579號(Bathan等人，西元2011年7月12日)。
圖4的晶粒110(即：110.1、110.2、110.3)係可用適合的介電材料(未顯示)而為底部填充及囊封。一種散熱片(未顯示)可被提供在頂部上。
此段落係概述本發明的一些特點。其他特點可被描述在隨後的段落中。本發明係由隨附的申請專利範圍所界定，隨附的申請專利範圍係以參照方式而納入此段落。
一些實施例係提供適用於具有孔穴之有機、陶瓷、矽、或其他型式的插入物之架構與製造技術。一種插入物可包括多晶片模組(MCM,multi-chip module)之多個階層的晶粒。一些實施例提供簡單的製造過程。
本發明係不受限於上述的特徵與優點，除了由隨附申請專利範圍所界定之外。
110‧‧‧積體電路(IC)(晶粒)
110A、110B、110C、110D、110E、110F、110G‧‧‧晶粒
112‧‧‧接觸墊
114‧‧‧印刷電路板(PCB)
114C‧‧‧接觸墊
114L‧‧‧互連線路
120‧‧‧插入物
120C.B、120C.T‧‧‧接觸墊
120L‧‧‧互連線路
120S‧‧‧基板
140‧‧‧連接
210‧‧‧蓋子(加強件)
220‧‧‧環氧樹脂
230‧‧‧熱油脂
304‧‧‧孔穴
304B‧‧‧底壁部
304P‧‧‧周邊壁部
310‧‧‧底部填充劑
320‧‧‧囊封物
410.1、410.2、410.3‧‧‧階梯
420‧‧‧接觸結構
510‧‧‧基板(晶圓)
510.1、510.2‧‧‧基板
514.0‧‧‧孔(階層L0孔)
514.1‧‧‧L1孔
514.2‧‧‧L2孔
518‧‧‧介電質
520'‧‧‧導體
520.0‧‧‧導體(接線段)(接觸墊)
520.1‧‧‧L1接線段
520.2‧‧‧L2接線段
520.3‧‧‧L3接線段
520.4‧‧‧L4接線段
520S‧‧‧晶種層
520T‧‧‧垂直接線
524.1‧‧‧L1囊封物(層)
524.2‧‧‧L2囊封物(層)
524.3‧‧‧L3囊封物(層)
524.4‧‧‧L4囊封物(層)
532‧‧‧保護層
534‧‧‧端子
540‧‧‧散熱片
610.3‧‧‧重新分佈層(RDL)
620.3‧‧‧互連件(RDL線路)
630.3‧‧‧接觸墊
810‧‧‧黏著劑
圖1、2、3、4係顯示具有根據先前技術的插入物之結構的垂直橫截面。
圖5A、5B.1係顯示在根據本發明的一些實施例之製造過程中的插入物的垂直橫截面。
圖5B.2係在根據本發明的一些實施例之製造過程中的插入物的俯視圖。
圖5C、5D、5E、5F、5G、5H、5I、5J、5K、5L、6、7、8A係顯示在根據本發明的一些實施例之製造過程中的插入物的垂直橫截面。
圖8B係在根據本發明的一些實施例之製造過程中的插入物的俯視圖。
在此段落所描述的實施例係說明而非限制本發明。本發明係由隨附的申請專利範圍所界定。
在本發明的一些實施例中，堆疊的晶粒或多晶片模組(MCM) 可被置放在一個插入物孔穴中，該孔穴可具有如在圖2-4或其他形狀的任何形狀。一些實施例使用類似於420的垂直接線，用於將上方的晶粒連接到在插入物之下方的電路。然而，在一些實施例中，該等接線僅為通過插入物厚度的一個小部分。舉例來說，該等接線可通過孔穴的底壁部而未通過周邊壁部的任何部分。
在一些實施例中，該種組件被製造為在該孔穴內之一個堆疊的階層；各個階層包括個別的晶粒或多個晶粒110與環繞該等晶粒的囊封物。一個垂直接線可通過多個囊封物階層。通過各個階層之接線段是藉由將導電材料沉積在此階層中所作成的一個孔中而分別作成。此短的段是比將導電材料沉積到其深度為接線的整個長度之一個較深的孔中而為較容易製造。由於長的接線為較容易製造，較高的堆疊為可能，且各個接線可為較窄以改善接線密度。
圖5A係說明根據本發明的一些實施例之插入物製造的開始階段。如在圖5A所示，插入物製造係以一個基板510來開始，例如：由矽(單晶或一些其他型式)或另一種半導體或非半導體材料所作成的一個晶圓。吾人將聚焦在適用於由矽所作成的晶圓之製造技術，但類似的技術可被用於其他的半導體與非半導體材料，其包括金屬、玻璃、陶瓷、聚合物、有機或複合材料，且包括疊層。
晶圓510係充分厚以提供期望的剛度、散耗熱、及/或其他期望性質。舉例來說，一些實施例使用200或300mm直徑且至少650微米厚度的一種單晶矽晶圓。在一些實施例中，要在該種結構中所作成之垂直接線的長度不必在選擇晶圓厚度時被納入考量，因為接線長度並非由晶圓 厚度所界定。
孔穴304係形成在晶圓510的頂表面之中，例如：藉由一種遮罩蝕刻。若期望時，多次蝕刻可用不同的遮罩而被使用，以提供如在圖4之一種階梯狀的側壁。一個示範的孔穴深度為400微米或更小。垂直接線將通過該孔穴的底壁部304B。
吾人將晶圓510的頂側稱為“孔穴側”，且將底側稱為“非孔穴側”。此外，吾人將該孔穴側稱為“頂側”，且總將其顯示在頂部，即使晶圓可在製造或操作期間被顛倒或以任何角度來翻轉。同理，吾人將該非孔穴側稱為“底側”。
若多個插入物被製造在同個晶圓之中，則多個孔穴304可被同時形成。該多個插入物可被同時作成，且晶圓可稍後被切塊以分割該等插入物。為了簡明，僅有一個插入物將被顯示。
該孔穴的側向限度係由周邊壁部304P所界定。該等壁部為充分寬(水平地)以提供期望的剛度且使該孔穴的底壁部304B與整個晶圓510保持平坦。
接著(圖5B.1)孔514.0被作成為通過該孔穴的底壁部304B以容納該等垂直接線的底部段。圖5B.2係該種結構的俯視圖，其具有一個陣列的孔514.0。該等孔可為任何數目，且可具有任何幾何形狀(如在圖5B.2之圓形、方形、或一些其他形狀)。
該等孔可由一種遮罩蝕刻來作成。該遮罩可被作成在非孔穴側，且該蝕刻可從該非孔穴側來進行。替代而言，遮罩與蝕刻可從孔穴側來實行。非遮罩技術亦可被使用，例如：從該孔穴或非孔穴側之雷射剝蝕 或衝壓(衝壓是適用在若插入物為由諸如軟塑膠的一種軟材料所作成)。其他方法亦可被使用。對於可模造材料(例如：塑膠)而言，圖5B.1與圖5B.2的結構可無需任何的蝕刻或遮罩而藉由模造來作成。
孔514.0將含有用於垂直接線之導電的基板穿孔(TSV,through-substrate via)。高密度TSV之習用的形成係一個有挑戰的過程，因為一方面而言，該等TSV是為了高密度而應為窄，且另一方面而言，該基板必須為厚以提供機械強度。作成其通過一個厚的基板之窄的TSV為困難。然而，圖5B.1、圖5B.2的晶圓係藉由周邊壁部304P而為強化，且該等TSV僅通過底壁部304B。若底壁部304B為薄，該等TSV可為窄且因此可為較高的密度。在一些矽的實施例中，該底壁部的厚度為20微米或更小。
若期望時，電路(未顯示)被形成在晶圓510之中，可能包括電晶體、二極體、電容器、及/或其他的電路元件。該電路可在孔穴304的形成之前且/或在任何其他製造階段而被形成在壁部304P及/或304B之中。
吾人將孔514.0稱為“階層0孔”或“階層L0孔”。其他的孔將被作成在更高的階層，如下文所述。(為了易於描述，吾人使用階層的概念；本發明是有關於結構及方法而非關於任何描述技術。)
若晶圓510係由非介電材料(例如：矽)所作成，介電質518(圖5C)可被形成在孔的側壁上。該介電質可覆蓋整個晶圓，如同在圖5C，或可覆蓋僅為該等孔的表面且如需要時而可能為另外的區域。若該介電質覆蓋整個晶圓，並不需要任何遮罩。若該介電質覆蓋僅為孔的表面，該介電質可使用其被用以形成該等孔514.0之同個遮罩(未顯示)來形成(舉例來說，該介電質可藉由一種剝離過程而型樣化)。
該介電質係可藉由濺鍍(此為適用於二氧化矽、氮化矽、與一些其他介電材料)、或熱氧化(若晶圓是由矽或其氧化物為介電的一些其他可氧化材料所作成)、或藉由一些其他過程所形成。上述的過程與介電材料並非為限制性。
若期望時，一個障壁層(未顯示)可被形成在該等孔中與別處的介電質518之上，以保護該晶圓為免於受到後續形成的材料(例如：金屬)之汙染。
如在圖5D所示，孔514.0係用導電材料520.0來填充(或內襯)以形成TSV，其將作用為接線段。此可藉由濺鍍或其他的技術來完成，例如：電鍍(其費用為相當低廉)。在圖5D的實例中，電鍍係使用形成的一個晶種(seed)層520S以覆蓋該非孔穴側。該晶種層可能或可能未進入該等孔514.0之中。在示範的實施例中，該晶種層係藉由濺鍍所形成的銅。為了防止銅形成在頂部(孔穴)側，濺鍍可為以某個角度來實行，即：該晶圓可為傾斜以防止銅分子為透過該等孔而到達該孔穴。替代而言，該晶種層可為經疊層在非孔穴側上的金屬薄片(例如：銅箔)。其他技術亦可被使用。
然後，該種結構被置放在一種電鍍槽(未顯示)，且晶種層520S被連接到一個電源的一個端子534以作為在電鍍操作中的一個陰極。結果，孔514.0被電鍍具有導體520.0，例如：銅。導體520.0填充該等孔514.0，且因此將接觸墊提供在孔穴底部，即：在底壁部304B的頂表面。該等接觸墊可能比該等孔514.0為寬。
導體520.0可包括在不同的電鍍及/或無電式電鍍步驟中所作成的多層。
如在圖5D所示，若晶種510S並未從底部所遮罩，導體亦可被電鍍在晶種層的底部上。經電鍍在晶種層的底部上之導體是在圖5D被標示為520'，但未被單獨標示在後續圖式中。而，為了簡化圖式，對於晶種層與導體520'，吾人均使用標號520S，吾人將二層均稱為“晶種層520S”。
導體520.0、520S可包括多個導電層。在一些實施例中，導體的頂表面(在該等孔穴內)可使用作為用於其他接線段之電鍍的晶種，如下所述。
一個選用式保護層532(圖5E)(例如：聚醯亞胺或一些其他有機聚合物)可被沉積在層520'的底表面上，以保護該種結構且避免在後續的電鍍步驟中之在該底表面上的電鍍。
一個或多個晶粒110被置放到該孔穴中而在底壁部304B之上。三個晶粒110A、110B、110C被顯示，且可能存在任何數目。該等晶粒的接觸墊110C被附接到個別的接觸墊520.0(藉由諸如上述的140之連接，例如：焊錫、黏著劑、熱壓縮、或可能其他型式(可能為離散的接線)；不同的連接可被使用於同個結構中的不同晶粒)。吾人將此等晶粒稱為階層1晶粒或階層L1晶粒或L1晶粒。
該等晶粒係藉由一種適合的介電囊封物524.1(在下文稱為階層1或L1“囊封物”)而為底部填充及囊封。底部填充可藉由毛細管或無流通技術來實行。囊封可藉由可模造材料之旋轉(spin-on)沉積及固化或可能藉由其他技術來實行。適合的底部填充劑及囊封物材料可為習用者，包括具有適合的填充劑之有機聚合物樹脂(諸如：苯環丁烯(BCB,benzocyclobutene)或環氧樹脂)、或可能其他型式。吾人將該底部填充劑及囊封物稱為“囊封 物524.1”。
在圖5E，囊封物524.1延伸到高達晶粒510B與510C的頂部表面，因此為側向及在下面囊封此等晶粒，但該囊封物並未覆蓋此等晶粒。囊封物524.1覆蓋晶粒110A。該囊封物可延伸到任何階層，尤其是可覆蓋超過一個晶粒，且/或反之為可終止在該等晶粒之一者或多者的頂部表面之下。頂部表面階層可藉由降低在沉積後的囊封物階層而作調整，該沉積為例如：使用化學蝕刻或藉由研磨物(例如：乾式或濕式噴砂)之蝕刻。
一些接觸墊520.0並未由任何的L1晶粒110所覆蓋。
孔514.1(圖5F)被形成在囊封物中以暴露出其未由L1晶粒110所覆蓋的接觸墊520.0。吾人將孔514.1稱為階層1或L1孔。用於作成L1孔514.1之一種適合的過程取決於囊封物的材料。舉例來說，對於樹脂而言，雷射剝蝕可被使用，其為一種在通過模具穿孔(TMV,through-mold via)之製造中的已知技術。若囊封物為可光成像，則光刻技術可被使用，即：透過一種基於玻璃的遮罩而曝光且隨後為在一種顯影液之中的顯影。此等實例並非為限制性。
L1孔514.1係暴露出接觸墊520.0。該等孔被填充或內襯有導體520.1(圖5G)以形成階層L1接線段。段520.1可為藉由電鍍所形成；電鍍電流可透過晶種層520S與L0接線段520.0而從非孔穴側來提供，藉由將該晶種層連接到一個電源的端子534。導體520.1填充(或內襯)L1孔514.1，且因此提供在L1囊封物524.1的頂表面之接觸墊(“L1接觸墊”)。該等L1接觸墊可能比該等L1孔514.1為寬。
此過程可被持續任何次數，以建立任何數目個階層。舉例來 說，圖5H-5L說明階層L2形成。包括晶粒110D之一個或多個晶粒110(“L2晶粒”)被附接在階層L1的頂部上；該等晶粒的接觸墊被附接到L1接觸墊520.1。在此實施例中，晶粒110D是在頂部與底部上均具有接觸墊112。頂部的接觸墊112將被附接到覆在上面的電路(尚未形成)。
L2囊封物524.2被形成以底部填充及囊封L2晶粒。L2孔514.2(圖5I)被形成在L2囊封物524.2之中以暴露其並未由一個晶粒所覆蓋的彼等L1接觸墊520.1。L2孔514.2被填充或內襯有導體520.2(圖5J)，其提供L2接線段。導體520.2可為藉由電鍍所形成；電鍍電流可透過晶種層520S與較低階層的接線段520.0而從底側來提供，藉由將晶種層520S連接到一個電源的端子534。L2接線段520.2接觸在下面的L1接線段520.1，且提供在L2囊封物524.2的頂表面之接觸墊。該等接觸墊可能比該等L2孔514.2為寬。該等L2特徵可使用如同對於階層L1之上述的相同過程來形成。
圖5K係顯示一種最終的結構，其具有四個階層與在頂部上的一個散熱片540。階層L3包括一個晶粒110E，其一些底部接觸墊被附接到階層L2接觸墊520.2(未標示在此圖中)。晶粒110E的其他底部接觸墊被附接到L2晶粒110D的頂部接觸墊112。L3晶粒110E是藉由囊封物524.3所底部填充且側向囊封，囊封物524.3是由可模造材料所作成。L3接線段520.3是通過囊封物524.3的垂直段。L4晶粒110F具有底部接觸墊，其被附接到L3晶粒110E的頂部接觸墊且附接到接線段520.3(到由此等段所提供的頂部接觸墊)。L3接線段520.3可藉由電鍍來形成；電鍍電流可從底側而透過較低階層的接線段520.0、520.1、520.2來提供。L4晶粒110F是藉由囊封物524.4而為底部填充及側向囊封，囊封物524.4是由可模造材料所作成。 L4接線段520.4是通過囊封物524.4的垂直段。例如晶粒、MCM、或離散接線或其他離散構件之外部電路(未顯示)可被附接到段524.4的頂端。該等頂端可被形成以利於此類的附接；舉例來說，若附接將為藉由焊錫，則諸如鎳的一個障壁層可被電鍍或非電式電鍍以保護段524.4的下面部分為免於焊錫汙染；且，金可被電鍍或非電式電鍍在段524.4的頂部上以阻止在焊接期間的氧化。
圖5K的結構係包括一個垂直接線510T，其不具有電氣功能性而為提供熱移除。此接線是由階層0到階層4的垂直段520(即：520.0、520.1、520.2、520.3、520.4)所組成。此接線延伸到散熱片540。頂部階層段520.4可藉由電鍍來形成；電鍍電流可從底側而透過較低階層的接線段520.0、520.1、520.2、520.3來提供。任何數目個熱移除接線可被提供；該等熱移除接線可能或可能未延伸到散熱片。
頂部階層L4包括接線段520.4，其提供在囊封物520.4的頂部而和散熱片540為並排的接觸墊。此等接觸墊可被連接到外部電路，如上所述。
在一些實施例中，各個囊封層524係在一個單獨的操作中被沉積及固化；該囊封層不具有任何單獨固化的子層。因此，該囊封層不具有其將會存在於子層之間的任何內部表面邊界。一個內部表面邊界係由表面狀態來描述其特徵。一個表面狀態係具有分子能量為高於該表面下方之一種狀態；表面狀態可由視覺來偵測(可能使用顯微鏡觀察)或可能藉由超音波或其他方式。然而，本發明不受限於此類的實施例。
在一些實施例中，若一個階層Li的一個或多個晶粒110係 以不同於側向囊封的一種操作而底部填充，且該底部填充劑被個別固化，則囊封層可具有在該底部填充劑與該囊封物的側向囊封部分之間的邊界的一個表面。再者，該側向囊封部分可由不同於該底部填充劑的一種材料所作成。
在所有階層的製造之後或在製造期間的任何點，該插入物的底部可被處理以任何期望方式來將保護層532與導體520S移除或型樣化。在圖5L，保護層532被移除，且該導體被薄化及型樣化以提供在接線段520.0的末端之接觸墊120C.B。此等接觸墊可被附接到其他晶粒、MCM、或諸如PCB或插入物的封裝基板。替代而言，其他電路可被形成在底部上，例如：作為包括多個介電、導電、與半導體層之一個重新分佈層(RDL,redistribution layer)的部分者，其提供電路為經耦合到接線段520.0且可從在插入物下方所接近。該重新分佈層可具有在底部的接觸墊，其可被耦合到其他晶粒、MCM、或諸如PCB或插入物的封裝基板。
圖6係顯示其可在一些實施例中為可用之另外的特徵。在此，階層L3包括一個重新分佈層610.3，其具有由介電層所分開的若干個導電層。該等導電層提供互連件620.3，其垂直及側向(可能為水平)延伸。互連件620.3終止在該RDL之頂部的接觸墊630.3。如所期望，互連件620.3將在下面的接線段520.2與在上面的接線段520.3互連。在一些實施例中，RDL 610.3的介電層是由如同囊封層524(例如：藉由一種旋轉過程所沉積之可模造的有機聚合物、或來自上述的其他材料)之相同或類似的材料所形成，且藉由相同的技術(例如：光刻技術或雷射剝蝕)而為型樣化。該等導電層亦可藉由其他的沉積與型樣化技術來形成，例如：使用光刻技術或藉由 附加的製造(印製)。
在圖6的實例中，一些RDL線路620.3將L2接線段520.2連接到L3接線段520.3。一條線路620.3將L2晶粒110E的一個頂部接觸墊112連接到一個L2接線段520.2的頂部。另一條線路620.3將一個L2接線段520.2連接到L3晶粒110F的一個底部接觸墊。
如必要時，在線路620.3的末端之接觸墊630.3可提供一個區域陣列型樣或其他型樣以供連接到L3晶粒與接線段。
在一些實施例中，階層L2包括一個晶粒，其不具有底部接觸墊而僅具有由RDL 610.3所連接到其他電路的頂部接觸墊。任何階層均可包括其不具有底部接觸墊而具有附接到在該孔穴內或外的其他電路的頂部接觸墊之一個晶粒。此外，一個晶粒可不具有頂部接觸墊。在圖7的實例中，晶粒110E不具有頂部接觸墊，再者，L2囊封物524.2覆蓋該晶粒，且RDL 610.3覆蓋該囊封物。
階層L3接線段520.3(圖6、7)可藉由電鍍而形成在RDL 610.3的頂部；電鍍電流是透過接線段620.3而從底層520S被導通到RDL 610.3的頂部。
L4接線段520.4與其個別在下面的L3段520.3係用於熱移除。
以上，RDL 610.3係關聯於階層L3，但此僅為術語的問題：吾人可稱RDL 610.3係階層L2的部分者。一個RDL可被提供在任何階層。此外，多個交替的RDL與囊封層可被提供在單一層中，即：用於附接到前個階層之單一組的晶粒110。
基板510可由不同的基板所組裝，且一個實例被顯示在圖8A(垂直橫截面)與圖8B(比圖8A為小的刻度之俯視圖)。在此實例中，基板510包括一個平面基板510.1與其附接到平面基板510.1的一個基板510.2。該附接是藉由黏著劑810，但直接黏合亦可被使用。在圖8B之中，多個基板510.2(下文稱為“框架”)被附接到單一個平面基板510.1，且多個結構是由圖7的型式或上述的其他型式而被形成在同個平面基板510.1。在製造結束時或在任何其他製造階段，平面基板510.1可沿著通過在框架510.2之間的直線(未顯示)而切割。
平面基板510.1與框架510.2可由相同或不同材料所作成，包括用於晶圓510之上述的任何材料。若存在時，黏著劑810可為任何適合的黏著劑，例如：塑膠，其為以可流通的形式所沉積且接著使用熱、壓力、輻射、及/或其他方式所固化。非可流通的黏著劑亦可被使用。基板510可包括超過二個基板之一種堆疊，例如：各個框架510.2或平面基板510.1可為多個基板之一種疊層。
不論基板510是否為多個基板的一個組件，基板510(以及若存在時的各個構成基板)可為一種一致或非一致的媒體，即：在各個內部點可能或可能未具有相同的物體性質。在一些實施例中，基板510係關於以下性質的任一者或多者而為一致：化學組成、密度、彈性模數、導電性、介電常數、對於一個或多個波長(可能為所有超音波(US,ultrasound)波長)的超音波(US)傳播速度、對於一個或多個波長(例如：在紅外線範圍與以下的波長)的光波傳播速度。舉例來說，一致的基板510可為單一晶體(例如：單晶矽)，且可為有機或無機，且可為一種複合材料或上述的其他材料。此等 實例並非為限制性。若基板510為諸如510.1與510.2的多件之一種組件，則在一些實施例中，相鄰的諸件之一個介面區域(該區域包括該二件的相鄰部分)是關於上文所述的性質之至少一者為不一致，即：化學組成、密度、彈性模數、導電性、介電常數、對於一個或多個波長的超音波傳播速度、對於一個或多個波長的光波傳播速度。舉例來說，在圖7A，該介面區域被界定為包括黏著劑810以及基板510.1與510.2的相鄰表面，且若該黏著劑具有不同於基板510.1或510.2的相鄰表面之化學組成，該介面為不一致。若該附接是藉由基板510.1之直接黏合到基板510.2且該等基板是由相同的材料(例如：矽)所作成，該介面可為一致，且該基板510可與單一件所初始作成的一個基板為難以分辨。然而，該介面亦可關於光或聲音傳播速度為不一致，例如：若該介面包括可由超音波(US)或頻譜成像所偵測的氣泡或其他狀態。
本發明不受限於上述的實施例。其他的實施例與變化是在本發明的範疇內，如由隨附的申請專利範圍所界定。
110A、110B、110C、110D、110E、110F、110G‧‧‧晶粒
112‧‧‧接觸墊
120C.B‧‧‧接觸墊
520.0、520.1、520.2、520.3、520.4‧‧‧接線段
524.2、524.3、524.4‧‧‧囊封物
610.3‧‧‧重新分佈層(RDL)
620.3‧‧‧互連件

Claims (21)

  1. 一種電路組件，其包含複數個階層L0到Ln，其中n係大於1的一個整數，該電路組件包含一個基板，其頂側包含一個孔穴，該孔穴包含一個底壁部；其中該階層L0包含：該底壁部；複數個通孔，其之每一個通過該底壁部；在個別的通孔中的複數個導體(“L0導體”)；其中對於除了L0與L1之外的各個階層Li：至少部分的階層Li係覆在至少部分的階層Li-1之上；各個階層Li包含一個或多個電路模組，其之每一個具有一個或多個接觸墊，各個接觸墊係藉由置於該孔穴中的一個或多個第一導電路徑而被電氣連接到一個或多個L0導體。
  2. 如申請專利範圍第1項之電路組件，其中該基板包含：第一基板，其包含該底壁部；及第二基板，其包含該孔穴的側壁部，該第二基板被附接到該第一基板；其中該第一與第二基板的一個介面區域係關於以下的至少一者而為不一致：化學組成、密度、彈性模數、導電性、介電常數、對於一個或多個波長的超音波傳播速度、對於不超過紅外線波長之一個或多個波長的光波傳播速度。
  3. 如申請專利範圍第1項之電路組件，其更包含：由一種可模造材料所作成的複數個第一囊封層，其中各個階層L1到Ln-1包含至少一個第一 囊封層，其側向囊封在該階層的該一個或多個電路模組。
  4. 如申請專利範圍第3項之電路組件，其中各個第一囊封層的至少第一部分係至少上升為高達其由該第一囊封層所側向囊封的至少一個電路模組的一個頂表面；其中各個第一囊封層的至少該第一部分係至少下降為低達其由該第一囊封層所側向囊封的至少一個電路模組的一個底表面；其中各個第一囊封層的至少該第一部分係在單一個固化操作中被形成而不具有個別固化的子層。
  5. 如申請專利範圍第4項之電路組件，其中對於通過任何第一囊封層的各個第一導電路徑，該第一導電路徑包含其通過該第一囊封層的一個垂直段。
  6. 如申請專利範圍第3項之電路組件，其中i大於0之至少一個階層Li包含在其通過該階層的第一囊封層之至少一個第一導電路徑中的至少一個水平段，該水平段係低於該階層的第一囊封層。
  7. 如申請專利範圍第6項之電路組件，其中該水平段係覆在階層Li-1的該第一囊封層與階層Li-1的至少一個晶粒之上，該晶粒係由階層Li-1的該第一囊封層所覆蓋。
  8. 如申請專利範圍第3項之電路組件，其更包含：在該孔穴中的一個或多個第二導電路徑，其中各個第二導電路徑不具有電氣功能性而為用於加強從該電路組件到周圍的熱移除，其中各個第二導電路徑係從一個L0導體而延伸通過除了L0之外的一個或多個階層且用於除了L0之外的各個階層。
  9. 如申請專利範圍第3項之電路組件，其中各個第一囊封層具有一個平面的頂表面。
  10. 如申請專利範圍第1項之電路組件，其中通過該底壁部的各個通孔係垂直，且各個L0導體係垂直。
  11. 一種製造方法，其包含：得到一種結構，其包含：一個基板，其頂側包含一個孔穴，該孔穴包含一個底壁部，該基板包含複數個通孔(“L0通孔”)，其之每一個通過該底壁部；複數個導體(“L0導體”)，其之每一個通過個別的L0通孔；一個導電層，其置於該底壁部之下且被電氣連接到各個L0導體；將一個或多個電路模組(“L1電路模組”)附接到該孔穴的一個底部以將各個L1電路模組的一個或多個接觸墊電氣連接到一個或多個L0導體；形成一種可模造材料的一個囊封層(“L1囊封層”)以側向囊封該一個或多個L1電路模組；形成在該L1囊封層之中的一個或多個通孔(“L1通孔”)，各個L1通孔暴露出其為由至少一個L0導體所提供或經電氣連接到該至少一個L0導體的一個特徵；且將導電材料電鍍到該等L1通孔中而在由該等L1通孔所暴露的該等特徵上，以形成一個或多個L1導體，各個L1導體通過個別的L1通孔，其中該電鍍包含提供一個電鍍電流，其流通過該等特徵、該等L0導體、該導電層、及經耦合到該導電層之一個電源的一個端子。
  12. 如申請專利範圍第11項之方法，其中該基板包含：第一基板，其包含該底壁部；及第二基板，其包含該孔穴的側壁部，該第二基板被附接到該第一基板；且得到該種結構包含：將該第一基板附接到該第二基板以提供該基板。
  13. 如申請專利範圍第11項之方法，其更包含：形成在該孔穴的底部上之一個重新分佈層，其中該等特徵係在該重新分佈層的一個頂部上，該重新分佈層係將該等特徵電氣連接到該等L0導體。
  14. 如申請專利範圍第11項之方法，其更包含：將一個或多個電路模組(“L2電路模組”)附接在該孔穴內以將各個L2電路模組的一個或多個接觸墊電氣連接到一個或多個L1導體；形成一種可模造材料的一個囊封層(“L2囊封層”)以側向囊封該一個或多個L2電路模組；形成在該L2囊封層之中的一個或多個通孔(“L2通孔”)，各個L2通孔暴露出其為由至少一個L1導體所提供或經電氣連接到該至少一個L1導體的一個特徵；且將導電材料電鍍到該等L2通孔中而在由該等L2通孔所暴露的該等特徵上，以形成複數個L2導體，各個L2導體係通過個別的L2通孔，其中該電鍍包含提供一個電鍍電流，其流通過該等L1導體、該等L0導體、該導電層、及經耦合到該導電層之一個電源的一個端子。
  15. 一種電路組件，其包含：一個基板，其頂側包含一個孔穴，該孔穴包含一個底壁部； 複數個通孔，其之每一個通過該底壁部；在個別的通孔中的複數個導體；在該孔穴中的複數個電路模組，各個電路模組具有一個或多個接觸墊；在該孔穴中而覆在彼此之上的複數個第一囊封層，其中各個第一囊封層係由一種可模造材料所作成且側向囊封該等電路模組的一者或多者；複數個第一導電路徑，其之每一個置於該孔穴中且通過一個或多個第一囊封層以將至少一個電路模組的至少一個接觸墊連接到其通過該底壁部的至少一個導體。
  16. 如申請專利範圍第15項之電路組件，其中該基板包含：第一基板，其包含該底壁部；及第二基板，其包含該孔穴的側壁部，該第二基板被附接到該第一基板；其中該第一與第二基板的一個介面區域係關於以下的至少一者而為不一致：化學組成、密度、彈性模數、導電性、介電常數、對於一個或多個波長的超音波傳播速度、對於不超過紅外線波長之一個或多個波長的光波傳播速度。
  17. 如申請專利範圍第15項之電路組件，其中各個第一囊封層的至少第一部分係至少上升為高達其由該第一囊封層所側向囊封的至少一個電路模組的一個頂表面；其中各個第一囊封層的至少該第一部分係至少下降為低達其由該第一囊封層所側向囊封的至少一個電路模組的一個底表面；其中各個第一囊封層的至少該第一部分係在單一個固化操作中被形成而不具有個別固化的子層。
  18. 如申請專利範圍第17項之電路組件，其中各個囊封層具有一個平面的頂表面。
  19. 如申請專利範圍第15項之電路組件，其更包含：一個或多個水平的導電互連件，其之每一個屬於通過覆在該水平的導電互連件之上的第一囊封層之至少一個第一導電路徑。
  20. 如申請專利範圍第15項之電路組件，其更包含：在該孔穴中的一個或多個第二導電路徑，其中各個第二導電路徑不具有電氣功能性而為用於加強從該電路組件到周圍的熱移除，其中各個第二導電路徑係開始在該通孔中的一個導體且延伸通過該等囊封層的一者或多者。
  21. 如申請專利範圍第15項之電路組件，其中通過該底壁部的各個通孔係垂直，且在該底壁部中的各個通孔之中的各個導體係垂直。
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