CN112670249A - 半导体封装方法、半导体封装结构及封装体 - Google Patents

半导体封装方法、半导体封装结构及封装体 Download PDF

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Publication number
CN112670249A
CN112670249A CN201910982076.1A CN201910982076A CN112670249A CN 112670249 A CN112670249 A CN 112670249A CN 201910982076 A CN201910982076 A CN 201910982076A CN 112670249 A CN112670249 A CN 112670249A
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Prior art keywords
semiconductor
semiconductor die
conductive
substrate wafer
electrically connected
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CN201910982076.1A
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English (en)
Inventor
刘杰
应战
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN201910982076.1A priority Critical patent/CN112670249A/zh
Priority to PCT/CN2020/096254 priority patent/WO2021073133A1/zh
Priority to EP20877686.4A priority patent/EP4047639A4/en
Publication of CN112670249A publication Critical patent/CN112670249A/zh
Priority to US17/372,530 priority patent/US11990451B2/en
Pending legal-status Critical Current

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Abstract

本发明提供一种半导体封装方法、半导体封装结构及封装体，所述封装方法包括如下步骤：提供衬底晶圆，衬底晶圆具有相对设置的第一表面及第二表面，在第一表面具有多个凹槽，在凹槽底部具有多个导电柱，导电柱贯穿凹槽底部至第二表面；提供多个半导体裸片堆叠体；将半导体裸片堆叠体置于凹槽中，半导体裸片堆叠体的上表面低于或者平齐于凹槽的上边缘，半导体裸片堆叠体的底部与导电柱电连接；在凹槽的侧壁与半导体裸片堆叠体之间的间隙内充满绝缘介质，形成绝缘介质层，且绝缘介质层覆盖半导体裸片堆叠体的上表面，以密封半导体裸片堆叠体，形成半导体封装结构。本发明的优点在于，形成的半导体封装结构封装高度低、稳固性高、可靠性高及翘曲度低。

Description

半导体封装方法、半导体封装结构及封装体
技术领域
本发明涉及半导体封装领域，尤其涉及一种半导体封装方法、半导体封装结构及封装体。
背景技术
堆叠式封装技术，也称为3D或三维封装技术，是目前主流的多芯片封装技术之一，能够将至少两个半导体晶片(Die，也称为裸片，即从晶圆上切割出来的一块具有完整功能的块)在垂直方向叠加起来，常用来制造存储器芯片、逻辑芯片、处理器芯片等电子元件。随着电子产业的发展，需要电子元件的高容量、高功能、高速和小尺寸。为了满足上述需求，需要在单个封装中并入更多晶片，而这会造成电子元件的封装高度变高，且在半导体封装结构移动或者振动的情况下，晶片之间可能会存在微小错位，导致封装体结构的可靠性变低，影响封装体结构的性能。
因此，如何降低封装体的封装高度，提高封装体的可靠性成为目前亟需解决的技术问题。
发明内容
本发明所要解决的技术问题是，提供一种半导体封装方法、半导体封装结构及封装体，其能够具有封装高度低、可靠性高及翘曲度低的特点。
为了解决上述问题，本发明提供了一种半导体封装方法，其包括如下步骤：提供衬底晶圆，所述衬底晶圆具有相对设置的第一表面及第二表面，在所述第一表面具有多个凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；提供多个半导体裸片堆叠体；将所述半导体裸片堆叠体置于所述凹槽中，所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；在所述凹槽的侧壁与所述半导体裸片堆叠体之间的间隙内充满绝缘介质，形成绝缘介质层，且所述绝缘介质层覆盖所述半导体裸片堆叠体的上表面，以密封所述半导体裸片堆叠体，形成半导体封装结构。
进一步，在所述衬底晶圆的第二表面具有多个导电块，所述导电块与所述导电柱电连接。
进一步，在所述衬底晶圆上形成凹槽的方法包括如下步骤：对所述衬底晶圆的第一表面进行平坦化处理；自所述第一表面去除部分所述衬底晶圆，至暴露出所述导电柱，形成所述凹槽。
进一步，所述衬底晶圆具有切割道，以所述切割道作为形成所述凹槽的对准标记。
进一步，所述半导体裸片堆叠体由多个半导体裸片堆叠形成，所述半导体裸片之间电连接，并通过所述半导体裸片堆叠体的底部与所述导电柱电连接。
进一步，所述半导体裸片之间通过贯穿各所述半导体裸片的导电柱及相邻所述半导体裸片间的导电块电连接。
进一步，所述半导体裸片堆叠体的底部与贯穿所述凹槽底部的导电柱之间通过导电块电连接。
进一步，所述衬底晶圆的热膨胀系数大于或者等于所述绝缘介质层的热膨胀系数。
进一步，所述衬底晶圆为硅晶圆，所述绝缘介质层为二氧化硅绝缘介质层。
进一步，所述半导体封装方法还包括如下步骤：在所述绝缘介质层的上表面及所述衬底晶圆的第一表面覆盖盖板晶圆。
进一步，所述盖板晶圆朝向所述衬底晶圆的表面具有多个导电柱，所述导电柱通过所述绝缘介质层中的导电结构与所述半导体裸片堆叠体的上表面电连接。
进一步，在密封所述半导体裸片堆叠体的步骤后，还包括切割步骤：沿凹槽之间的间隙切割所述半导体封装结构，形成多个彼此独立的封装体。
本发明还提供一种半导体封装结构，其包括：衬底晶圆，所述衬底晶圆具有相对设置的第一表面及第二表面，在所述第一表面具有多个凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；多个半导体裸片堆叠体，放置在所述凹槽内，且所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；绝缘介质层，充满所述凹槽的侧壁与所述半导体裸片堆叠体之间的间隙，且所述绝缘介质层覆盖所述半导体裸片堆叠体的上表面，以密封所述半导体裸片堆叠体。
进一步，在所述衬底晶圆的第二表面具有多个导电块，所述导电块与所述导电柱电连接。
进一步，所述半导体裸片堆叠体由多个半导体裸片堆叠形成，所述半导体裸片之间电连接，并通过所述半导体裸片堆叠体的底部与所述导电柱电连接。
进一步，所述半导体裸片之间通过贯穿各所述半导体裸片的导电柱及相邻所述半导体裸片间的导电块电连接。
进一步，所述半导体裸片堆叠体的底部与贯穿所述凹槽底部的导电柱之间通过导电块电连接。
进一步，所述衬底晶圆的热膨胀系数大于或者等于所述绝缘介质层的热膨胀系数。
进一步，所述衬底晶圆为硅晶圆，所述绝缘介质层为二氧化硅绝缘介质层。
进一步，在所述绝缘介质层的上表面及所述衬底晶圆的第一表面覆盖盖板晶圆。
进一步，所述盖板晶圆朝向所述衬底晶圆的表面具有多个导电柱，所述绝缘介质层中设置有导电结构，所述导电柱通过所述导电结构与所述半导体裸片堆叠体的上表面电连接。
本发明还提供一种封装体，其包括：衬底，所述衬底具有相对设置的第一表面及第二表面，在所述第一表面具有至少一凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；至少一半导体裸片堆叠体，放置在所述凹槽内，所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；绝缘介质层，充满所述凹槽的侧壁与所述半导体裸片堆叠体之间的间隙，且所述绝缘介质层覆盖所述半导体裸片堆叠体的上表面，以密封所述半导体裸片堆叠体。
本发明的优点在于，在衬底晶圆上形成凹槽来容纳半导体裸片堆叠体，并通过绝缘介质层进行密封，能够在封装相同数量的半导体裸片的同时，大大降低半导体封装结构的高度，实现超薄封装。另外，所述绝缘介质层填充在所述凹槽的侧壁与所述半导体裸片堆叠体之间的间隙内，所述绝缘介质层能够固定所述半导体裸片堆叠体，避免其在移动或者振动时半导体裸片之间发生错位，造成半导体裸片之间及半导体裸片堆叠体与衬底晶圆之间连接不良，提高半导体裸片堆叠体的稳固性，提高半导体封装结构的可靠性。
附图说明
图1是本发明半导体封装方法的一具体实施方式的步骤示意图；
图2A～图2H是本发明半导体封装方法的一具体实施方式的流程示意图；
图3是本发明半导体封装结构的一具体实施方式的结构示意图；
图4是本发明封装体的一具体实施方式的结构示意图。
具体实施方式
下面结合附图对本发明提供的半导体封装方法、半导体封装结构及封装体的具体实施方式做详细说明。
图1是本发明半导体封装方法的一具体实施方式的步骤示意图。请参阅图1，所述半导体封装方法包括如下步骤：步骤S10，提供衬底晶圆，所述衬底晶圆具有相对设置的第一表面及第二表面，在所述第一表面具有多个凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；步骤S11，提供多个半导体裸片堆叠体；步骤S12，将所述半导体裸片堆叠体置于所述凹槽中，所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；步骤S13，在所述凹槽的侧壁与所述半导体裸片堆叠体之间的间隙内充满绝缘介质，形成绝缘介质层，且所述绝缘介质层覆盖所述半导体裸片堆叠体的上表面，以密封所述半导体裸片堆叠体，形成半导体封装结构；步骤S14，在所述绝缘介质层的上表面及所述衬底晶圆的第一表面覆盖盖板晶圆；步骤S15，沿凹槽之间的间隙切割所述半导体封装结构，形成多个彼此独立的封装体。
图2A～图2H是本发明半导体封装方法的一具体实施方式的流程示意图。
请参阅步骤S10及图2C，提供衬底晶圆200，所述衬底晶圆200具有相对设置的第一表面200A及第二表面200B。在所述第一表面200A具有多个凹槽201，在所述凹槽201底部具有多个导电柱202，所述导电柱202贯穿所述凹槽201底部至所述第二表面200B。
下面举例说明形成所述凹槽201的一具体实施方式。
请参阅图2A，所述衬底晶圆200具有相对设置的第一表面200A及第二表面200B。其中，所述第一表面200A为所述衬底晶圆200的背面，所述第二表面200B为所述衬底晶圆200的正面，即在所述第二表面200B，所述衬底晶圆200具有功能层200C。所述导电柱202自所述第二表面200B向所述衬底晶圆200内部延伸，且所述导电柱202的表面暴露于所述第二表面200B。所述导电柱202不仅可起到导电的作用，还可起到导热的作用。
请参阅图2B，对所述衬底晶圆200的第一表面200A进行平坦化处理，以便于后续工艺的进行。进一步，可采用化学机械研磨的方法对所述衬底晶圆200的第一表面200A进行平坦化处理。在该步骤中，所述衬底晶圆200被减薄。需要说明的是，在该步骤执行完毕后，所述衬底晶圆200的第一表面200A至所述第二表面200B的功能层200C的距离H要大于或者等于半导体裸片堆叠体210的高度，以为后续工艺提供足够的操作空间，所述凹槽201的宽度要大于或者等于半导体裸片堆叠体210的宽度，优选地，所述凹槽201的宽度略大于半导体裸片堆叠体210的宽度，以便于所述半导体裸片堆叠体210放置在所述凹槽201内。
请参阅图2C，自所述第一表面200A去除部分所述衬底晶圆200，至暴露出所述导电柱202，形成所述凹槽201。在该步骤中，可采用光刻与刻蚀工艺去除部分所述衬底晶圆200，当在所述凹槽201的底部暴露出所述导电柱202时停止刻蚀。进一步，在临近停止刻蚀时，可以通过调整刻蚀条件，使得凹槽201边缘刻蚀速率小于凹槽201中部刻蚀速率，从而使凹槽201底部边角处呈圆弧状，可以增强凹槽201侧壁的稳定性。
进一步，在该步骤中，所述衬底晶圆200具有切割道203，如图2C所示，切割道203经过相邻的两个凹槽201之间的间隙，则在形成所述凹槽201时，可将所述切割道203作为形成所述凹槽201的对准标记，从而提高形成所述凹槽201的精确度，且不需要额外制作对准标记，节省了工艺步骤，提高生产效率。
上述为在所述衬底晶圆200的第一表面200A形成凹槽201的一具体实施方式，在本发明其他具体实施方式中，也可采用其他方法在所述衬底晶圆200的第一表面200A形成凹槽201。
在本具体实施方式中，所述切割道203的宽度与两凹槽201之间的距离相同，在本发明其他具体实施方式中，凹槽201可占用部分切割道203的空间，使得两相邻凹槽201之间的距离小于切割道203的宽度，进而便于后续半导体裸片堆叠体210置于所述凹槽201内；另外还能够避免所述半导体裸片堆叠体210的侧面与所述凹槽201的侧壁接触，避免影响所述半导体裸片堆叠体210的性能。
进一步，请继续参阅图2A，在所述衬底晶圆200的第二表面200B具有多个导电块204，所述导电块204与所述导电柱202电连接，以将所述导电柱202电连接至外部器件，例如，印刷电路板。其中，所述导电块204可在形成所述凹槽201之前形成在所述衬底晶圆200的第二表面200B。
请参阅步骤S11及图2D，提供多个半导体裸片堆叠体210。所述半导体裸片堆叠体210的数量可与所述凹槽201的数量相同，或者所述半导体裸片堆叠体210的数量多于所述凹槽201的数量。具体地说，若所述半导体裸片堆叠体210的数量与所述凹槽201的数量相同，则在后续工艺中，在一个凹槽201内放置一个半导体裸片堆叠体210；若所述半导体裸片堆叠体210的数量多于所述凹槽201的数量，则在一个凹槽201内可并行放置两个及两个以上半导体裸片堆叠体210。
所述半导体裸片堆叠体210由多个半导体裸片210A堆叠形成，在本具体实施方式中，示意性地绘示三个半导体裸片210A。三个半导体裸片210A依次叠放，形成所述半导体裸片堆叠体210。在半导体裸片堆叠体210中，所述半导体裸片210A之间电连接，以使得所述半导体裸片210A的电信号能够被传递至外部结构。在本具体实施方式中，所述半导体裸片210A之间通过贯穿各所述半导体裸片的导电柱211及相邻所述半导体裸片间的导电块212电连接。每一所述半导体裸片210A均具有贯穿其的导电柱211，两个半导体裸片210A的导电柱211通过设置在两者之间的导电块212电连接。其中，在所述半导体裸片210A上形成导电柱的方法包括但不限于本领域公知的硅通孔(TSV)工艺。
其中，在该步骤实施完毕后，所述半导体裸片堆叠体210的底部暴露有导电柱的表面，所述半导体裸片堆叠体210的顶部也暴露有导电柱的表面。
请参阅步骤S12及图2E，将所述半导体裸片堆叠体210置于所述凹槽201中。在该步骤中，在一个所述凹槽201内可放置一个半导体裸片堆叠体210，也可放置多个半导体裸片堆叠体210。在本具体实施方式中，在一个凹槽201内放置一个半导体裸片堆叠体210。
所述半导体裸片堆叠体210的底部与贯穿所述凹槽201底部的导电柱202电连接。也就是说，在所述半导体裸片堆叠体210的底部暴露的导电柱211与所述凹槽201底部暴露的导电柱202电连接。具体地说，两者可通过导电块213电连接。
所述半导体裸片堆叠体210的上表面低于或者平齐于所述凹槽201的上边缘，以便于后续工艺的进行。在本具体实施方式中，所述半导体裸片堆叠体210的上表面低于所述凹槽201的上边缘。另外，为了便于所述半导体裸片堆叠体210放入所述凹槽201中，所述凹槽201的宽度大于或者等于所述半导体裸片堆叠体210的宽度，则在所述半导体裸片堆叠体210放入所述凹槽201中后，所述半导体裸片堆叠体210的侧面与所述凹槽201的侧壁之间具有间隙。
请参阅步骤S13及图2F，在所述凹槽210的侧壁与所述半导体裸片堆叠体210之间的间隙内充满绝缘介质，形成绝缘介质层230，且所述绝缘介质层230覆盖所述半导体裸片堆叠体210的上表面，以密封所述半导体裸片堆叠体210，形成半导体封装结构。
该步骤执行完毕，所述凹槽201被绝缘介质层230填满，所述半导体裸片堆叠体210被密封，半导体裸片堆叠体210的多个半导体裸片210A之间被彼此固定，且所述半导体裸片堆叠体210被相对于衬底晶圆固定，从而能够避免在移动或者振动时半导体裸片之间及半导体裸片堆叠体与衬底晶圆之间发生错位，造成半导体裸片之间及半导体裸片堆叠体与衬底晶圆之间连接不良，提高半导体裸片堆叠体的稳固性，提高半导体封装结构的可靠性。
另外，本发明半导体封装方法在衬底晶圆上形成凹槽来容纳半导体裸片堆叠体，并通过绝缘介质层进行密封，能够在封装相同数量的半导体裸片的同时，大大降低半导体封装结构的高度，实现超薄封装。
优选地，所述衬底晶圆200的热膨胀系数大于或者等于所述绝缘介质层230的热膨胀系数。其优点在于，在半导体封装结构受热时，所述绝缘介质层230的变形小于所述衬底晶圆200的变形，从而避免所述衬底晶圆200被迫变形，而影响半导体封装结构的可靠性及翘曲度。当然，所述衬底晶圆200的热膨胀系数与所述绝缘介质层230的热膨胀系数也不能差别太大，否则可能会造成绝缘介质层230与衬底晶圆200的凹槽201的侧壁之间脱离的情况发生。具体地说，在本具体实施方式中，所述衬底晶圆200为硅晶圆，所述绝缘介质层230为二氧化硅绝缘介质层。
可选地，所述半导体封装方法还包括如下步骤：请参阅步骤S14及图2G，在所述绝缘介质层230的上表面及所述衬底晶圆200的第一表面覆盖盖板晶圆220，以进一步密封所述半导体裸片堆叠体210。其中，所述盖板晶圆220与所述衬底晶圆200可通过键合工艺结合。
进一步，所述盖板晶圆220朝向所述衬底晶圆200的表面具有多个导电柱221，所述绝缘介质层230中也设置有导电柱231，则所述盖板晶圆220中的所述导电柱221可通过所述绝缘介质层230中的导电柱231与所述半导体裸片堆叠体210的上表面电连接，即，所述盖板晶圆220表面的所述导电柱221与所述半导体裸片堆叠体210的上表面暴露的导电柱211电连接，所述盖板晶圆220可通过所述导电柱221向所述半导体裸片堆叠体210提供热传导，并进一步固定所述半导体裸片堆叠体210的位置。另外，在半导体封装中，还可以在所述盖板晶圆220上堆叠其他晶圆，所述导电柱221可起到电连接的作用。。其中，在所述绝缘介质层230中设置导电柱231的步骤可在覆盖盖板晶圆220的步骤之前进行。
可选地，在步骤S13或者步骤S14之后，还包括一切割步骤。在本具体实施方式中，在步骤S14之后，还包括一切割步骤。请参阅步骤S15及图2H，沿凹槽201之间的间隙切割所述半导体封装结构，形成多个彼此独立的封装体。具体地说，沿凹槽201之间的切割道203切割，以形成多个彼此独立的封装体。所述切割方法包括但不限于机械切割、激光切割等。
本发明还提供一种采用上述半导体封装方法形成的半导体封装结构。图3是本发明半导体封装结构的一具体实施方式的结构示意图。请参阅图3，所述半导体封装结构包括衬底晶圆300、多个半导体裸片堆叠体310、绝缘介质层330及盖板晶圆320。
所述衬底晶圆300具有相对设置的第一表面300A及第二表面300B，在所述第一表面300A具有多个凹槽301，在所述凹槽301底部具有多个导电柱302，所述导电柱302贯穿所述所述凹槽301底部至所述第二表面300B。在所述衬底晶圆300的第二表面300B具有多个导电块304，所述导电块304与所述导电柱302电连接。
所述半导体裸片堆叠体310放置在所述凹槽301内，且所述半导体裸片堆叠体310的上表面低于或者平齐于所述凹槽301的上边缘，在本具体实施方式中，所述半导体裸片堆叠体310的上表面低于所述凹槽301的上边缘。所述半导体裸片堆叠体310的底部与所述导电柱302电连接。所述半导体裸片堆叠体由310由多个半导体裸片310A堆叠形成，所述半导体裸片310A之间可通过贯穿各所述半导体裸片310A的导电柱311及相邻所述半导体裸片310A间的导电块312电连接，并通过所述半导体裸片堆叠体310的底部与所述导电柱302电连接。其中，所述半导体裸片堆叠体310的底部与所述导电柱302之间可通过导电块313电连接。
所述绝缘介质层330充满所述凹槽301的侧壁与所述半导体裸片堆叠体310之间的间隙，且所述绝缘介质层330覆盖所述半导体裸片堆叠体310的上表面，以密封所述半导体裸片堆叠体310。所述衬底晶圆300的热膨胀系数大于或者等于所述绝缘介质层330的热膨胀系数。其优点在于，在半导体封装结构受热时，所述绝缘介质层330的变形小于所述衬底晶圆300的变形，从而避免所述衬底晶圆300被迫变形，而影响半导体封装结构的可靠性及翘曲度。当然，所述衬底晶圆300的热膨胀系数与所述绝缘介质层330的热膨胀系数也不能差别太大，否则可能会造成绝缘介质层330与衬底晶圆300的凹槽301的侧壁之间脱离的情况发生。具体地说，在本具体实施方式中，所述衬底晶圆300为硅晶圆，所述绝缘介质层330为二氧化硅绝缘介质层。
所述盖板晶圆320为可选结构，其覆盖在所述绝缘介质层330及所述衬底晶圆300的第一表面300A，以密封所述半导体裸片堆叠体310。进一步，所述盖板晶圆320朝向所述衬底晶圆300的表面具有多个导电柱321，所述绝缘介质层330中也具有导电柱331，所述盖板晶圆320的所述导电柱321通过所述绝缘介质层330中的导电柱331与所述半导体裸片堆叠体310的上表面电连接。具体地说，所述导电柱321与所述半导体裸片堆叠体310的上表面暴露的导电柱311电连接。所述盖板晶圆300可通过所述导电柱321向所述半导体裸片堆叠体310提供热传导，并进一步固定所述半导体裸片堆叠体310的位置。另外，在半导体封装中，还可以在所述盖板晶圆300上堆叠其他晶圆，所述导电柱321可起到电连接的作用。
本发明半导体封装结构在衬底晶圆上形成凹槽来容纳半导体裸片堆叠体，并通过绝缘介质层进行密封，大大降低半导体封装结构的高度，实现超薄封装。另外，所述绝缘介质层填充在所述凹槽的侧壁与所述半导体裸片堆叠体之间的间隙内，所述绝缘介质层能够固定所述半导体裸片堆叠体，避免其在移动或者振动时半导体裸片之间及半导体裸片堆叠体与衬底之间发生错位，造成半导体裸片之间及半导体裸片堆叠体与衬底晶圆之间连接不良，，提高半导体裸片堆叠体的稳固性，提高半导体封装结构的可靠性。
本发明还提供一种封装体。图4是本发明封装体的一具体实施方式的结构示意图。请参阅图4，所述封装体为上述的半导体封装结构沿凹槽之间的切割道切割而成。所述封装体包括衬底400、至少一半导体裸片堆叠体410、绝缘介质层430及盖板420。
所述衬底400具有相对设置的第一表面400A及第二表面400B，在所述第一表面400A具有至少一凹槽401，在所述凹槽401底部具有多个导电柱402，所述导电柱402贯穿所述凹槽401底部至所述第二表面400B。
所述半导体裸片堆叠体410放置在所述凹槽401内，所述半导体裸片堆叠体410的上表面低于或者平齐于所述凹槽401的上边缘，所述半导体裸片堆叠体410的底部与所述导电柱402电连接。
所述绝缘介质层430充满所述凹槽401的侧壁与所述半导体裸片堆叠体410之间的间隙，且所述绝缘介质层430覆盖所述半导体裸片堆叠体410的上表面，以密封所述半导体裸片堆叠体410。
所述盖板420为可选结构，其覆盖在所述绝缘介质层430的上表面及所述衬底400的第一表面400A，以进一步密封半导体裸片堆叠体410。
本发明封装体的封装高度低，实现了超薄封装，且在封装体移动或者振动时半导体裸片之间及半导体裸片堆叠体与衬底之间不会发生错位，不会造成半导体裸片之间及半导体裸片堆叠体与衬底晶圆之间连接不良，提高半导体裸片堆叠体的稳固性，提高封装体的可靠性。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (22)

1.一种半导体封装方法，其特征在于，包括如下步骤：
提供衬底晶圆，所述衬底晶圆具有相对设置的第一表面及第二表面，在所述第一表面具有多个凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；
提供多个半导体裸片堆叠体；
将所述半导体裸片堆叠体置于所述凹槽中，所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；
在所述凹槽的侧壁与所述半导体裸片堆叠体之间的间隙内充满绝缘介质，形成绝缘介质层，且所述绝缘介质层覆盖所述半导体裸片堆叠体的上表面，以密封所述半导体裸片堆叠体，形成半导体封装结构。
2.根据权利要求1所述的半导体封装方法，其特征在于，在所述衬底晶圆的第二表面具有多个导电块，所述导电块与所述导电柱电连接。
3.根据权利要求1所述的半导体封装方法，其特征在于，在所述衬底晶圆上形成凹槽的方法包括如下步骤：
对所述衬底晶圆的第一表面进行平坦化处理；
自所述第一表面去除部分所述衬底晶圆，至暴露出所述导电柱，形成所述凹槽。
4.根据权利要求3所述的半导体封装方法，其特征在于，所述衬底晶圆具有切割道，以所述切割道作为形成所述凹槽的对准标记。
5.根据权利要求1所述的半导体封装方法，其特征在于，所述半导体裸片堆叠体由多个半导体裸片堆叠形成，所述半导体裸片之间电连接，并通过所述半导体裸片堆叠体的底部与所述导电柱电连接。
6.根据权利要求5所述的半导体封装方法，其特征在于，所述半导体裸片之间通过贯穿各所述半导体裸片的导电柱及相邻所述半导体裸片间的导电块电连接。
7.根据权利要求1所述的半导体封装方法，其特征在于，所述半导体裸片堆叠体的底部与贯穿所述凹槽底部的导电柱之间通过导电块电连接。
8.根据权利要求1所述的半导体封装方法，其特征在于，所述衬底晶圆的热膨胀系数大于或者等于所述绝缘介质层的热膨胀系数。
9.根据权利要求8所述的半导体封装方法，其特征在于，所述衬底晶圆为硅晶圆，所述绝缘介质层为二氧化硅绝缘介质层。
10.根据权利要求1所述的半导体封装方法，其特征在于，所述半导体封装方法还包括如下步骤：在所述绝缘介质层的上表面及所述衬底晶圆的第一表面覆盖盖板晶圆。
11.根据权利要求10所述的半导体封装方法，其特征在于，所述盖板晶圆朝向所述衬底晶圆的表面具有多个导电柱，所述导电柱通过所述绝缘介质层中的导电结构与所述半导体裸片堆叠体的上表面电连接。
12.根据权利要求1所述的半导体封装方法，其特征在于，在密封所述半导体裸片堆叠体的步骤后，还包括切割步骤：沿凹槽之间的间隙切割所述半导体封装结构，形成多个彼此独立的封装体。
13.一种半导体封装结构，其特征在于，包括：
衬底晶圆，所述衬底晶圆具有相对设置的第一表面及第二表面，在所述第一表面具有多个凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；
多个半导体裸片堆叠体，放置在所述凹槽内，且所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；
绝缘介质层，充满所述凹槽的侧壁与所述半导体裸片堆叠体之间的间隙，且所述绝缘介质层覆盖所述半导体裸片堆叠体的上表面，以密封所述半导体裸片堆叠体。
14.根据权利要求13所述的半导体封装结构，其特征在于，在所述衬底晶圆的第二表面具有多个导电块，所述导电块与所述导电柱电连接。
15.根据权利要求13所述的半导体封装结构，其特征在于，所述半导体裸片堆叠体由多个半导体裸片堆叠形成，所述半导体裸片之间电连接，并通过所述半导体裸片堆叠体的底部与所述导电柱电连接。
16.根据权利要求15所述的半导体封装结构，其特征在于，所述半导体裸片之间通过贯穿各所述半导体裸片的导电柱及相邻所述半导体裸片间的导电块电连接。
17.根据权利要求13所述的半导体封装结构，其特征在于，所述半导体裸片堆叠体的底部与贯穿所述凹槽底部的导电柱之间通过导电块电连接。
18.根据权利要求13所述的半导体封装结构，其特征在于，所述衬底晶圆的热膨胀系数大于或者等于所述绝缘介质层的热膨胀系数。
19.根据权利要求13所述的半导体封装结构，其特征在于，所述衬底晶圆为硅晶圆，所述绝缘介质层为二氧化硅绝缘介质层。
20.根据权利要求13所述的半导体封装结构，其特征在于，在所述绝缘介质层的上表面及所述衬底晶圆的第一表面覆盖盖板晶圆。
21.根据权利要求20所述的半导体封装结构，其特征在于，所述盖板晶圆朝向所述衬底晶圆的表面具有多个导电柱，所述绝缘介质层中设置有导电结构，所述导电柱通过所述导电结构与所述半导体裸片堆叠体的上表面电连接。
22.一种封装体，其特征在于，包括：
衬底，所述衬底具有相对设置的第一表面及第二表面，在所述第一表面具有至少一凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；
至少一半导体裸片堆叠体，放置在所述凹槽内，所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；
绝缘介质层，充满所述凹槽的侧壁与所述半导体裸片堆叠体之间的间隙，且所述绝缘介质层覆盖所述半导体裸片堆叠体的上表面，以密封所述半导体裸片堆叠体。
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