CN102468279B - 集成电路装置及其制造方法 - Google Patents

集成电路装置及其制造方法 Download PDF

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CN102468279B
CN102468279B CN201110004086.1A CN201110004086A CN102468279B CN 102468279 B CN102468279 B CN 102468279B CN 201110004086 A CN201110004086 A CN 201110004086A CN 102468279 B CN102468279 B CN 102468279B
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wafer
integrated circuit
stacking
active element
isolation structure
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CN102468279A (zh
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黄财煜
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Nanya Technology Corp
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Abstract

本发明揭示一种集成电路装置及其制造方法，该集成电路装置包含一下晶圆、设置于该下晶圆上的至少一堆叠晶圆、以及至少一导电插塞，其贯穿该堆叠晶圆且深入该下晶圆，其中该下晶圆及该堆叠晶圆以一中间黏着层予以接合，且在该下晶圆及该堆叠晶圆之间没有焊垫。该集成电路装置的制造方法，包含形成一下晶圆、形成至少一堆叠晶圆、使用一中间黏着层接合该至少一堆叠晶圆至该下晶圆上、以及形成至少一导电插塞，其贯穿该堆叠晶圆且深入该下晶圆，其中没有在该下晶圆及该堆叠晶圆之间形成焊垫。本发明揭示的集成电路装置的制造方法无需在下晶圆及堆叠晶圆之间形成焊垫，解决传统技术的焊垫制造相当复杂且昂贵问题。

Description

集成电路装置及其制造方法
技术领域
本发明涉及一种集成电路装置及其制造方法，特别涉及一种集成电路装置及其制造方法，其在形成穿硅导电插塞(through-silicon via，TSV)之前接合(bonding)晶圆。
背景技术
集成电路装置的封装技术一直朝轻薄化与更具安装可靠性的方向研发。近年来，随着电子产品轻薄化与多功能性的要求，许多技术已经逐渐为此领域的人所熟知。
以内存装置为例，经由使用至少两芯片(chip)的堆叠方式，可通过半导体整合工艺，使生产具有比传统内存容量大两倍的内存变得可能。此外，堆叠封装不只提供增加内存容量的优势，亦增加安装密度及增加安装区域使用效率的优势。因此，关于堆叠封装技术的研究与开发已在逐渐加速。
以堆叠封装为例，TSV已经在此领域中被揭露。利用TSV技术的堆叠封装具有一TSV设置于芯片的结构，使得芯片可通过TSV与其它芯片以物理方式及电性方式彼此连接。一般而言，TSV的制造方法经由蚀刻技术而形成一贯穿基板的通孔，再以导电材料(例如铜)填满通孔。为了增加传输速度及制造高密度元件，具有数个集成电路装置(各具有TSV)的半导体晶圆的厚度必须予以减少。
US 7,683,459揭示一种混合式接合方法，用于具有TSV的晶圆堆叠，其中图案化的黏着层黏合堆叠中的相邻二片晶圆，而焊料则用以电气连接上晶圆的TSV底端至下晶圆的TSV顶端的焊垫。然而，在下晶圆的TSV顶端形成焊垫(bump pad)需要种晶工艺、电镀工艺、微影工艺以及蚀刻工艺，因此焊垫的制造相当复杂且昂贵。
发明内容
为了解决上述背景技术的问题，本发明提供一种集成电路装置及其制造方法，其在形成穿硅导电插塞之前接合晶圆，无需在下晶圆及堆叠晶圆之间形成焊垫，如此即可解决背景技术的焊垫制造相当复杂且昂贵问题。
本发明的一实施例揭示一种集成电路装置，包含一下晶圆、设置于该下晶圆上的至少一堆叠晶圆、以及至少一导电插塞，其贯穿该堆叠晶圆且深入该下晶圆，其中该下晶圆及该堆叠晶圆以一中间黏着层予以接合，且在该下晶圆及该堆叠晶圆之间没有焊垫。
在本发明的一实施例中，该集成电路装置的制造方法，包含形成一下晶圆、形成至少一堆叠晶圆、使用一中间黏着层接合该至少一堆叠晶圆至该下晶圆上、以及形成至少一导电插塞，其贯穿该堆叠晶圆且深入该下晶圆，其中没有在该下晶圆及该堆叠晶圆之间形成焊垫。
相较于US 7,683,459在每个晶圆上形成焊垫，本发明的实施例揭示的集成电路装置及其制造方法是先接合堆叠晶圆及下晶圆，再形成贯穿该堆叠晶圆且深入该下晶圆的导电插塞。如此本发明的实施例揭示的集成电路装置的制造方法无需在下晶圆及堆叠晶圆之间形成焊垫，解决背景技术的焊垫制造相当复杂且昂贵问题。
上文已相当广泛地概述本发明的技术特征及优点，以使下文的本发明详细描述得以获得较佳了解。构成本发明的权利要求标的的其它技术特征及优点将描述于下文。本发明所属技术领域中普通技术人员应了解，可相当容易地利用下文揭示的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本发明相同的目的。本发明所属技术领域中普通技术人员亦应了解，这类等效建构无法脱离所附的权利要求范围所界定的本发明的精神和范围。
附图说明
通过参照前述说明及下列图式，本发明的技术特征及优点得以获得完全了解。
图1至图12是剖示图，例示本发明一实施例的集成电路装置的制造方法。
其中，附图标记说明如下：
10A    下晶圆
10B   堆叠晶圆
11    晶圆
13    有源元件
15    介电层
17    浅沟槽隔离结构
19    凹部
21    介电区块
23    凹槽
25    接触洞
27    接触插塞
29    内连线
30    连接结构
31    导电层
33    介电层
35    保护层
37    黏着层
39    载具
41    中间黏着层
43    通孔
45    种晶层
47    导电插塞
49    焊垫
100   集成电路结构
具体实施方式
图1至图12是剖示图，例示本发明一实施例的集成电路装置100的制造方法。参考图1，首先进行工艺以在一硅晶圆11之中形成一有源元件13(例如晶体管)、邻近该有源元件13的浅沟槽隔离结构(STI；shallow trenchisolation)17、以及覆盖该有源元件13的一介电层15。之后，进行一蚀刻工艺以形成一凹部19于该浅沟槽隔离结构17之中，如图2所示。在本发明的一实施例中，该凹部19贯穿该浅沟槽隔离结构17。
参考图3，经由沉积工艺在该凹部19中填入介电材料以形成一介电区块21，再进行微影及蚀刻工艺以局部移除该介电区块21及该介电层15，以便形成至少一凹槽23。参考图4，进行微影及蚀刻工艺以局部移除该介电层15，以便形成至少一接触洞25，其曝露该有源元件13的至少一端点。
参考图5，经由沉积工艺在该接触洞25及该凹槽23之中填入相同的导电材料(例如钨)，以形成一接触插塞27于该接触洞25之中及一内连线29于该凹槽23之中。之后，进行一沉积工艺以形成一导电层31，其经由该接触插塞27电气连接该有源元件13及该内连线29，如图6所示。在本发明的一实施例中，该导电层31及该内连线29形成一连接结构30。
参考图7，经由沉积工艺形成一介电层33以覆盖该导电层31，再经由沉积工艺形成一保护层35以覆盖该介电层33而形成一下晶圆10A。之后，重复图1至图6所示的工艺于另一晶圆11上，并将一载具39通过一黏着层37黏着于该晶圆11的上端，再进行一薄化工艺(例如晶背研磨工艺或化学机械研磨工艺)以从该晶圆11的背面局部去除该晶圆11而形成一堆叠晶圆10B，如图8所示。
参考图9，通过一中间黏着层41将该堆叠晶圆10B接合于该下晶圆10A，其中在该下晶圆10A与该堆叠晶圆10B之间没有形成焊垫。在本发明的一实施例中，该中间黏着层41是该下晶圆10A与该堆叠晶圆10B之间的唯一膜层，亦即该堆叠晶圆10B在没有使用焊料情形下接合于该下晶圆10A。之后，将该载具39及该黏着层37从该堆叠晶圆10B的上端移除，再使用含氟蚀刻气体进行一干蚀刻工艺以形成至少一通孔(via hole)43，其以实质上直线方式贯穿该堆叠晶圆10B并深入该下晶圆10A，如图10所示。在本发明的一实施例中，该通孔43并未贯穿该下晶圆10A。
参考图11，经由物理气相沉积技术在该通孔43内形成阻障层及种晶层45，并进一电镀工艺以在该通孔43内填入导电材料(例如铜)而形成一导电插塞47。在本发明的一实施例中，该导电插塞47贯穿该堆叠晶圆10B的介电区块21，并深入该下晶圆10A的介电区块21。特别地，该导电插塞47并未贯穿该下晶圆10A的介电区块21。
参考图12，在该堆叠晶圆10B之上形成一焊垫49而完成该集成电路结构100。在本发明的一实施例中，该导电插塞47设置于该浅沟槽隔离结构17之中且连接于该焊垫49。在本发明的一实施例中，该导电插塞47电气连接于该连接结构30的内连线29，而该连接结构30的导电层31则电气连接该有源元件13至该内连线29，如此该有源元件13即电气连接于该导电插塞47。
相较于US 7,683,459在每个晶圆上形成焊垫，本发明的实施例揭示的集成电路装置100的制造方法是先接合堆叠晶圆10B及下晶圆10A，再形成贯穿堆叠晶圆10B且深入下晶圆10A的导电插塞47。如此，本发明的实施例揭示的集成电路装置的制造方法无需在下晶圆10A及堆叠晶圆10B之间形成焊垫，解决传统技术的焊垫制造相当复杂且昂贵问题。
本发明的技术内容及技术特点已揭示如上，然而本发明所属技术领域中的普通技术人员应了解，在不背离所附权利要求所界定的本发明精神和范围内，本发明的教示及揭示可作种种的替换及修饰。例如，上文揭示的许多工艺可以不同的方法实施或以其它工艺予以取代，或者采用上述二种方式的组合。
此外，本发明的权利要求范围并不局限于上文揭示的特定实施例的工艺、机台、制造、物质的成份、装置、方法或步骤。本发明所属技术领域中的普通技术人员应了解，基于本发明教示及揭示工艺、机台、制造、物质的成份、装置、方法或步骤，无论现在已存在或日后开发者，其与本发明实施例揭示的内容以实质相同的方式执行实质相同的功能，而达到实质相同的结果，亦可使用于本发明。因此，以下的权利要求用以涵盖用以此类工艺、机台、制造、物质的成份、装置、方法或步骤。

Claims (20)

1.一种集成电路装置，包含：
一下晶圆；包括：
一第一有源元件；
一第一浅沟槽隔离结构，邻近该第一有源元件设置；
第一介电区块，贯穿该第一浅沟槽隔离结构；
第一介电层，覆盖该第一有源元件、该第一浅沟槽隔离结构和该第一介电区块；
第一连接结构，设置于该第一介电区块和该第一浅沟槽隔离结构上；以及
至少一堆叠晶圆，设置于该下晶圆上，并包括：
一第二有源元件；
一第二浅沟槽隔离结构，邻近该第二有源元件设置；
一第二介电区块，贯穿该第二浅沟槽隔离结构；
一第二介电层，覆盖该第二有源元件、该第二浅沟槽隔离结构和该第二介电区块；
第二连接结构，设置于该第二介电区块和该第二浅沟槽隔离结构上；
其中该下晶圆及该堆叠晶圆以一中间黏着层予以接合，且在该下晶圆及该堆叠晶圆之间没有焊垫；以及
至少一导电插塞，以直线方式贯穿该堆叠晶圆且深入该下晶圆。
2.根据权利要求1所述的集成电路装置，其特征在于，该导电插塞贯穿该第二介电区块。
3.根据权利要求1所述的集成电路装置，其特征在于，该导电插塞没有贯穿该下晶圆。
4.根据权利要求1所述的集成电路装置，其特征在于，且该导电插塞没有贯穿该第一介电区块。
5.根据权利要求1所述的集成电路装置，其特征在于，该至少一堆叠晶圆包含一上晶圆，该上晶圆包含至少一焊垫，且该导电插塞连接于该焊垫。
6.根据权利要求1所述的集成电路装置，其特征在于，该第二连接结构电气连接该导电插塞及该第二有源元件。
7.根据权利要求6所述的集成电路装置，其特征在于，该第二连接结构包含：
至少一内连线；以及
一导电层，电气连接该有源元件及该内连线。
8.根据权利要求7所述的集成电路装置，其特征在于，该堆叠晶圆包含一接触插塞，且该内连线及该接触插塞由相同导电材料构成。
9.根据权利要求6所述的集成电路装置，其特征在于，该导电插塞设于该第二浅沟槽隔离结构之中。
10.根据权利要求1所述的集成电路装置，其特征在于，该下晶圆及该堆叠晶圆之间没有焊料。
11.一种集成电路装置的制造方法，包含下列步骤：
形成一下晶圆；
形成至少一堆叠晶圆；
使用一中间黏着层接合该至少一堆叠晶圆至该下晶圆上，其中没有在该下晶圆及该堆叠晶圆之间形成焊垫，其中该至少一堆叠晶圆包括至少一个第二有源元件、一第二介电区块和一第二浅沟槽隔离结构，该第二介电区块和该第二浅沟槽隔离结构邻近该第二有源元件，该第二介电区块贯穿该第二浅沟槽隔离结构，该下晶圆包括第一有源元件、一第一介电区块和一第一浅沟槽隔离结构，该第一介电区块贯穿该第一浅沟槽隔离结构；以及
形成至少一导电插塞，以直线方式贯穿该堆叠晶圆且深入该下晶圆。
12.根据权利要求11所述的集成电路装置的制造方法，其特征在于，形成所述至少一堆叠晶圆的步骤包含：
形成一第二介电区块，且所述至少一导电插塞贯穿该第二介电区块。
13.根据权利要求11所述的集成电路装置的制造方法，其特征在于，形成至少一导电插塞的步骤没有贯穿该下晶圆。
14.根据权利要求11所述的集成电路装置的制造方法，其特征在于，形成一下晶圆的步骤包含：
形成该第一介电区块，且该导电插塞没有贯穿该第一介电区块。
15.根据权利要求11所述的集成电路装置的制造方法，其特征在于，还包含：
形成至少一焊垫于该堆叠晶圆上，其中该导电插塞连接于该焊垫。
16.根据权利要求11所述的集成电路装置的制造方法，其特征在于，形成至少一堆叠晶圆的步骤包含：
形成该至少一第二有源元件；以及
形成该第二连接结构，电气连接该导电插塞及该第二有源元件。
17.根据权利要求16所述的集成电路装置的制造方法，其特征在于，形成一第二连接结构的步骤包含：
形成至少一内连线；以及
形成一导电层，电气连接该第二有源元件及该内连线。
18.根据权利要求17所述的集成电路装置的制造方法，其特征在于，形成至少一堆叠晶圆的步骤包含：
形成一接触插塞，该接触插塞连接于该第二有源元件，且该内连线及该接触插塞是由相同导电材料构成。
19.根据权利要求16所述的集成电路装置的制造方法，其特征在于，形成至少一堆叠晶圆的步骤包含：
形成一第二浅沟槽隔离结构，邻近该第二有源元件，且该导电插塞设于该第二浅沟槽隔离结构之中。
20.根据权利要求11所述的集成电路装置的制造方法，其特征在于，使用一中间黏着层接合该至少一堆叠晶圆至该下晶圆上的步骤没有使用焊料。
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