CN103426856A - 晶片封装体及其形成方法 - Google Patents

晶片封装体及其形成方法 Download PDF

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Publication number
CN103426856A
CN103426856A CN2013101849410A CN201310184941A CN103426856A CN 103426856 A CN103426856 A CN 103426856A CN 2013101849410 A CN2013101849410 A CN 2013101849410A CN 201310184941 A CN201310184941 A CN 201310184941A CN 103426856 A CN103426856 A CN 103426856A
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China
Prior art keywords
semiconductor layer
substrate
layer
encapsulation body
lower semiconductor
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CN2013101849410A
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CN103426856B (zh
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张恕铭
黄郁庭
刘沧宇
何彦仕
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种晶片封装体及其形成方法，该晶片封装体包括：一第一基底；一第二基底，设置于该第一基底之上，其中该第二基底包括一下半导体层、一上半导体层、及该下半导体层与该上半导体层之间的一绝缘层，且该下半导体层的一部分电性接触该第一基底上的至少一接垫；一导电层，设置于该第二基底的该上半导体层之上，且电性连接该下半导体层的与该至少一接垫电性接触的该部分；一开口，自该上半导体层朝该下半导体层延伸并延伸进入该下半导体层；以及一保护层，设置于该上半导体层及该导电层之上，其中该保护层延伸至该开口的部分侧壁上，且不覆盖该开口中的该下半导体层。

Description

晶片封装体及其形成方法
技术领域
本发明有关于晶片封装体，且特别是有关于多晶片封装体。
背景技术
随着电子产品朝向轻、薄、短、小发展的趋势，半导体晶片的封装结构也朝向多晶片封装(multi-chip package,MCP)结构发展，以达到多功能和高性能要求。多晶片封装结构是将不同类型的半导体晶片，例如逻辑晶片、模拟晶片、控制晶片、存储器晶片、微机电系统晶片，整合在单一封装基底之上。
业界亟需改进的多晶片封装技术。
发明内容
本发明一实施例提供一种晶片封装体，包括：一第一基底；一第二基底，设置于该第一基底之上，其中该第二基底包括一下半导体层、一上半导体层、及该下半导体层与该上半导体层之间的一绝缘层，且该下半导体层的一部分电性接触该第一基底上的至少一接垫；一导电层，设置于该第二基底的该上半导体层之上，且电性连接该下半导体层的与该至少一接垫电性接触的该部分；一开口，自该上半导体层朝该下半导体层延伸并延伸进入该下半导体层；以及一保护层，设置于该上半导体层及该导电层之上，其中该保护层延伸至该开口的部分侧壁上，且不覆盖该开口中的该下半导体层。
本发明一实施例提供一种晶片封装体的形成方法，包括：提供一第一基底；提供一第二基底，包括一下半导体层、一上半导体层、及该下半导体层与该上半导体层之间的一绝缘层；将该第二基底接合于该第一基底之上且使该下半导体层的一部分电性接触该第一基底上的至少一接垫；移除部分的该上半导体层及该绝缘层以形成露出该下半导体层的一上表面的一开口；于该第二基底的该上半导体层之上形成一导电层，其中该导电层电性连接该下半导体层的与该至少一接垫电性接触的该部分；于该上半导体层及该导电层上形成一保护层，其中该保护层延伸至该开口的侧壁上，且该开口中的该下半导体层的该上表面未被该保护层覆盖；以及以该保护层为遮罩，自该开口中的该下半导体层的该上表面移除部分的该下半导体层而使该开口延伸进入该下半导体层。
附图说明
图1A-图1K显示根据本发明一实施例的晶片封装体的制程剖面图。
图2显示根据本发明一实施例的晶片封装体的剖面图。
附图中符号的简单说明如下：
10、20：基底
100：上半导体层
100a、100b：表面
102：绝缘层
104：下半导体层
106a：孔洞
106b、106c：开口
108：导电层
109：保护层
110：承载基底
112、112’：粘着层
200：半导体基底
200a、200b：表面
202：介电层
204：接垫
206：孔洞
208：绝缘层
210a：晶种层
210b：导电层
212：保护层
214：导电结构。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以以多种特定形式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。本领域技术人员自本申请的权利要求中所能推及的所有实施方式皆属本申请所欲揭露的内容。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关联性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装各种晶片及/或多晶片的堆叠。例如，其可用于封装各种包含有源元件或无源元件(active or passiveelements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronic devices)、微机电系统(Micro Electro Mechanical System;MEMS)、微流体系统(microfluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package;WSP)制程对影像感测元件、发光二极管(light-emitting diodes;LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力感测器(process sensors)喷墨头(ink printer heads)、或功率金属氧化物半导体场效晶体管模组(power MOSFET modules)等半导体晶片进行封装。
上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。在一实施中，上述切割后的封装体为一晶片尺寸封装体(CSP;chipscale package)。晶片尺寸封装体(CSP)的尺寸可仅略大于所封装的晶片。例如，晶片尺寸封装体的尺寸不大于所封装晶片的尺寸的120%。
图1A-图1K显示根据本发明一实施例的晶片封装体的制程剖面图。如图1A所示，提供基底10及20。在一实施例中，基底10及20可皆为半导体晶圆，其例如分别为(但不限于)包含微机电系统的晶圆及包含互补式金属氧化物半导体场效晶体管的晶圆。
在一实施例中，基底10包括下半导体层104、上半导体层100及位于下半导体层104与上半导体层100之间的绝缘层102。上半导体层100可具有表面100a及表面100b，且可以以表面100b下的绝缘层102而与下半导体层104电性绝缘。在一实施例中，下半导体层104中可定义有多个间隙，其可将下半导体层104划分为多个彼此大抵分离的部分。
在一实施例中，基底20(例如为半导体晶圆)包括半导体基底200、设置于半导体基底200的表面200a上的接垫204及介电层202。接垫204可包含信号接垫或接地接垫。
在一实施例中，可将基底10接合于基底20之上，使得部分的下半导体层104接合并电性接触至少一接垫204。在一实施例中，部分的下半导体层104所接触的接垫204可为(但不限于)接地接垫。在一实施例中，下半导体层104与接垫204之间的接合可为半导体-金属接合，例如(但不限于)锗铝接合。
接着，如图1B所示，可选择性薄化上半导体层100。适合的薄化制程例如包括机械研磨制程、化学机械研磨制程、蚀刻制程或前述的组合。
接着，可于上半导体层100的表面100a上形成与部分的下半导体层104及接垫204(例如是接地接垫)电性连接的导电层。导电层可通过穿孔及/或经由基底的侧边而与接垫204(例如是接地接垫)电性连接。然而，为简化说明，以下仅以通过穿孔而与接垫204(例如是接地接垫)电性连接的实施方式为例。
如图1C所示，可自上半导体层100的表面100a移除部分的上半导体层100及绝缘层102以形成朝下半导体层104延伸的孔洞106a。在一实施例中，孔洞106a可对齐于接垫204(例如是接地接垫)及与接垫204连接的部分的下半导体层104。在另一实施例中，孔洞106a可对齐于接垫204，但所对齐的接垫204不与下半导体层104接触。在又一实施例中，孔洞106a不与接垫204对齐。
在一实施例中，可自上半导体层100的表面100a移除部分的上半导体层100及绝缘层102以形成朝下半导体层104延伸的开口106b。开口106b可露出下半导体层104的上表面。在一实施例中，开口106b与孔洞106a可于同一个图案化制程中同时形成。在一实施例中，开口106b的形状与分布不同于孔洞106a。
接着，如图1D所示，可于上半导体层100的表面100a上形成导电层108。在一实施例中，导电层108可延伸进入孔洞106a而电性接触孔洞106a所露出的下半导体层104。下半导体层104的由孔洞106a所露出的部分可电性连接半导体基底200上的接垫204(其例如为接地接垫)。因此，导电层108可与接垫204电性连接而可作为接地用途。在一实施例中，导电层108可经图案化而不延伸进入开口106b中。在一实施例中，导电层108的最靠近开口106b的侧边与开口106b隔有一距离。在一实施例中，导电层108可直接接触上半导体层100。在一实施例中，孔洞106a可位于预定切割道(未显示)之中。
此外，导电层108除了可用作接地外，在其他实施例中，导电层108可作为电磁干扰防护(EMI shielding)层、导热层或反射层。
接着，如图1E所示，可于上半导体层100及导电层108上形成图案化保护层109。保护层109可包括氧化物、氮化物、氮氧化物或前述的组合。在一实施例中，可采用化学气相沉积法、涂布法、喷涂法或其他适合制程沉积保护层109。接着，可使用微影及蚀刻制程将保护层109图案化。在一实施例中，开口106b中的部分的下半导体层104未被保护层109覆盖而露出。在一实施例中，保护层109可直接接触导电层108、上半导体层100及绝缘层102。
接着，如图1F所示，可以以保护层109为遮罩，自开口106b中的下半导体层104的上表面移除部分的下半导体层104而使开口106b延伸进入下半导体层104之中而成为开口106c。保护层109可延伸于开口106c的部分侧壁上，其可例如直接接触开口106c侧壁上的上半导体层100及绝缘层102。开口106c中的下半导体层104可不由保护层109所覆盖。在一实施例中，开口106c底部处的下半导体层104可例如作为感测区，例如(但不限于)压力感测区或声音感测区。
如图1G所示，接着可选择性于上半导体层100上设置承载基底110。例如，可采用粘着层112而将承载基底110接合于上半导体层100上的保护层109之上。在一实施例中，粘着层112可为暂时性粘着层，其粘性可在后续的照光、加热或清洗之后而大抵消除。
接着，如图1H所示，可选择性薄化半导体基底200。例如，可以以承载基底110为支撑，自半导体基底200的表面200b薄化半导体基底200。
如图1H所示，可接着自表面200b移除部分的半导体基底200以形成朝接垫204(其例如是信号接垫)延伸的孔洞206。
接着，如图1H所示，可于半导体基底200的表面200b上形成绝缘层208。绝缘层208可延伸于孔洞206的侧壁与底部上。在一实施例中，可进一步通过图案化制程移除孔洞206底部上的部分的绝缘层208而使接垫204(例如，信号接垫)露出。
如图1I所示，可接着于绝缘层208上形成电信连接接垫204(例如，信号接垫)的导电层。例如，可先形成晶种层210a，并接着通过电镀制程形成导电层210b。
接着，如图1J所示，可于导电层210b及绝缘层208上形成保护层212，其具有露出部分的导电层210b的至少一开口。接着，可于开口中形成信号导电结构214，其例如为导电凸块或焊球。
如图1K所示，可接着移除粘着层112及其上的承载基底110。在一实施例中，可例如通过照光、加热及/或使用溶剂的方式移除粘着层112及承载基底110。在所接合的两基底为半导体晶圆的实施例中，可接着沿着预定切割道(未显示)进行切割制程以将两基底切割为多个彼此分离的晶片封装体。如图1K所示，在一实施例中，开口106c可露出薄化的部分下半导体层104，其可例如用作感测区。
图2显示根据本发明一实施例的晶片封装体的剖面图，其中相同或相似的标号用以标示相同或相似的元件。图2的实施例大抵相同于图1A-图1K所示的实施例。主要区别在于所使用的粘着层112’可为(但不限于)永久性的粘着胶。因此，在图2实施例中的晶片封装体中仍具有承载基底110。
在本发明实施例中，晶片封装体的信号导电结构214可设于晶片封装体的下表面，而(接地)接垫204可通过下半导体层104而与设置在晶片封装体的上侧的导电层108电性连接。因此，晶片封装体的下表面上的导电凸块的分布密度可获舒缓。此外，本发明实施例的开口可露出下半导体层104，以作为感测用途，其例如可感应压力变化及声音变化。所感应的压力或声音变化可转为电子信号而传至基底20中处理，并可通过信号导电结构214导出晶片封装体以供利用。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
一第一基底；
一第二基底，设置于该第一基底之上，其中该第二基底包括一下半导体层、一上半导体层、及该下半导体层与该上半导体层之间的一绝缘层，且该下半导体层的一部分电性接触该第一基底上的至少一接垫；
一导电层，设置于该第二基底的该上半导体层之上，且电性连接该下半导体层的与该至少一接垫电性接触的该部分；
一开口，自该上半导体层朝该下半导体层延伸并延伸进入该下半导体层；以及
一保护层，设置于该上半导体层及该导电层之上，其中该保护层延伸至该开口的部分侧壁上，且不覆盖该开口中的该下半导体层。
2.根据权利要求1所述的晶片封装体，其特征在于，还包括一信号导电结构，该信号导电结构设置于该第一基底的一下表面之上，且电性连接该第一基底上的一信号接垫。
3.根据权利要求2所述的晶片封装体，其特征在于，还包括一第二导电层，该第二导电层电性连接该信号导电结构及该信号接垫。
4.根据权利要求3所述的晶片封装体，其特征在于，还包括一孔洞，该孔洞自该第一基底的该下表面朝该信号接垫延伸，其中该第二导电层延伸进入该孔洞而电性接触该信号接垫，且该第二导电层与该第一基底之间隔有一第二绝缘层。
5.根据权利要求1所述的晶片封装体，其特征在于，该导电层的最靠近该开口的一侧边与该开口隔有一距离。
6.根据权利要求1所述的晶片封装体，其特征在于，还包括一第二孔洞，该第二孔洞自该第二基底的该上半导体层的一上表面朝该第二基底的该下半导体层延伸，其中该导电层延伸进入该第二孔洞而电性接触该下半导体层的该部分。
7.根据权利要求6所述的晶片封装体，其特征在于，该第二孔洞对齐于该至少一接垫。
8.根据权利要求1所述的晶片封装体，其特征在于，该导电层直接接触该第二基底。
9.根据权利要求1所述的晶片封装体，其特征在于，该保护层直接接触该导电层、该上半导体层及该绝缘层。
10.根据权利要求1所述的晶片封装体，其特征在于，还包括一承载基底，设置于该第二基底之上。
11.一种晶片封装体的形成方法，其特征在于，包括：
提供一第一基底；
提供一第二基底，包括一下半导体层、一上半导体层、及该下半导体层与该上半导体层之间的一绝缘层；
将该第二基底接合于该第一基底之上且使该下半导体层的一部分电性接触该第一基底上的至少一接垫；
移除部分的该上半导体层及该绝缘层以形成露出该下半导体层的一上表面的一开口；
于该第二基底的该上半导体层之上形成一导电层，其中该导电层电性连接该下半导体层的与该至少一接垫电性接触的该部分；
于该上半导体层及该导电层上形成一保护层，其中该保护层延伸至该开口的侧壁上，且该开口中的该下半导体层的该上表面未被该保护层覆盖；以及
以该保护层为遮罩，自该开口中的该下半导体层的该上表面移除部分的该下半导体层而使该开口延伸进入该下半导体层。
12.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括于该第一基底的一下表面上设置一信号导电结构，该信号导电结构电性连接该第一基底上的一信号接垫。
13.根据权利要求12所述的晶片封装体的形成方法，其特征在于，还包括：
自该第一基底的该下表面移除部分的该第一基底以形成露出该信号接垫的一孔洞；
于该第一基底的该下表面上及该第二孔洞的一侧壁上形成一第二绝缘层；
于该第一基底的该下表面上形成一第二导电层，该第二导电层延伸进入该孔洞而电性连接该信号接垫；以及
于该第一基底的该下表面上的该第二导电层上形成该信号导电结构。
14.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括于形成该导电层之前，移除部分的该上半导体层以形成朝该下半导体层延伸的一第二孔洞，接着形成该导电层以使该导电层延伸进入该第二孔洞而电性接触该下半导体层的该部分。
15.根据权利要求14所述的晶片封装体的形成方法，其特征在于，该开口与该第二孔洞同时形成。
16.根据权利要求14所述的晶片封装体的形成方法，其特征在于，该导电层完全覆盖该孔洞的一侧壁及一底部。
17.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括于该第二基底之上接合一承载基底。
18.根据权利要求17所述的晶片封装体的形成方法，其特征在于，还包括移除该承载基底。
19.根据权利要求11所述的晶片封装体的形成方法，其特征在于，该保护层直接接触该导电层、该上半导体层及该绝缘层。
20.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括对该第一基底及该第二基底进行一切割制程以形成彼此分离的多个晶片封装体。
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