CN103985683A - 晶片封装体 - Google Patents

晶片封装体 Download PDF

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Publication number
CN103985683A
CN103985683A CN201410042921.4A CN201410042921A CN103985683A CN 103985683 A CN103985683 A CN 103985683A CN 201410042921 A CN201410042921 A CN 201410042921A CN 103985683 A CN103985683 A CN 103985683A
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Prior art keywords
wafer
depression
wafer encapsulation
conductive structure
conductor layer
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CN201410042921.4A
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CN103985683B (zh
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何彦仕
刘沧宇
林佳升
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种晶片封装体，其包括：一半导体基底，具有一第一表面及一第二表面；一第一凹陷，自该第一表面朝该第二表面延伸；一第二凹陷，自该第一凹陷的一底部朝该第二表面延伸，其中该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面；一导线层，设置于该第一表面上，且延伸进入该第一凹陷及/或该第二凹陷；一绝缘层，位于该导线层与该半导体基底之间；一晶片，设置于该第一表面上；以及一导电结构，设置于该晶片与该第一表面之间。本发明不仅有助于晶片封装体的缩小化，还可提升导线层的可靠度。

Description

晶片封装体
技术领域
本发明有关于晶片封装体及其形成方法，且特别是有关于以晶圆级封装制程所形成的晶片封装体。
背景技术
晶片封装制程是形成电子产品过程中的一重要步骤。晶片封装体除了将晶片保护于其中，使免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
由于电子产品缩小化的需求仍持续，如何于有限空间中设置更多的导电线路成为重要课题。
发明内容
本发明一实施例提供一种晶片封装体，包括：一半导体基底，具有一第一表面及一第二表面；一第一凹陷，自该第一表面朝该第二表面延伸；一第二凹陷，自该第一凹陷的一底部朝该第二表面延伸，其中该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面；一导线层，设置于该第一表面上，且延伸进入该第一凹陷及/或该第二凹陷；一绝缘层，位于该导线层与该半导体基底之间；一晶片，设置于该第一表面上；以及一导电结构，设置于该晶片与该第一表面之间。
本发明一实施例提供一种晶片封装体，包括：一半导体基底，具有一第一表面及一第二表面；多个凹陷，自该第一表面朝该第二表面延伸，且彼此相连通，其中所述凹陷的侧壁与底部共同形成该半导体基底的一外侧表面；一导线层，设置于该第一表面上，且延伸进入至少其中一个所述凹陷；一绝缘层，位于该导线层与该半导体基底之间；一晶片，设置于该第一表面上；以及一导电结构，设置于该晶片与该第一表面之间。
本发明不仅有助于晶片封装体的缩小化，还可提升导线层的可靠度。
附图说明
图1显示根据本发明一实施例的晶片封装体的剖面图。
图2显示根据本发明一实施例的晶片封装体的剖面图。
图3显示根据本发明一实施例的晶片封装体的剖面图。
图4显示根据本发明一实施例的晶片封装体的剖面图。
附图中符号的简单说明如下：
100～半导体基底；100a、100b～表面；101～介电层；104、104a～导电垫；116～绝缘层；118～导线层；119～线路重布层；130a、130b～凹陷；162、162a～绝缘层；164、164a～穿基底导电结构；172～晶片；174、174a～导电结构；176～间隔层；178～承载基底；179～空腔；194、194a～导电垫；196～保护层；204～焊线。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定形式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间必然具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装各种晶片。例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active orpassive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronicdevices)、微机电系统(Micro Electro Mechanical System;MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package;WSP)制程对影像感测元件、发光二极管(light-emitting diodes;LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wavedevices)、压力感测器(process sensors)喷墨头(ink printer heads)、或功率金氧半场效电晶体模组(power MOSFET modules)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。在一实施中，上述切割后的封装体为一晶片尺寸封装体(CSP;chipscale package)。晶片尺寸封装体(CSP)的尺寸可仅略大于所封装的晶片。例如，晶片尺寸封装体的尺寸不大于所封装晶片的尺寸的120%。
图1显示根据本发明一实施例的晶片封装体的剖面图。晶片封装体可包括半导体基底100，其具有表面100a及表面100b。半导体基底100可包括(但不限于)硅基底、硅锗基底、或前述的组合。在一实施例中，半导体基底100可为一半导体晶片。例如，半导体基底100可为一影像感测晶片，具有影像感测区(未显示)形成于其中，其例如形成于半导体基底100之中，且接近表面100a。
半导体基底100的表面100a上可选择性形成有介电层101。介电层101中可形成有多个导电垫，例如导电垫104及导电垫104a。每一导电垫104或导电垫104a可包括多层导电层的堆叠。这些堆叠的导电层可通过彼此间的导电通路(未显示)而彼此电性连接。在一实施例中，导电垫104或导电垫104a可通过介电层101中及/或半导体基底100中的导电通路(未显示)而与半导体基底100中的元件区(例如，影像感测区)中的电子元件电性连接。介电层101可具有露出导电垫104及导电垫104a的开口。介电层101的材质可包括(但不限于)氧化硅、氮化硅、氮氧化硅、或前述的组合。
在一实施例中，半导体基底100可通过图案化制程及/或切割制程而具有多个凹陷。这些凹陷可自表面100a朝表面100b延伸，并彼此相连通。此外，这些凹陷的侧壁与底部可共同形成半导体基底100的外侧表面。即，半导体基底100的部分的外侧表面是由这些凹陷的侧壁与底部所共同形成。在图1的实施例中，以两个凹陷130b及130a为例做说明。然应注意的是，在其他实施例中，半导体基底100可具有三个或三个以上的相连通凹陷，且这些凹陷的底部及侧边可共同形成半导体基底100的外侧表面。
如图1所示，凹陷130b可自半导体基底100的表面100a朝表面100b延伸。凹陷130a可自凹陷130b的底部朝表面100b延伸。凹陷130b的侧壁及底部与凹陷130a的侧壁及底部可共同形成半导体基底100的外侧表面。
半导体基底100的表面100a上可形成有绝缘层116。绝缘层116可延伸进入凹陷130b及凹陷130a。在一实施例中，绝缘层116可顺应性形成于凹陷130b及凹陷130a的侧壁及底部上。绝缘层116的材质可包括(但不限于)氧化硅、氮化硅、氮氧化硅、高分子材料、其他适合的绝缘材料、或前述的组合。绝缘层116可具有露出导电垫104及104a的开口。
半导体基底100的表面100a上的绝缘层116上可形成有多个导电线，其包含导电线118。导电线118的材质可包括(但不限于)铜、铝、金、铂、镍、锡、银、或前述的组合。导线层118可延伸进入凹陷130b及/或凹陷130a。例如，在一实施例中，导线层118可延伸于凹陷130b的侧壁与底部上，且更进一步延伸于凹陷130a的侧壁与底部上，如图1所示。或者，导线层118可仅延伸进入凹陷130b。在一实施例中，导线层118可电性连接导电垫104a。在一实施例中，可选择性形成焊线204。焊线204可电性接触延伸进入凹陷130b及/或凹陷130a中的导线层118。在一实施例中，焊线204可直接接触这些凹陷中的最接近表面100b的最低凹陷(例如，凹陷130a)的底部正上方的导线层118。最低凹陷(例如，凹陷130a)的底部可大抵平行于表面100b。焊线204可用于使其他电子构件(例如，印刷电路板)的电性信号通过导线层118而传递至晶片封装体。
半导体基底100的表面100a上可设置有晶片172。设置于晶片172与半导体基底100的表面100a之间的导电结构(例如，导电结构174或导电结构174a)可用以于半导体基底100与晶片172之间传递电性信号。导电结构174及导电结构174a例如可为(但不限于)导电凸块、焊球、或其他相似结构。
在一实施例中，导线层118可电性连接导电结构174a。在此情形下，电性信号除了可通过导电结构174a而于晶片172与半导体基底100之间传递外，还可通过导线层118及形成于凹陷130a或凹陷130b中的焊线204而与其他电子构件彼此传递电性信号。此外，导电结构174还可直接电性接触露出的导电垫104而使电性信号于晶片172与半导体基底100之间传递。在一实施例中，晶片172可为信号处理器晶片，而半导体基底100可为包含影像感测区(未显示)的影像感测晶片。
在一实施例中，晶片封装体可选择性包括承载基底178。承载基底178可设置于半导体基底100的表面100b之上。承载基底178与半导体基底100之间还可选择性设置间隔层176。间隔层176、承载基底178及半导体基底100可共同围绕出大抵密闭的空腔179。在一实施例中，承载基底178可包括透明基底，例如是(但不限于)玻璃基底、石英基底、蓝宝石基底、透明高分子基底、或前述的组合。间隔层176的材质可包括(但不限于)高分子材料、金属材料、陶瓷材料、半导体材料、或前述的组合。
图2显示根据本发明一实施例的晶片封装体的剖面图，其中相同或相似的标号用以标示相同或相似的元件。在此实施例中，凹陷130b自半导体基底100的表面100b朝表面100a延伸，且凹陷130a自凹陷130b的底部朝表面100a延伸。在此实施例中，半导体基底100的表面100b上设置有导电垫194及导电垫194a。保护层196可覆盖半导体基底100的表面100b，且具有露出导电垫194及导电垫194a的开口。导电垫194可通过形成于半导体基底100中的穿基底导电结构164而电性连接半导体基底100的表面100a上的导电垫104。穿基底导电结构164与半导体基底100之间可形成有绝缘层162。穿基底导电结构164的材质可包括(但不限于)铜、铝、金、铂、锡、镍、或前述的组合。绝缘层162的材质可包括(但不限于)氧化硅、氮化硅、氮氧化硅、高分子材料、或前述的组合。
晶片172可通过设置于其下的导电结构174而传递电性信号至半导体基底100或接收来自半导体基底100的电性信号。此外，导电结构174a可电性连接导线层118，且导线层118可电性连接导电垫194a，并电性连接凹陷中的焊线层204。在此实施例中，导线层118不电性连接穿基底导电结构164。
图3显示根据本发明一实施例的晶片封装体的剖面图，其中相同或相似的标号用以标示相同或相似的元件。图3所示结构相似于图1所示结构，差异主要在于图3所示结构还包括线路重布层119。线路重布层119可形成于绝缘层116之上。线路重布层119的材质可包括(但不限于)铜、铝、金、铂、锡、镍、或前述的组合。在一实施例中，线路重布层119与导线层118可图案化自相同的导电层。因此，线路重布层119与导线层118可同时形成，并具有相同的材质。线路重布层119可用以电性连接晶片172下方的导电结构174。在一实施例中，线路重布层119可延伸进入半导体基底100的凹陷的中。例如，线路重布层119亦可延伸进入凹陷130a，并可与电性接触焊线204。或者，延伸进入凹陷130a的线路重布层119可不电性接触焊线204，但可选择性与其他导电结构或其他焊线电性连接。
图4显示根据本发明一实施例的晶片封装体的剖面图，其中相同或相似的标号用以标示相同或相似的元件。图4所示结构相似于图2所示结构，差异主要在于图4所示的结构还包括穿基底导电结构164a。穿基底导电结构164a电性连接导电垫104a及导电垫194a。此外，导线层118电性连接导电垫194a、导电结构174a及焊线204。
在本发明实施例中，通过堆叠晶片与将导线层导引至凹陷的中，可于有限空间之中，设置更多的导电线路，有助于晶片封装体的缩小化。由于导线线路的传递距离减小，信号传递速度可获提升。此外，由于焊线形成于凹陷的中，可受到凹陷的保护而使晶片封装体的可靠度提升。由于焊线形成于凹陷的中，可使晶片封装体的整体体积缩小。本发明实施例所形成的凹陷包括多个相连通的凹陷，可使导线层于更为缓和的轮廓上沉积，可提升导线层的可靠度。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
一半导体基底，具有一第一表面及一第二表面；
一第一凹陷，自该第一表面朝该第二表面延伸；
一第二凹陷，自该第一凹陷的一底部朝该第二表面延伸，其中该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面；
一导线层，设置于该第一表面上，且延伸进入该第一凹陷及/或该第二凹陷；
一绝缘层，位于该导线层与该半导体基底之间；
一晶片，设置于该第一表面上；以及
一导电结构，设置于该晶片与该第一表面之间。
2.根据权利要求1所述的晶片封装体，其特征在于，还包括：
一介电层，位于该第一表面与该绝缘层之间；以及
一第一导电垫，位于该介电层之中，其中该导线层电性连接该第一导电垫。
3.根据权利要求2所述的晶片封装体，其特征在于，该导线层电性连接该导电结构。
4.根据权利要求2所述的晶片封装体，其特征在于，还包括：
一第二导电垫，位于该介电层之中；以及
一第二导电结构，设置于该晶片与该第一表面之间，且电性连接该第二导电垫。
5.根据权利要求4所述的晶片封装体，其特征在于，该第二导电结构通过一线路重布层而电性连接该第二导电垫。
6.根据权利要求1所述的晶片封装体，其特征在于，该半导体基底为一半导体晶片。
7.根据权利要求6所述的晶片封装体，其特征在于，该半导体晶片为一影像感测晶片，而该晶片为一信号处理器晶片。
8.根据权利要求1所述的晶片封装体，其特征在于，该导线层延伸于该第二凹陷的该第二底部上。
9.根据权利要求1所述的晶片封装体，其特征在于，还包括一焊线，该焊线电性接触延伸进入该第一凹陷及/或该第二凹陷中的该导线层。
10.根据权利要求1所述的晶片封装体，其特征在于，还包括一承载基底，该承载基底设置于该第二表面上。
11.根据权利要求10所述的晶片封装体，其特征在于，还包括一间隔层，该间隔层设置于该承载基底与该半导体基底之间，其中该间隔层、该承载基底及该半导体基底共同围绕出大抵密封的一空腔。
12.根据权利要求10所述的晶片封装体，其特征在于，该承载基底为一透明基底。
13.根据权利要求1所述的晶片封装体，其特征在于，还包括：
一介电层，位于该第二表面上；
一导电垫，位于该介电层之中；
一穿基底导电结构，穿过该第一表面及该第二表面，且电性连接该导电垫及该导电结构；以及
一第二绝缘层，位于该穿基底导电结构与该半导体基底之间。
14.根据权利要求13所述的晶片封装体，其特征在于，该导线层电性连接该穿基底导电结构。
15.根据权利要求13所述的晶片封装体，其特征在于，该导线层不电性连接该穿基底导电结构。
16.根据权利要求13所述的晶片封装体，其特征在于，还包括：
一第二导电垫，位于该介电层之中；
一第二导电结构，设置于该晶片与该第一表面之间；
一第二穿基底导电结构，穿过该第一表面及该第二表面，且电性连接该第二导电垫及该第二导电结构；以及
一第三绝缘层，位于该第二穿基底导电结构与该半导体基底之间。
17.一种晶片封装体，其特征在于，包括：
一半导体基底，具有一第一表面及一第二表面；
多个凹陷，自该第一表面朝该第二表面延伸，且彼此相连通，其中所述凹陷的侧壁与底部共同形成该半导体基底的一外侧表面；
一导线层，设置于该第一表面上，且延伸进入至少其中一个所述凹陷；
一绝缘层，位于该导线层与该半导体基底之间；
一晶片，设置于该第一表面上；以及
一导电结构，设置于该晶片与该第一表面之间。
18.根据权利要求17所述的晶片封装体，其特征在于，还包括一焊线，该焊线电性接触延伸进入至少其中一个所述凹陷的该导线层。
19.根据权利要求18所述的晶片封装体，其特征在于，还包括一焊线，其中该焊线直接接触所述凹陷的最接近该第二表面的一最低凹陷的底部正上方的该导线层。
20.根据权利要求19所述的晶片封装体，其特征在于，该最低凹陷的底部大抵平行于该第二表面。
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