TWI569402B - 晶片封裝體 - Google Patents

晶片封裝體 Download PDF

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Publication number
TWI569402B
TWI569402B TW103103714A TW103103714A TWI569402B TW I569402 B TWI569402 B TW I569402B TW 103103714 A TW103103714 A TW 103103714A TW 103103714 A TW103103714 A TW 103103714A TW I569402 B TWI569402 B TW I569402B
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Taiwan
Prior art keywords
chip package
recess
layer
substrate
wafer
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TW103103714A
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English (en)
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TW201432880A (zh
Inventor
何彥仕
劉滄宇
林佳昇
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精材科技股份有限公司
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Publication of TW201432880A publication Critical patent/TW201432880A/zh
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Publication of TWI569402B publication Critical patent/TWI569402B/zh

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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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Description

晶片封裝體
本發明係有關於晶片封裝體及其形成方法，且特別是有關於以晶圓級封裝製程所形成之晶片封裝體。
晶片封裝製程是形成電子產品過程中之一重要步驟。晶片封裝體除了將晶片保護於其中，使免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
由於電子產品縮小化之需求仍持續，如何於有限空間中設置更多的導電線路成為重要課題。
本發明一實施例提供一種晶片封裝體，包括：一半導體基底，具有一第一表面及一第二表面；一第一凹陷，自該第一表面朝該第二表面延伸；一第二凹陷，自該第一凹陷之一底部朝該第二表面延伸，其中該第一凹陷之一側壁及該底部與該第二凹陷之一第二側壁及一第二底部共同形成該半導體基底之一外側表面；一導線層，設置於該第一表面上，且延伸進入該第一凹陷及/或該第二凹陷；一絕緣層，位於該導線層與該半導體基底之間；一晶片，設置於該第一表面上；以及一導電結構，設置於該晶片與 該第一表面之間。
本發明一實施例提供一種晶片封裝體，包括：一半導體基底，具有一第一表面及一第二表面；複數個凹陷，自該第一表面朝該第二表面延伸，且彼此相連通，其中該些凹陷之側壁與底部共同形成該半導體基底之一外側表面；一導線層，設置於該第一表面上，且延伸進入至少其中一該些凹陷；一絕緣層，位於該導線層與該半導體基底之間；一晶片，設置於該第一表面上；以及一導電結構，設置於該晶片與該第一表面之間。
100‧‧‧半導體基底
100a、100b‧‧‧表面
101‧‧‧介電層
104、104a‧‧‧導電墊
116‧‧‧絕緣層
118‧‧‧導線層
119‧‧‧線路重佈層
130a、130b‧‧‧凹陷
162、162a‧‧‧絕緣層
164、164a‧‧‧穿基底導電結構
172‧‧‧晶片
174、174a‧‧‧導電結構
176‧‧‧間隔層
178‧‧‧承載基底
179‧‧‧空腔
194、194a‧‧‧導電墊
196‧‧‧保護層
204‧‧‧銲線
第1圖顯示根據本發明一實施例之晶片封裝體的剖面圖。
第2圖顯示根據本發明一實施例之晶片封裝體的剖面圖。
第3圖顯示根據本發明一實施例之晶片封裝體的剖面圖。
第4圖顯示根據本發明一實施例之晶片封裝體的剖面圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定形式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發 明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間必然具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝各種晶片。例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)噴墨頭(ink printer heads)、或功率金氧半場效電晶體模組(power MOSFET modules)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而， 在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。在一實施中，上述切割後的封裝體係為一晶片尺寸封裝體(CSP；chip scale package)。晶片尺寸封裝體(CSP)之尺寸可僅略大於所封裝之晶片。例如，晶片尺寸封裝體之尺寸不大於所封裝晶片之尺寸的120%。
第1圖顯示根據本發明一實施例之晶片封裝體的剖面圖。晶片封裝體可包括半導體基底100，其具有表面100a及表面100b。半導體基底100可包括(但不限於)矽基底、矽鍺基底、或前述之組合。在一實施例中，半導體基底100可為一半導體晶片。例如，半導體基底100可為一影像感測晶片，具有影像感測區(未顯示)形成於其中，其例如形成於半導體基底100之中，且接近表面100a。
半導體基底100之表面100a上可選擇性形成有介電層101。介電層101中可形成有複數個導電墊，例如導電墊104及導電墊104a。每一導電墊104或導電墊104a可包括多層導電層之堆疊。這些堆疊的導電層可透過彼此間之導電通路(未顯示)而彼此電性連接。在一實施例中，導電墊104或導電墊104a可透過介電層101中及/或半導體基底100中之導電通路(未顯示)而與半導體基底100中之元件區(例如，影像感測區)中的電子元件電性性連接。 介電層101可具有露出導電墊104及導電墊104a之開口。介電層101之材質可包括(但不限於)氧化矽、氮化矽、氮氧化矽、或前述之組合。
在一實施例中，半導體基底100可透過圖案化製程及/或切割製程而具有複數個凹陷。這些凹陷可自表面100a朝表面100b延伸，並彼此相連通。此外，這些凹陷之側壁與底部可共同形成半導體基底100之外側表面。即，半導體基底100之部分的外側表面係由這些凹陷之側壁與底部所共同形成。在第1圖之實施例中，以兩個凹陷130b及130a為例做說明。然應注意的是，在其他實施例中，半導體基底100可具有三個或三個以上之相連通凹陷，且這些凹陷之底部及側邊可共同形成半導體基底100之外側表面。
如第1圖所示，凹陷130b可自半導體基底100之表面100a朝表面100b延伸。凹陷130a可自凹陷130b之底部朝表面100b延伸。凹陷130b之側壁及底部與凹陷130a之側壁及底部可共同形成半導體基底100之外側表面。
半導體基底100之表面100a上可形成有絕緣層116。絕緣層116可延伸進入凹陷130b及凹陷130a。在一實施例中，絕緣層116可順應性形成於凹陷130b及凹陷130a之側壁及底部上。絕緣層116之材質可包括(但不限於)氧化矽、氮化矽、氮氧化矽、高分子材料、其他適合的絕緣材料、或前述之組合。絕緣層116可具有露出導電 墊104及104a之開口。
半導體基底100之表面100a上之絕緣層116上可形成有複數個導電線，其包含導電線118。導電線118之材質可包括(但不限於)銅、鋁、金、鉑、鎳、錫、銀、或前述之組合。導線層118可延伸進入凹陷130b及/或凹陷130a。例如，在一實施例中，導線層118可延伸於凹陷130b之側壁與底部上，且更進一步延伸於凹陷130a之側壁與底部上，如第1圖所示。或者，導線層118可僅延伸進入凹陷130b。在一實施例中，導線層118可電性連接導電墊104a。在一實施例中，可選擇性形成銲線204。銲線204可電性接觸延伸進入凹陷130b及/或凹陷130a中之導線層118。在一實施例中，銲線204可直接接觸這些凹陷中之最接近表面100b之最低凹陷(例如，凹陷130a)之底部正上方的導線層118。最低凹陷(例如，凹陷130a)之底部可大抵平行於表面100b。銲線204可用於使其他電子構件(例如，印刷電路板)之電性訊號透過導線層118而傳遞至晶片封裝體。
半導體基底100之表面100a上可設置有晶片172。設置於晶片172與半導體基底100之表面100a之間的導電結構(例如，導電結構174或導電結構174a)可用以於半導體基底100與晶片172之間傳遞電性訊號。導電結構174及導電結構174a例如可為(但不限於)導電凸塊、銲球、或其他相似結構。
在一實施例中，導線層118可電性連接導電結 構174a。在此情形下，電性訊號除了可透過導電結構174a而於晶片172與半導體基底100之間傳遞外，還可透過導線層118及形成於凹陷130a或凹陷130b中之銲線204而與其他電子構件彼此傳遞電性訊號。此外，導電結構174還可直接電性接觸露出的導電墊104而使電性訊號於晶片172與半導體基底100之間傳遞。在一實施例中，晶片172可為訊號處理器晶片，而半導體基底100可為包含影像感測區(未顯示)之影像感測晶片。
在一實施例中，晶片封裝體可選擇性包括承載基底178。承載基底178可設置於半導體基底100之表面100b之上。承載基底178與半導體基底100之間還可選擇性設置間隔層176。間隔層176、承載基底178、及半導體基底100可共同圍繞出大抵密閉之空腔179。在一實施例中，承載基底178可包括透明基底，例如是(但不限於)玻璃基底、石英基底、藍寶石基底、透明高分子基底、或前述之組合。間隔層176之材質可包括(但不限於)高分子材料、金屬材料、陶瓷材料、半導體材料、或前述之組合。
第2圖顯示根據本發明一實施例之晶片封裝體的剖面圖，其中相同或相似之標號用以標示相同或相似之元件。在此實施例中，凹陷130b係自半導體基底100之表面100b朝表面100a延伸，且凹陷130a自凹陷130b之底部朝表面100a延伸。在此實施例中，半導體基底100之表面100b上設置有導電墊194及導電墊194a。保護層196可覆蓋半導體基底100之表面100b，且具有露出導電墊194 及導電墊194a之開口。導電墊194可透過形成於半導體基底100中之穿基底導電結構164而電性連接半導體基底100之表面100a上之導電墊104。穿基底導電結構164與半導體基底100之間可形成有絕緣層162。穿基底導電結構164之材質可包括(但不限於)銅、鋁、金、鉑、錫、鎳、或前述之組合。絕緣層162之材質可包括(但不限於)氧化矽、氮化矽、氮氧化矽、高分子材料、或前述之組合。
晶片172可透過設置於其下之導電結構174而傳遞電性訊號至半導體基底100或接收來自半導體基底100之電性訊號。此外，導電結構174a可電性連接導線層118，且導線層118可電性連接導電墊194a，並電性連接凹陷中之銲線層204。在此實施例中，導線層118不電性連接穿基底導電結構164。
第3圖顯示根據本發明一實施例之晶片封裝體的剖面圖，其中相同或相似之標號用以標示相同或相似之元件。第3圖所示結構相似於第1圖所示結構，差異主要在於第3圖所示結構更包括線路重佈層119。線路重佈層119可形成於絕緣層116之上。線路重佈層119之材質可包括(但不限於)銅、鋁、金、鉑、錫、鎳、或前述之組合。在一實施例中，線路重佈層119與導線層118可圖案化自相同的導電層。因此，線路重佈層119與導線層118可同時形成，並具有相同的材質。線路重佈層119可用以電性連接晶片172下方之導電結構174。在一實施例中，線路重佈層119可延伸進入半導體基底100之凹陷之中。例如， 線路重佈層119亦可延伸進入凹陷130a，並可與電性接觸銲線204。或者，延伸進入凹陷130a之線路重佈層119可不電性接觸銲線204，但可選擇性與其他導電結構或其他銲線電性連接。
第4圖顯示根據本發明一實施例之晶片封裝體的剖面圖，其中相同或相似之標號用以標示相同或相似之元件。第4圖所示結構相似於第2圖所示結構，差異主要在於第4圖所示之結構更包括穿基底導電結構164a。穿基底導電結構164a電性連接導電墊104a及導電墊194a。此外，導線層118電性連接導電墊194a、導電結構174a、及銲線204。
在本發明實施例中，透過堆疊晶片與將導線層導引至凹陷之中，可於有限空間之中，設置更多的導電線路，有助於晶片封裝體之縮小化。由於導線線路之傳遞距離減小，訊號傳遞速度可獲提升。此外，由於銲線形成於凹陷之中，可受到凹陷之保護而使晶片封裝體的可靠度提升。由於銲線係形成於凹陷之中，可使晶片封裝體之整體體積縮小。本發明實施例所形成之凹陷包括複數個相連通之凹陷，可使導線層於更為緩和之輪廓上沉積，可提升導線層之可靠度。
100‧‧‧半導體基底
100a、100b‧‧‧表面
101‧‧‧介電層
104、104a‧‧‧導電墊
116‧‧‧絕緣層
118‧‧‧導線層
130a、130b‧‧‧凹陷
172‧‧‧晶片
174、174a‧‧‧導電結構
176‧‧‧間隔層
178‧‧‧承載基底
179‧‧‧空腔
204‧‧‧銲線

Claims (20)

  1. 一種晶片封裝體，包括：一半導體基底，具有一第一表面及一第二表面；一第一凹陷，自該第一表面朝該第二表面延伸；一第二凹陷，自該第一凹陷之一底部朝該第二表面延伸，其中該第一凹陷之一側壁及該底部與該第二凹陷之一第二側壁及一第二底部共同形成該半導體基底之一外側表面；一導線層，設置於該第一表面上，且延伸進入該第一凹陷及/或該第二凹陷；一絕緣層，位於該導線層與該半導體基底之間；一晶片，設置於該第一表面上；以及一導電結構，設置於該晶片與該第一表面之間。
  2. 如申請專利範圍第1項所述之晶片封裝體，更包括：一介電層，位於該第一表面與該絕緣層之間；以及一第一導電墊，位於該介電層之中，其中該導線層電性連接該第一導電墊。
  3. 如申請專利範圍第2項所述之晶片封裝體，其中該導線層電性連接該導電結構。
  4. 如申請專利範圍第2項所述之晶片封裝體，更包括：一第二導電墊，位於該介電層之中；以及一第二導電結構，設置於該晶片與該第一表面之間，且電性連接該第二導電墊。
  5. 如申請專利範圍第4項所述之晶片封裝體，其中該第二導電結構透過一線路重佈層而電性連接該第二導電墊。
  6. 如申請專利範圍第1項所述之晶片封裝體，其中該半導體基底為一半導體晶片。
  7. 如申請專利範圍第6項所述之晶片封裝體，其中該半導體晶片為一影像感測晶片，而該晶片為一訊號處理器晶片。
  8. 如申請專利範圍第1項所述之晶片封裝體，其中該導線層延伸於該第二凹陷之該第二底部上。
  9. 如申請專利範圍第1項所述之晶片封裝體，更包括一銲線，電性接觸延伸進入該第一凹陷及/或該第二凹陷中之該導線層。
  10. 如申請專利範圍第1項所述之晶片封裝體，更包括一承載基底，設置於該第二表面上。
  11. 如申請專利範圍第10項所述之晶片封裝體，更包括一間隔層，設置於該承載基底與該半導體基底之間，其中該間隔層、該承載基底、及該半導體基底共同圍繞出大抵密封之一空腔。
  12. 如申請專利範圍第10項所述之晶片封裝體，其中該承載基底為一透明基底。
  13. 如申請專利範圍第1項所述之晶片封裝體，更包括：一介電層，位於該第二表面上；一導電墊，位於該介電層之中； 一穿基底導電結構，穿過該第一表面及該第二表面，且電性連接該導電墊及該導電結構；以及一第二絕緣層，位於該穿基底導電結構與該半導體基底之間。
  14. 如申請專利範圍第13項所述之晶片封裝體，其中該導線層電性連接該穿基底導電結構。
  15. 如申請專利範圍第13項所述之晶片封裝體，其中該導線層不電性連接該穿基底導電結構。
  16. 如申請專利範圍第13項所述之晶片封裝體，更包括：一第二導電墊，位於該介電層之中；一第二導電結構，設置於該晶片與該第一表面之間；一第二穿基底導電結構，穿過該第一表面及該第二表面，且電性連接該第二導電墊及該第二導電結構；以及一第三絕緣層，位於該第二穿基底導電結構與該半導體基底之間。
  17. 一種晶片封裝體，包括：一半導體基底，具有一第一表面及一第二表面；複數個凹陷，自該第一表面朝該第二表面延伸，且彼此相連通，其中該些凹陷之側壁與底部共同形成該半導體基底之一外側表面；一導線層，設置於該第一表面上，且延伸進入至少其中一該些凹陷；一絕緣層，位於該導線層與該半導體基底之間；一晶片，設置於該第一表面上；以及 一導電結構，設置於該晶片與該第一表面之間。
  18. 如申請專利範圍第17項所述之晶片封裝體，更包括一銲線，電性接觸延伸進入至少其中一該些凹陷之該導線層。
  19. 如申請專利範圍第18項所述之晶片封裝體，更包括一銲線，其中該銲線直接接觸該些凹陷之最接近該第二表面之一最低凹陷之底部正上方的該導線層。
  20. 如申請專利範圍第19項所述之晶片封裝體，其中該最低凹陷之底部大抵平行於該第二表面。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120152606A1 (en) * 2010-12-16 2012-06-21 Ibiden Co., Ltd. Printed wiring board
TWI563616B (en) * 2014-04-28 2016-12-21 Xintex Inc Stacked chip package and method for forming the same
US9812413B2 (en) * 2015-01-21 2017-11-07 Xintec Inc. Chip module and method for forming the same
US10056319B2 (en) * 2016-04-29 2018-08-21 Delta Electronics, Inc. Power module package having patterned insulation metal substrate
JP6615701B2 (ja) * 2016-06-24 2019-12-04 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
CN109997227A (zh) * 2017-08-31 2019-07-09 深圳市大疆创新科技有限公司 电子器件及包括其的测距装置和电子设备
JP7019894B2 (ja) 2017-08-31 2022-02-16 エスゼット ディージェイアイ テクノロジー カンパニー リミテッド 物体を感知する方法及びセンサシステム
CN207517678U (zh) * 2017-12-07 2018-06-19 中芯长电半导体（江阴）有限公司 具有天线组件的半导体封装结构
CN207852654U (zh) * 2017-12-27 2018-09-11 中芯长电半导体（江阴）有限公司 具有天线组件的半导体封装结构
CN207852888U (zh) * 2017-12-27 2018-09-11 中芯长电半导体（江阴）有限公司 具有天线组件的半导体封装结构
CN207852651U (zh) * 2017-12-27 2018-09-11 中芯长电半导体（江阴）有限公司 具有天线组件的半导体封装结构
KR20210101355A (ko) * 2020-02-07 2021-08-19 삼성전자주식회사 반도체 패키지

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7310239B1 (en) * 2004-02-20 2007-12-18 Silicon Pipe, Inc. IC packaging interposer having controlled impedance or optical interconnections and an integral heat spreader
US20110278741A1 (en) * 2010-05-14 2011-11-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0778968A (ja) * 1993-09-06 1995-03-20 Toshiba Corp 半導体装置とその製造方法
US5714800A (en) * 1996-03-21 1998-02-03 Motorola, Inc. Integrated circuit assembly having a stepped interposer and method
NO20001360D0 (no) * 2000-03-15 2000-03-15 Thin Film Electronics Asa Vertikale elektriske forbindelser i stabel
US20030006493A1 (en) * 2001-07-04 2003-01-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
US6747348B2 (en) * 2001-10-16 2004-06-08 Micron Technology, Inc. Apparatus and method for leadless packaging of semiconductor devices
US6750547B2 (en) * 2001-12-26 2004-06-15 Micron Technology, Inc. Multi-substrate microelectronic packages and methods for manufacture
US8258607B2 (en) * 2005-10-19 2012-09-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Apparatus and method for providing bypass capacitance and power routing in QFP package
KR100997787B1 (ko) * 2008-06-30 2010-12-02 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
TWI619218B (zh) * 2010-05-11 2018-03-21 精材科技股份有限公司 晶片封裝體及其形成方法
KR101787041B1 (ko) * 2010-11-17 2017-10-18 삼성전자주식회사 식각방지막이 구비된 반도체 소자 및 그 제조방법
US9711403B2 (en) * 2011-01-17 2017-07-18 Xintec Inc. Method for forming chip package
CN102738373B (zh) * 2011-04-11 2014-11-05 展晶科技(深圳)有限公司 发光二极管封装结构及其制造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7310239B1 (en) * 2004-02-20 2007-12-18 Silicon Pipe, Inc. IC packaging interposer having controlled impedance or optical interconnections and an integral heat spreader
US20110278741A1 (en) * 2010-05-14 2011-11-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant

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