TWI573223B - 空腔基板保護之積體電路 - Google Patents

空腔基板保護之積體電路 Download PDF

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Publication number
TWI573223B
TWI573223B TW104107704A TW104107704A TWI573223B TW I573223 B TWI573223 B TW I573223B TW 104107704 A TW104107704 A TW 104107704A TW 104107704 A TW104107704 A TW 104107704A TW I573223 B TWI573223 B TW I573223B
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Taiwan
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substrate
cavity
die
integrated circuit
attached
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TW104107704A
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English (en)
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TW201535603A (zh
Inventor
宏 沈
查爾斯Ｇ 渥奇克
阿爾卡爾古德Ｒ 斯塔拉姆
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英凡薩斯公司
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Description

空腔基板保護之積體電路 【相關申請案之交互參照】
本申請案主張美國先行申請案序號第61/952,066號的優先權，標題為「INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES,AND METHODS OF MANUFACTURE(空腔基板保護之積體電路與製造方法)」，其申請於2014年3月12日，在此以引用之方式將其併入。
本文件係關於積體電路，且更具體地，係關於具有包含半導體積體電路的晶粒之組件。
在積體電路的製造中，一或更多個電路製造在半導體晶圓中，且然後在所謂的「單分」或「切割」的處理中分離成「晶粒」(也稱為「晶片」)。晶粒(例如第1圖的110所示)附接至佈線基板(WS,wiring substrate，例如印刷佈線板)120，其具有導線130來連接晶粒至彼此且至系統的其他元件。更具體地，晶粒具有連接至晶粒的電路(未圖示)之接觸墊110C，且這些接觸墊附接至WS 120的接觸墊120C。墊120C藉由導線130而互連。藉由可包含焊料、導電環氧樹脂、或其他種類的連接140，來執行墊110至墊120C的附接。
封裝150(例如，具有二氧化矽或其他粒子的環氧樹脂)保護晶粒110與連接140免於濕氣與其他污染物、紫外線、α粒子、以及其他可能的有害元素。封裝也強化了晶粒至WS的附接，來抵抗力學應力，並且協助將熱傳導遠離晶粒(至選擇性的散熱器160，或直接至周圍(例如，空氣))。
吾人之所欲在於，提供晶粒免於力學應力、熱、以及其他有害元素的改良保護。
此章節總結了本發明的一些範例性實施。
在一些實施例中，晶粒由額外的保護基板保護，保護基板附接至佈線基板。晶粒位於保護基板中的空腔中(晶粒可突伸出空腔之外)。保護基板可類似於用於保護MEMS(Micro-Electro-Mechanical Structures，微機電結構)元件的覆蓋晶圓(cap wafer)；參見K.Zoschke等人所寫的「Hermetic Wafer Level Packaging of MEMS Components Using Through Silicon Via and Wafer to Wafer Bonding Technologies(使用矽通孔與晶圓至晶圓接合技術之MEMS元件的全封閉晶圓級封裝)」(2013年電子元件與技術會議，IEEE，1500-1507頁)；也參見2005年10月25日頒發給Siniaguine的美 國專利第6,958,285號。然而，在一些實施例中，保護基板施加壓力於晶粒上(例如，每一晶粒可實體接觸於空腔表面)，以強化晶粒至WS 120的力學附接、提供晶粒與保護基板之間良好的熱傳導性、協助使晶粒平坦(如果晶粒翹曲的話)、以及減小垂直尺寸。保護基板可或可不具有連接至晶粒或至佈線基板之其自身的電路。
在一些實施例中，晶粒不接觸空腔表面，但是晶粒藉由實體接觸於晶粒與空腔表面之固體材料(例如，接合層)而分隔於空腔表面。在一些實施例中，晶粒或固體材料在一些(但非全部)操作溫度時實體接觸於空腔表面(例如，實體接觸可能僅存在於較高的溫度，其中晶粒膨脹)。操作溫度為可獲得電性功能的溫度。
在一些實施例中，空腔包含晶粒的堆疊，且堆疊中的頂部晶粒接觸於空腔表面(或者頂部晶粒之上的固體材料實體接觸於空腔表面)。在一些實施例中，每一晶粒(或者堆疊中的頂部晶粒(如果有堆疊的話))的整個頂表面實體接觸於空腔表面。在一些實施例中，保護基板向下施加壓力於每一空腔中的晶粒上，以強化晶粒至佈線基板的附接並且抵消晶粒翹曲。
在一些實施例中，佈線基板為中介層。中介層通常使用作為中間基板，以調節晶粒製造技術與印刷佈線基板(PWS,printed wiring substrates)之間的失配。更具體地，晶粒的接觸墊110C可放置得遠遠較靠近彼此(以較小的間距)，相較於PWS墊120C來說。因此(第2圖)，中間基板120.1可使用在晶粒120與PWS(以120.2表示)之間。中介層120.1包含基板120.1S(例如，半導體或其他材料)、基板120.1S的頂部上的再分佈層(RDL, redistribution layer)210.T、以及基板120.1S的底部上的另一再分佈層210.B。每一RDL 210.T、210.B包含互連線216，互連線216藉由RDL的介電質220而絕緣於彼此與基板120.1S。線216連接至中介層的頂部上的接觸墊120.1C.T以及底部上的接觸墊120.1C.B。RDL 210.T的線216藉由導電(例如，金屬化的)通孔224而連接至RDL 210.B的線216。墊120.1C.T藉由連接140.1而附接至晶粒的墊110C，如同第1圖中。墊120.1C.B利用連接140.2而附接至PWS 120.2的墊120.2C。墊120.1C.B比墊120.1C.T有較大的間距，以調節PWS接點120.2C的間距。
中介層基板120.1S應盡可能地薄，以縮短晶粒110與PWS120.2之間的信號路徑，且因此使系統更快且耗電更少。此外，如果中介層為薄的，可促進金屬化的通孔224的製造。然而，薄的中介層難以處理：它們為易碎的、易翹曲的、且在製造期間不吸收或散熱。因此，一般的製造處理(例如，上面引用的Zoschke等人中所述)在製造期間將中介層附接至暫時基板(「支撐晶圓」)。支撐晶圓稍後移除。附接與分離暫時的支撐晶圓為沉重的負擔。前述美國專利第6,958,285號的處理不使用支撐晶圓。下述的一些新穎處理也不使用支撐晶圓。
本發明不限於上述的特徵與優點，並且包含下述的其他特徵。
110‧‧‧晶粒
110C‧‧‧接觸墊
120‧‧‧佈線基板(WS)
120.1‧‧‧中間基板(中介層)
120.1C.B‧‧‧接觸墊
120.1C.T‧‧‧接觸墊
120.1S‧‧‧基板
120.2‧‧‧PWS
120.2C‧‧‧墊
120C‧‧‧接觸墊
130‧‧‧導線
140、140.1、140.2‧‧‧連接
150‧‧‧封裝
160‧‧‧散熱器
210.B‧‧‧再分佈層(RDL)
210.T‧‧‧再分佈層
216‧‧‧互連線
220‧‧‧介電質
224、224B‧‧‧通孔
224M‧‧‧金屬
310‧‧‧層
320‧‧‧光阻
324‧‧‧介電質
410‧‧‧保護基板
410S‧‧‧基板
410L‧‧‧腿部
414‧‧‧空腔
420‧‧‧輔助層
430‧‧‧光阻
504‧‧‧組件
504S‧‧‧堆
525‧‧‧溫度界面材料(TIM)
610‧‧‧黏合劑
810、820‧‧‧接合層
910‧‧‧接觸墊
920‧‧‧介電質
930‧‧‧介電質
1110C‧‧‧接觸墊
1210‧‧‧結構
第1與2圖為先前技術所建構並且包含積體電路的組件的垂直橫剖面 圖。
第3A、3B、3C、3D、3E、4A、4B、4C、5A、5B、5C、5D、5E.1、6、7、8A、8B、8C、9A、9B、9C、9D、10圖為本較佳較實施例的結構的垂直橫剖面圖，詳述如下。
第5E.2與5E.3圖為本較佳較實施例之水平橫剖面的底視圖，詳述如下。
第6、7、8A、8B、8C、9A、9B、9C、9D、10、11、12圖為本較佳較實施例之結構的垂直橫剖面圖，詳述如下。
此章節中敘述的實施例非用以限制本發明。基本上，本發明不限於特定的材料、處理、尺寸或其他細節，除了如同由所附申請專利範圍所界定的。
第3A圖為本發明較佳實施例之中介層120.1的製造的開始階段。最初選擇足夠厚之中介層基板120.1S，以於製造中，易於處理與充分散熱。在一些實施例中，基板120.1S為200mm或300mm直徑與650微米或更大厚度的單晶矽晶圓。這些材料與尺寸為範例，不限制本發明。例如，基板120.1S可由其他半導體材料(例如砷化鎵)、或玻璃、或藍寶石、或金屬、或可能的其他材料製成。可能的材料包含NbTaN與LiTaN。基板稍後將打薄；例如，在矽的實例中，最終的厚度可為5至50微米。這些尺寸並非限制。
基板120.1S經圖案化，形成盲通孔224B(第3B圖)。「盲」指通孔不穿過基板120.1S。例如，針對矽基板，首先，選擇性的層310(第3A圖)形成在基板120.1S上，以保護基板及/或改良隨後形成的光阻320的附 著。例如，層310可為熱氧化、化學氣相沉積(CVD)或濺射所形成的二氧化矽。然後，沉積並且光微影圖案化光阻320，以界定通孔。在光阻320曝露的區域中蝕刻層310與基板120.1S，以形成盲通孔。通孔深度等於或稍微大於基板120.1S的最終深度，例如針對一些矽基板的實施例為5至51微米。通孔可藉由乾式蝕刻來形成，例如乾式反應離子蝕刻(DRIE,dry reactive ion etching)。範例之每一通孔直徑可為60微米或更小，但是其他尺寸也可能。通孔可為垂直的(如圖所示)，或者可具有傾斜的側壁。如同上述，特定的尺寸、處理與其他特徵僅為例示，而非限制。
通孔之後金屬化。如果基板120.1S為矽，進行如下步驟。移除光阻320與保護層310，且介電質層324(第3C圖)形成於基板120.1S的完整頂表面上。介電質324可作為通孔表面的襯裡。在一些實施例中，介電質324藉由矽基板的熱氧化或藉由CVD或物理氣相沉積(PVD)而形成。介電質324使基板與隨後形成在通孔224B中的金屬電性絕緣。介電質厚度取決於吾人所欲的處理參數，且在範例性熱氧化物實施例中為1微米(熱氧化物為藉由熱氧化所形成的二氧化矽)。其他的尺寸與材料可用來替代。如果基板120.1S本身為介電質，介電質324可省略。
然後，金屬224M(第3D圖)形成於通孔224B中及介電質324之上。實施例中，金屬224M填滿通孔，但是在其他實施例中，金屬為通孔表面上的襯裡。在範例性實施例中，金屬224M為電鍍銅。例如，阻障層(金屬或介電質，未單獨繪示)先形成於介電質324上，以協助銅附著並且防止銅擴散至介電質324或基板120.1S中。合適的阻障層可包含一層鈦-鎢(參見Kosenko等人於2012年9月13日公開之美國早期公開專利第2012/0228778 號，在此以引用之方式將其併入)，及/或含有鎳的層(Uzoh等人於2013年1月17日公開之US 2013/0014978，在此以引用之方式將其併入)。然後，種子層(例如銅)藉由物理氣相沉積(例如，PVD，可能為濺射)形成於阻障層上。然後，電鍍銅於種子層上，以填充通孔224B且覆蓋整個基板120.1S。然後，藉由化學機械研磨(CMP)，從通孔之間的區域移除銅。選擇性地，CMP也可從這些區域移除阻障層(如果存在的話)，並且可停止於介電質324上。因此，銅與阻障層僅保留在通孔224B中與之上。
為了便於敘述，我們將稱通孔224為「金屬化的」，但是也可使用非金屬的導電材料(例如，摻雜的多晶矽)。
如果層224M並未填滿通孔，但是僅作為通孔表面的襯裡，一些其他材料(未圖示)可形成在層224M上作為填料，以填充通孔且提供平坦的頂表面給晶圓。這種填料材料可為聚酰亞胺，例如藉由旋塗法來沉積。
選擇性地，RDL 210.T(第3E圖)形成在基板120.1S的上方，以提供接觸墊120.1C.T在吾人所欲的位置處。RDL 210.T可藉由，例如，相關於第1與2圖之上述先前技術的技術來形成。如果接觸墊120.1C.T由金屬224M的頂部區域提供，則省略RDL 210.T。在此種實例中，如果基板120.1S並非介電質，則介電質層可形成在基板上並且受到光微影圖案化來曝露接觸墊120.1C.T。
中介層120.1可包含在基板120.1S與再分佈層210.T中的電晶體、電阻器、電容器與其他裝置(未圖示)。在通孔224與RDL 210.T的製造之前、期間及/或之後，吾人可使用上述的處理步驟及/或額外的處理步驟來 形成這些裝置。此種製造技術為熟知的。參見例如前述的美國專利第6,958,285號以及早期公開的專利公開案2012/0228778。
如第1與2圖之先前技術的方法或其他方法(例如，擴散接合；在此種實例中，連接140.1並非額外的元件，但是為接觸墊110C及/或120.1C.T的部分)，可利用連接140.1將晶粒110附接至接觸墊120.1C.T。
選擇性地，使用相關於第1圖之上述的相同技術(例如，藉由模製及/或底部填充)，封裝(未圖示)可形成於晶粒的周圍及/或晶粒之下。封裝可為任何合適的材料(例如，具有二氧化矽或其他粒子的環氧樹脂)。在一些實施例中並未使用封裝。其他實施例使用封裝，但是對於封裝的需求是寬鬆的，因為晶粒將由額外的保護基板410(第5A圖)來保護，如同下述。在一些實施例中，封裝僅設置於晶粒的下方(作為底部填充)，亦即，僅在晶粒與基板120.1S之間(圍繞著連接140.1)。
第4A-4C圖為保護基板410的製造。許多變化都有可能。基板410應該具有足夠的剛性，以促進組件的後續處理，如同下面解釋的。在所示的實施例中，基板410包含厚度為650微米或更大的單晶矽基板410S。其他材料與厚度都有可能，取決於任何可能為重要的因素(包含材料與處理的可用性)。一個可能的因素為，減少基板410與120.1S之間的熱膨脹係數(CTE)的不匹配：如果基板120.1S為矽，則基板410S可為矽或具有類似的CTE的另一種材料。另一個因素為，減少基板410與晶粒110之間的CTE不匹配。在一些實施例中，基板410S不具有任何電路，但是如果想要在基板410S中或上有電路，則這可能影響材料的選擇。在下述的步驟之前，及/或中間，及/或之後，則可製造電路。
另一個可能的因素為，高的熱傳導性，以促成基板410作用為散熱器。例如，可為合適的金屬。
空腔414(第4C圖)形成在基板410中，以對應晶粒110的尺寸與位置。範例處理如下(此處理適合於矽基板410S，且可能不適合於其他材料；已知的處理可用於矽或其他材料)。首先，形成輔助層420(第4B圖)，以覆蓋基板410S，來保護隨後形成的光阻430或改良隨後形成的光阻430的附著。沉積光阻430且光微影圖案化光阻430，以界定空腔。蝕刻掉光阻開口所曝露的輔助層420。然後，在這些開口中蝕刻基板410S，以形成具有傾斜、向上擴張的側壁之空腔414。空腔深度取決於晶粒110的厚度與連接140.1，如同下面解釋的。非傾斜(垂直)或逆行的側壁或其他側壁輪廓也可能。
然後，移除光阻430。在所示的範例中，也移除輔助層420，但是在其他實施例中，層420保留在最終結構中。
如同第5A圖所示，基板410附接中介層120.1，使得每一晶粒110配接至對應的空腔414中。更具體地，保護基板410的腿部410L附接中介層120.1的頂表面(例如，接至RDL 210.T(如果RDL存在的話)；腿部410L為保護基板410圍繞空腔的那些部分)。基板與中介層的附接為直接接合，但是其他類型的附接(例如，藉由黏合劑)也可使用，下面將進一步敘述。整個組件以元件符號504來標示。
在第5A圖中，晶粒的頂表面實體接觸於空腔414的頂表面。在一些實施例中，每一晶粒的頂表面接合至空腔的頂表面(直接或以某種其他方式，例如，藉由黏合劑)。此接合增加了兩個基板之間的接合強度， 並且改良了從晶粒至保護基板的熱路徑的熱傳導性。此外，晶粒與空腔表面之間的接合限制了晶粒的橫向運動，且因此抵消了可能弱化連接140.1的橫向或其他力。例如，如果保護基板410與中介層120.1具有匹配的CTE，則晶粒的頂表面至空腔表面之接合將導致保護基板410，使晶粒在熱循環中跟隨中介層的運動；相信這可減輕晶粒至中介層的連接140.1上的應力。
在其他實施例中，晶粒並未接合至空腔的頂表面，且因此晶粒的頂表面在熱運動中可沿著空腔的頂表面橫向滑動。這可降低熱應力，例如，如果晶粒與中介層的CTE匹配較優於中介層與保護基板410之間的匹配。
在一些實施例中，不管晶粒是否接合至空腔表面，晶粒上的基板410的向下壓力有助於抵消晶粒翹曲。在一些實施例中，晶粒傾向於隨溫度增高而增加翹曲，且該壓力也可隨溫度增高而增加(例如，如果晶粒垂直膨脹超過保護基板的腿部410L)。
如同上述，在一些實施例中，晶粒係底部填充及/或由合適的應力減輕材料(例如，環氧樹脂)從上方封裝。在從上方封裝的實例中，該封裝可為實體接觸於空腔414的頂表面之固體材料(可能為熱固的)。該封裝可或可不接合至空腔表面，如同上述，其中益處類似於針對無封裝的實施例所上述的那些。
為了確保晶粒(或封裝)與空腔之間的實體接觸，晶粒(或封裝)的頂表面應該具有一致的高度。為了改良高度一致性，在基板410接合至中介層120.1之前，可研磨晶粒(或封裝)。合適的研磨處理包含精研、研磨與化學機械研磨(CMP)。另外，在將晶粒插入空腔之前，空腔表面及 /或晶粒可設有合適的溫度界面材料(TIM,temperature interface material，繪示在下面討論的第5E.2與5E.3圖中的525)，以改良晶粒與基板410之間的熱轉移。TIM的熱傳導性通常可較高於空氣的熱傳導性。範例性的TIM為那些在預期的操作溫度範圍內(例如針對某些組件，0℃至200℃)以半固體、凝膠狀(潤滑脂狀)的狀態存在或者至少當溫度高時使晶粒冷卻得特別令人滿意的(例如針對某些組件，20℃至200℃)之材料。凝膠狀材料填充晶粒與基板410之間的自由空間，以提供遠離晶粒的導熱路徑。範例性TIM材料為可從銀北極公司((其在美國加州具有辦公室)取得的熱潤滑脂；該潤滑脂的熱傳導性為1W/mK。
在接合基板410至中介層120.1之後，從底部將中介層打薄，以曝露金屬224M(第5B圖)。打薄包含部分移除基板120.1S與介電質324(如果介電質存在的話)。打薄可藉由已知技術來執行(例如，基板120.1S與介電質324的乾式或濕式、遮罩或未遮罩蝕刻之後，基板120.1S的機械研磨或精研；基板與介電質在一些實施例中為同時蝕刻)。在一些實施例中，介電質324在打薄操作結束時突伸出金屬224M周圍的基板120.1S之外，且金屬224M突伸出介電質。參見例如前述的美國專利第6,958,285號。如同上述，本發明不限於特定的處理。
有利的是，中介層120.1藉由基板410來保持平坦，所以促進組件504的處理。基板410也有助於吸收且散去在此製造階段與隨後的製造階段期間以及組件504的後續操作中所產生的熱。基板120.1S的最終厚度因此可非常小，例如50微米或甚至5微米或更小。因此，盲通孔224B(第3B圖)可為淺的。淺的深度可促進金屬化通孔的製造(亦即，促進通孔的蝕 刻以及後續沉積介電質與金屬進入通孔中)。深度淺也縮短通過通孔的信號路徑。此外，如果通孔淺，每一通孔可較窄，同時仍然允許可靠的介電質與金屬沉積。可因此減小通路間距。
如果需要的話，保護基板410可從頂部打薄；此未繪示。基板120.1S與410的組合厚度由吾人所欲的特性界定，例如剛性、耐翹曲、散熱、以及組件尺寸。
隨後的處理步驟取決於特定的應用。在一些實施例中(第5C圖)，可能使用先前技術的技術(例如如同第2圖中)，將RDL 210.B形成在基板120.1S的底部上。RDL提供接觸墊120.1C.B，且連接接觸墊120.1C.B與金屬224M。(如果省略RDL，則由金屬224M提供接觸墊)。如果需要的話，組件504可切割成堆504S(第5D圖)。然後，該等堆(組件堆或整個組件504，如果省略切割的話)附接至其他結構，例如第5E.1圖中的佈線基板120.2(例如，印刷佈線基板)。在第5E.1圖的範例中，堆504S附接至PWS 120.2，且基本上，堆504S的接點120.1C.B附接至PWS接點120.2C時，可藉由第1或2圖中的相同技術。PWS 120.2的導線130連接接觸墊120.2C至彼此或其他元件。這些細節並非限制。
第5E.2圖為沿著第5E.1圖中的線5E.2-5E.2之水平橫剖面的可能底視圖。在第5E.2圖的範例中，晶粒由溫度界面材料(TIM)525圍繞。腿部410L形成完全圍繞每一晶粒的區域，且接合至腿部的中介層也完全圍繞每一晶粒。
第5E.3圖為相同水平橫剖面的另一可能的底視圖，也具有TIM 525。在此範例中，腿部410L僅設置在每一晶粒的兩對立側上(左側與 右側)，但是並未設置在晶粒的上方與下方。每一空腔414為基板410S中的水平凹槽，可能含有多個晶粒沿著該凹槽橫向散佈。凹槽可運行通過整個基板。其他空腔形狀也可能。
如同上述，保護基板410與中介層120.1可藉由黏合劑來接合，且第6圖係藉由黏合劑610來接合。黏合劑610設置在腿部410L或中介層120.1的對應區域或兩者上。該結構對應第5A圖(在中介層打薄之前)。在一些實施例中，黏合劑為彈性的，具有低彈性係數(例如：矽樹脂橡膠(Silicone ruber))，以協助吸收晶粒110的熱膨脹(使得來自膨脹的晶粒110的壓力將不會損壞保護基板410或晶粒)。在一些實施例中，如果晶粒的CTE等於或大於保護基板410或基板410S的CTE，這是有益的。黏合劑的彈性也吸收晶粒的頂表面或空腔414的頂表面的高度不一致性。另外，為了吸收晶粒的膨脹，黏合劑可具有等於或大於晶粒的CTE之CTE。範例性的黏合劑為環氧樹脂型的底部填充。
第7圖為類似的實施例，但是黏合劑610覆蓋保護基板410S的整個底表面。黏合劑接合晶粒(或封裝)的頂表面至空腔的頂表面。黏合劑的CTE可等於、或大於、或小於晶粒的CTE。
第8A-8C圖例示使用單獨的接合層810、820來直接接合保護基板410至中介層120.1。在一些實施例中，接合層為二氧化矽，但是也可使用其他材料(例如，用於共熔接合的金屬)。參見第8A圖，晶粒附接至中介層120.1，如同第3E圖；晶粒之後選擇性地底部填充及/或從上方封裝(在第8A圖中，封裝150封裝且底部填充晶粒)。藉由任何合適的技術(例如，濺射)，形成接合層810(例如，二氧化矽或金屬)來覆蓋中介層與晶粒(以 及封裝，如果存在的話)。
參見第8B圖，保護基板410設有空腔，如同第4C圖中。然後，藉由任何合適的技術(例如，濺射，或熱氧化(如果基板410S為矽))，形成接合層820(例如，二氧化矽或金屬)來覆蓋基板表面。
參見第8C圖，中介層接合至基板410，使得層810、820實體接觸於彼此。然後，加熱該結構，以將層820接合至層810，其中兩層接觸，亦即，在腿部410L處與在空腔的頂表面處。然而，在一些實施例中，在接合之前，層820在空腔的頂表面處移除，並未接合晶粒至空腔的頂表面。
第6-8A圖的結構的後續處理(中介層打薄，可能的切割等)可如同上述的其他實施例。
上述處理步驟的順序並非限制；例如，通孔224可在中介層打薄之後形成。第9A-9D圖為範例性處理。中介層120.1基本上如同在第3E或6或8A圖中所製造，但是沒有通孔224(通孔將在稍後形成)。具體地，介電質324為中介層基板120.1S上的平坦層。然後，接觸墊910在未來通孔224的位置處形成於基板120.1S上。RDL 210.T選擇性地製造在中介層的頂部上，以連接接觸墊910至中介層的頂部上的墊120.1C.T。(替代地，墊120.1C.T可由墊910提供。)晶粒110附接至墊120.1C.T，且選擇性地底部填充與封裝。接合層810(如圖所示)選擇性地沉積，如同第8A圖中，以接合至保護基板(替代地，該接合可藉由第6或7圖中的黏合劑，或藉由相關於第5A圖所上述的直接接合處理)。
具有晶粒附接的中介層120.1然後接合至保護基板410(第9B圖)，如同上述的任何實施例中。然後，中介層打薄(第9C圖)。晶粒在後 續步驟期間將由基板410保護。基板410可在任何吾人所欲的階段打薄。
然後，金屬化的通孔224從中介層底部形成。範例性處理如下：
1.介電質920(例如，二氧化矽或氮化矽)沉積(例如，藉由濺射或CVD)，覆蓋中介層基板120.1S的底表面。
2.通孔(貫通孔)從底部蝕刻通過介電質920與基板120.1S。此為遮罩蝕刻，停止於接觸墊910上。
3.介電質930(例如，二氧化矽或氮化矽)沉積(例如，藉由濺射或CVD)，覆蓋中介層基板120.1S的底表面並且作為通孔的襯裡。介電質930從底部覆蓋接觸墊910。
4.蝕刻介電質930，以曝露接觸墊910。此可為遮罩蝕刻。替代地，可使用毯覆各向異性(垂直)蝕刻從每一接觸墊910的至少一部分之上移除介電質930，同時使介電質留在通孔側壁上。垂直蝕刻可或可不移除通孔外部的介電質930。
5.形成導電材料224M(例如，金屬)於通孔中，可能藉由上述相同的技術(例如，銅電鍍)。導電材料不存在於通孔外部(例如，它可藉由CMP研磨掉)。導電材料可填充通孔或僅作為通孔表面的襯裡。每一通孔中的導電材料實體接觸於對應的墊910。
隨後的處理步驟如第5C-5E.3圖所述，基本上，底部的RDL 210.B(第5C圖)與連接140.2可如上述形成。如果需要，可切割該結構(第5D圖)，並且附接至另一結構(例如，第5E.1圖中的PWS 120.2)。
通孔224為選擇性的，且進一步，基板120.1可為任何佈線基 板，例如第10圖的120所示。此圖式在腿部410L處與空腔頂表面處使用黏合劑610來接合保護基板410至WS 120之實施例，但是可使用上述的任何其他接合方法。底部填充或其他封裝並未繪出，但是整個晶粒的封裝可存在有或沒有底部填充。
相關於第5A-10圖之上述技術可用於附接任何數量的單獨的保護基板410至相同的中介層120.1或WS 120；不同的保護基板410可附接至基板120.1或120的相同側，其中不同的晶粒在相同或不同的保護基板410的不同空腔中。其他保護基板410可附接至基板120.1或120的對立側。一些晶粒可不具有保護基板410來保護它們。每一基板120.1S或410S可為晶圓，且兩個基板在給定的組件504中可為相同的尺寸；但是相同組件中也可能有不同的尺寸。
晶粒也可在相同的空腔中堆疊於彼此之上(參見第11圖，繪示如同第6圖的相同製造階段中的結構)，其中每一堆疊僅頂部晶粒實體接觸於對應的空腔的頂表面。每一堆疊中的晶粒可具有它們各自的電路透過其接觸墊1110C與各自的連接140(其可為上述的任何類型)而互連。在第11圖中，基板120.1S、410S藉由腿部410L上的黏合劑610接合在一起，如同第6圖中，但是也可使用上述的其他接合方法。堆疊的晶粒也可用於上述的其他變化型，例如，當保護基板直接接合至PWS時。
在一些實施例中，基板410S具有電路，可能連接至晶粒及/或中介層120.1S或PWS中的電路。參見第12圖，結構1210可連接至基板410S的頂部晶粒；每一結構1210包含基板410S中的接觸墊、頂部晶粒110上的對應接觸墊、以及接合兩接觸墊至彼此的連接(例如，焊料或上述的任何其 他類型)。在第12圖中，封裝150底部填充且完全圍繞每一晶粒，接觸於空腔的頂表面。如同上述，封裝及/或底部填充為選擇性的。
本發明不限於上述的實施例。例如，通孔224可在RDL之後形成，並且可通過一或兩個RDL而蝕刻。
一些實施例提供一種製品，包含：一第一基板(例如，120.1或120)，其包含一或更多個第一接觸墊(例如，頂部墊120.1C.T)；一或更多個晶粒，其附接至該第一基板，每一晶粒包含一半導體積體電路，該半導體積體電路包含一或更多個接觸墊係各自附接至一個別的第一接觸墊；一第二基板(例如，410或410S)，其包含一或更多個空腔，該第二基板係附接至該第一基板，其中每一晶粒的至少部分係位於該第二基板中的一對應空腔中，該第二基板包含一表面區域(例如，腿部410L的表面)係位於該等空腔之外並且附接至該第一基板；其中至少在該結構可電性操作的一些溫度時，至少一晶粒符合狀況(A)與(B)的一或兩者：(A)該晶粒實體接觸於該對應空腔的一表面；(B)該晶粒藉由實體接觸於該晶粒與該對應空腔的該表面之固體材料(例如，封裝或接合層)而分隔於該對應空腔的該表面。
在一些實施例中，在每一空腔係位於該第二基板的一底表面中之一側視中(例如，如同第5C或5E.1圖中)，該第二基板的該表面區域橫向圍繞每一空腔(例如，如同第5E.2圖中)。
在一些實施例中，該至少一晶粒附接至該對應空腔的該表面。
在一些實施例中，該至少一晶粒並未附接至該對應空腔的該表面。
在一些實施例中，該一或更多個第一接觸墊位於該第一基板的一第一側；該第一基板在相對於該第一側的一第二側包含一或更多個第二接觸墊(例如，在中介層底部處的接觸墊120.1C.B)；及該第一基板包含一或更多個導電路徑，該一或更多個導電路徑通過該第一基板(例如，金屬化的通孔224)並且電連接至少一第一接觸墊至至少一第二接觸墊。
在一些實施例中，該等狀況(A)與(B)的至少一者在室溫時符合。
在一些實施例中，該至少一晶粒處於來自該第二基板的壓力之下。
在一些實施例中，該壓力在室溫時不超過200MPa。在一些實施例中，該壓力大於大氣壓力(1巴(bar)，亦即，105Pa)，並且可在1巴至200MPa的範圍或此範圍的任何子範圍。該壓力也可高於或低於此範圍。
一些實施例提供一種用於製造一電性功能的製品之方法，該方法包含：獲得一第一基板(例如，120.1)，其包含一第一側與在該第 一側的一或更多個第一接觸墊；附接一或更多個晶粒至該第一基板，每一晶粒包含一半導體積體電路，該半導體積體電路包含一或更多個接觸墊係各自附接至一個別的第一接觸墊；獲得一第二基板(例如，410)，其包含一或更多個空腔；附接該第二基板至該第一基板，其中每一晶粒的至少部分係位於該第二基板中的一對應空腔中，該第二基板包含一表面區域(例如，腿部410L的底部區域)係位於該等空腔之外並且附接至該第一基板；其中至少在該結構可電性操作的一些溫度時，至少一晶粒符合狀況(A)與(B)的一或兩者：(A)該晶粒實體接觸於該對應空腔的一表面；(B)該晶粒藉由實體接觸於該晶粒與該對應空腔的該表面之固體材料而分隔於該對應空腔的該表面。
在一些實施例中，在每一空腔係位於該第二基板的一底表面中之一側視中，該第二基板的該表面區域橫向圍繞每一空腔。
在一些實施例中，該至少一晶粒附接至該對應空腔的該表面。
在一些實施例中，該至少一晶粒並未附接至該對應空腔的該表面。
在一些實施例中，該一或更多個第一接觸墊位於該第一基板的一第一側；該第一基板在相對於該第一側的一第二側包含一或更多個 第二接觸墊；及該第一基板包含一或更多個導電路徑，該一或更多個導電路徑通過該第一基板並且電連接至少一第一接觸墊至至少一第二接觸墊。
在一些實施例中，該等狀況(A)與(B)的至少一者在室溫時符合。
在一些實施例中，當該第一基板附接至該第二基板時，該至少一晶粒處於來自該第二基板的壓力之下。
在一些實施例中，該壓力在室溫時不超過200MPa。
在一些實施例中，該一或更多個晶粒為複數個晶粒，且該方法另包含在附接該第一基板至該第二基板之前，研磨在該晶粒的一第一側的一固體表面，該晶粒的該第一側為相對於每一晶粒的一或更多個接觸墊之一側，該固體表面為該晶粒的一表面或形成於該晶粒上的一封裝的一表面。
在一些實施例中，該固體表面為該封裝包含一環氧樹脂的一表面。
一些實施例提供一種製品，包含：一第一基板，其包含一或更多個第一接觸墊；一或更多個晶粒，其附接至該第一基板，每一晶粒包含一半導體積體電路，該半導體積體電路包含一或更多個接觸墊係各自附接至一個別的第一接觸墊；一第二基板，其包含一或更多個空腔，該第二基板係附接至該第一基板，其中每一晶粒的至少部分係位於該第二基板中的一對應空腔 中，該第二基板包含一表面區域係位於該等空腔之外並且附接至該第一基板；其中至少在該結構可電性操作的一些溫度時，至少一晶粒係處於來自該第二基板的壓力之下。
在一些實施例中，該壓力在室溫時不超過200MPa。
在一些實施例中，在每一空腔係位於該第二基板的一底表面中之一側視中，該第二基板的該表面區域橫向圍繞每一空腔。
在一些實施例中，該至少一晶粒附接至該對應空腔的該表面。
在一些實施例中，其中該至少一晶粒並未附接至該對應空腔的該表面。
在一些實施例中，其中該一或更多個第一接觸墊位於該第一基板的一第一側；該第一基板在相對於該第一側的一第二側包含一或更多個第二接觸墊；及該第一基板包含一或更多個導電路徑，該一或更多個導電路徑通過該第一基板並且電連接至少一第一接觸墊至至少一第二接觸墊。
其他實施例與變化都在本發明的範圍內，如同所附申請專利範圍所界定的。
320‧‧‧光阻
PR 320‧‧‧光阻
310‧‧‧層
120.1S‧‧‧基板

Claims (20)

  1. 一種空腔基板保護之積體電路，包含：(a)一結構，包含：一第一基板(Substrate)，包含一或更多個第一接觸墊；及一或更多個晶粒(Dies)，其附接至該第一基板，每一晶粒包含一半導體積體電路，該半導體積體電路包含之一或更多個接觸墊係各自附接至一個別的第一接觸墊；其中該結構包含一第一材料的一區域(Region)；(b)一第二基板，其包含一或更多個空腔(Cavities)在該第二基板之一底部中，該第二基板的一整個底表面係由一第二材料製成，該第二基板係附接至該結構，其中每一晶粒的至少部分係位於該第二基板中的一對應空腔中；其中該區域在該第二基板之下，且在頂視圖中，該區域可達該第二基板的一外部橫向邊界並且也可達到該一或更多個晶粒的至少一者；其中該第一材料係相同或不相同於該第二材料，並且具有實質上與該第二材料相同的熱膨脹係數(CTE)；其中該區域直接結合至該第二基板的該底表面，以實體接觸於該第二基板的該底表面；其中在該一或更多個空腔的至少一第一空腔裡，每一晶粒係由一固體的密封劑從上方封裝，該密封劑係實體接觸該第一空腔之一表面，但是不附接於該第一空腔的該表面之任何部分。
  2. 如申請專利範圍第1項之空腔基板保護之積體電路，其中該第二基板的該底表面包含附接至該結構的一表面區域，且該表面區域橫向圍繞每一空腔。
  3. 如申請專利範圍第1項之空腔基板保護之積體電路，其中：該第一基板包含在該第一基板的一底部側處的一或更多個第二接觸墊；及該第一基板包含一或更多個導電路徑，該一或更多個導電路徑通過該第一基板，並且電連接至少一第一接觸墊到至少一第二接觸墊。
  4. 如申請專利範圍第1項之空腔基板保護之積體電路，其中對至少一空腔而言，該空腔中的每一晶粒的熱膨脹係數(CTE)實質上與該第一及第二材料相同。
  5. 如申請專利範圍第1項之空腔基板保護之積體電路，其中該整個第二基板係由該第二材料製成。
  6. 如申請專利範圍第1項之空腔基板保護之積體電路，其中該第一與第二材料的至少一者為半導體。
  7. 如申請專利範圍第1項之空腔基板保護之積體電路，另包含一密封劑，該密封劑覆蓋且實體接觸於每一晶粒，該密封劑係一模製化合物(Molding Compound)，其中該第一與第二材料皆非一模製化合物。
  8. 如申請專利範圍第1項之空腔基板保護之積體電路，其中該第一區域為該第一基板的部分。
  9. 如申請專利範圍第1項之空腔基板保護之積體電路，其中除了每一空腔的一位置之外，該第二基板具有一第一厚度，該第二基板在每一空腔的該位置處較薄於該第一厚度。
  10. 如申請專利範圍第1項之空腔基板保護之積體電路，其中該第二基板在每一空腔之上比不在該一或更多個空腔的任一者之上的一位置處更薄。
  11. 如申請專利範圍第1項之空腔基板保護之積體電路，其中至少在該結構可電性操作的一些溫度時，至少一晶粒符合狀況(A)與(B)的一或兩者：(A)該晶粒實體接觸於該對應空腔的一表面；(B)該晶粒藉由實體接觸於該晶粒與該對應空腔的該表面之固體材料而分隔於該對應空腔的該表面。
  12. 如申請專利範圍第11項之空腔基板保護之積體電路，其中該至少一晶粒係附接至該對應空腔的該表面。
  13. 如申請專利範圍第11項之空腔基板保護之積體電路，其中該至少一晶粒 並未附接至該對應空腔的該表面。
  14. 如申請專利範圍第11項之空腔基板保護之積體電路，其中該狀況(A)與(B)的至少一者在室溫時符合。
  15. 一種空腔基板保護之積體電路，包含：(a)一結構，包含：一第一基板(Substrate)，包含一或更多個第一接觸墊；及一或更多個晶粒(Dies)，其附接至該第一基板，每一晶粒包含一半導體積體電路，該半導體積體電路包含之一或更多個接觸墊係各自附接至一個別的第一接觸墊；其中該結構包含一預定材料的一區域；(b)一第二基板，其包含一或更多個空腔(Cavities)在該該第二基板之一底部中，該第二基板的一整個底表面係由該預定材料製成，該第二基板係附接至該結構，其中每一晶粒的至少部分係位於該第二基板中的一對應空腔中；其中該區域在該第二基板之下，且在頂視圖中，該區域到達該第二基板的一外部橫向邊界並且也到達該一或更多個晶粒的至少一者；其中該區域直接結合至該第二基板的該底表面，以實體接觸於該第二基板的該底表面；其中在該一或更多個空腔的至少一第一空腔中，針對至少部分位於該第一空腔中的至少一晶粒，該晶粒附接至該第一空腔的一頂表面，而無一 模製化合物在該晶粒與該第一空腔的該頂表面之間。
  16. 如申請專利範圍第15項之空腔基板保護之積體電路，其中至少在該結構可電性操作的一些溫度時，至少一晶粒符合狀況(A)與(B)的一或兩者：(A)該晶粒實體接觸於該對應空腔的一表面；(B)該晶粒藉由實體接觸於該晶粒與該對應空腔的該表面之固體材料而分隔於該對應空腔的該表面。
  17. 如申請專利範圍第15項之空腔基板保護之積體電路，其中該區域為該第一基板的部分。
  18. 一種空腔基板保護之積體電路，包含：(a)一第一基板(Substrate)，包含：一第一主體，由一第一材料製成；一或更多個導電通孔(Conductive Vias)，每一導電通孔通過在該第一主體的一頂表面與一底表面之間的該第一主體；一再分佈層(Redistribution Layer)，其包含一或更多個導電線與並非該第一材料的介電質；及一或更多個第一接觸墊，其在該再分佈層的一頂部，並且間隔於該第一主體，該一或更多個導電線互連該一或更多個導電通孔的一或更多者與該一或更多個第一接觸墊的一或更多者；(b)一或更多個晶粒(Dies)，其附接至該第一基板，每一晶粒包含一半 導體積體電路，該半導體積體電路包含之一或更多個接觸墊係各自附接至一個別的第一接觸墊；(c)一第二基板，其包含一第二主體，該第二主體係由與該第一材料相同或不同的一第二材料製成，該第二基板包含一或更多個空腔(Cavities)在該底部中，每一空腔延伸至該第二主體中，該第二主體在每一空腔上的地方較薄，不在該一或更多個空腔的任一者之上的地方則較厚，該第二基板包含一底表面，該底表面包含之一區域係位於該一或更多個空腔的外部，並且直接結合至該再分佈層的一頂表面，以實體接觸於該再分佈層的該頂表面；其中該第一材料之熱膨脹係數(CTE)與該第二材料實質上相同；其中在該一或更多個空腔的至少一第一空腔中，針對至少部分位於該第一空腔中的至少一晶粒，該晶粒附接至該第一空腔的一頂表面，而無一模製化合物在該晶粒與該第一空腔的該頂表面之間。
  19. 如申請專利範圍第18項之空腔基板保護之積體電路，其中該第一材料相同於該第二材料。
  20. 如申請專利範圍第18項之空腔基板保護之積體電路，其中該第一與第二材料的至少一者為半導體。
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