TWI445104B - 半導體封裝結構及其製程 - Google Patents
半導體封裝結構及其製程 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 37
- 238000000034 method Methods 0.000 title claims description 36
- 235000012431 wafers Nutrition 0.000 claims description 155
- 239000010410 layer Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 34
- 239000008393 encapsulating agent Substances 0.000 claims description 29
- 238000005253 cladding Methods 0.000 claims description 17
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 238000012858 packaging process Methods 0.000 claims description 6
- 239000011247 coating layer Substances 0.000 claims description 5
- 239000011241 protective layer Substances 0.000 claims description 4
- 239000002335 surface treatment layer Substances 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 claims 1
- 239000003292 glue Substances 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000010909 process residue Substances 0.000 description 1
- 230000009979 protective mechanism Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Description
本發明是有關於一種半導體封裝技術,且特別是有關於一種堆疊式半導體元件封裝技術。
在現今的資訊社會中,電子產品的設計是朝向輕、薄、短、小的趨勢邁進,因此發展出諸如堆疊式半導體元件封裝等有利於微型化的封裝技術。
堆疊式半導體元件封裝是利用垂直堆疊的方式將多個半導體元件封裝於同一封裝結構中,如此可提升封裝密度以使封裝體小型化,且可利用立體堆疊的方式縮短半導體元件之間的訊號傳輸的路徑長度,以提升半導體元件之間訊號傳輸的速度,並可將不同功能的半導體元件組合於同一封裝體中。
習知一種堆疊式半導體元件封裝製程是將內埋有穿矽導孔(Through Silicon Via,TSV)的下層晶片覆晶接合在基板上並填入底膠保護,之後藉由研磨將下層晶片薄化並且將穿矽導孔的一端裸露出來,再進行上層晶片對下層晶片的堆疊接合。
前述製程為了避免下層晶片在研磨過程中因為基板表面與下層晶片的高低落差而與研磨輪撞擊導致受損,會在下層晶片接合至基板後在載具上全面塗佈一層保護膠,以在研磨時提供平坦表面。待穿矽導孔的一端被裸露之後,再以溶劑去除剩餘的保護膠。然而,此種方式會產生保護膠無法被完全移除,而有保護膠殘留,導致基板、下層晶片或封裝膠體表面污染的問題。
本發明提供一種半導體封裝結構及其製程,可避免習知製程在研磨後之保護膠殘留,導致基板、下層晶片或封裝膠體表面污染的問題。
本發明提供一種半導體封裝結構及其製程,適用於大尺寸之上層晶片與小尺寸之下層晶片的堆疊,可在上下層晶片接合後填入底膠,並可有效控制出膠量與溢膠問題。
為具體描述本發明之內容,在此提出一種半導體封裝製程,包括下列步驟。首先,配置一封裝母板於一載具上。封裝母板具有遠離載具的一承載面以及立於承載面上的一格柵牆(wall matrix)。格柵牆以及承載面共同定義出多個凹部。接著,分別接合多個第一晶片至封裝母板的所述多個凹部,其中每一第一晶片內具有多個穿矽導孔,並且,形成一第一底膠於每一第一晶片與相應的封裝母板之間。然後,形成一披覆層(overcoat layer)於載具上。披覆層覆蓋封裝母板以及第一晶片。接著,由載具上方來薄化披覆層以及格柵牆,直至位於格柵牆上方以及第一晶片上方的披覆層被完全移除。然後,暴露出每一第一晶片內的穿矽導孔的一端,並且分別接合多個第二晶片至所述多個第一晶片。接著,形成一第二底膠於每一第二晶片與相應的第一晶片之間。然後,分離載具與封裝母板,並且裁切封裝母板,以獲得多個封裝單元,其中封裝母板被裁切為多個封裝基材。
在本發明之一實施例中,第一底膠可在每一第一晶片與封裝母板接合前被預先配置在凹部內,或是在每一第一晶片與封裝母板接合後被填入每一第一晶片與封裝母板之間。
在本發明之一實施例中,第二底膠是在每一第二晶片與相應的第一晶片接合前被預先配置在第一晶片上,或是在每一第二晶片與相應的第一晶片接合後被填入每一第二晶片與相應的第一晶片之間。
在本發明之一實施例中,所述半導體封裝製程更包括在暴露出每一穿矽導孔的該端之後,對每一穿矽導孔的該端進行表面加工。
在本發明之一實施例中,所述半導體封裝製程更包括在覆晶接合第二晶片至第一晶片,並且形成第二底膠之後,形成一封裝膠體於封裝母板上。此封裝膠體覆蓋格柵牆與第二晶片,且在裁切封裝母板的同時,裁切封裝膠體。
本發明更提出一種半導體封裝結構,包括一封裝基材、一第一晶片、一第一底膠、一第二晶片以及一第二底膠。封裝基材具有一承載面。第一晶片接合至封裝基材。第一晶片內具有多個穿矽導孔。封裝基材的承載面上立有圍繞第一晶片的一側牆,且側牆的頂面與第一晶片的頂面實質上相互齊平。第一底膠配置於第一晶片與封裝基材之間。第二晶片配置於第一晶片上方,並接合至第一晶片的穿矽導孔。第二底膠配置於第二晶片與第一晶片之間。
在本發明之一實施例中,側牆與封裝基材的承載面共同定義出一凹部,且第一底膠填滿此凹部。
在本發明之一實施例中,第二晶片的尺寸大於第一晶片的尺寸。
在本發明之一實施例中,所述半導體封裝結構更包括一表面處理層,其配置於每一穿矽導孔突出第一晶片的一端上。
在本發明之一實施例中,所述半導體封裝結構更包括多個銲球,其配置於封裝基材的底部。
在本發明之一實施例中,所述半導體封裝結構更包括一封裝膠體,其配置於封裝基材上,且封裝膠體覆蓋側牆與第二晶片。
在本發明之一實施例中,封裝膠體的側面、側牆的側面以及封裝基材的側面實質上相互齊平。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
本發明在封裝母板上設置具有足夠厚度的柵格牆,其中此柵格牆可整合在現有基板製程中製作,例如,將封裝母板承載面上的銲罩層加厚,以形成此柵格牆,且柵格牆的厚度較佳被控制在大於薄化後的下層晶片的厚度。當下層晶片被接合至封裝母板,並且填入底膠之後,封裝母板上會全面塗佈一披覆層以利進行後續的研磨步驟。由於柵格牆的厚度大於薄化後的下層晶片的厚度,因此當研磨下層晶片至穿矽導孔的一端被裸露時,原先位於格柵牆上方以及下層晶片上方的披覆層已在研磨過程中被完全移除,因此不會有披覆層殘留及其衍生的污染問題,甚至可省去一道移除殘留披覆層的清洗步驟,從而可大幅提升製程良率與效率。
圖1A-1K依序繪示依據本發明之一實施例的一種半導體封裝製程。
首先,如圖1A所示,配置一封裝母板110於一載具10上。圖1A同時繪示了結構的上視圖與剖面圖。此封裝母板110例如是印刷電路板或其他類型的基板。載具10上具有黏著層12,用以固定封裝母板110。封裝母板110具有遠離載具10的一承載面110a以及立於承載面110a上的一格柵牆112。格柵牆112以及承載面110a共同定義出多個凹部114,每個凹部114對應進行後續晶片堆疊封裝步驟的區域,以分別形成封裝單元。
在此,格柵牆112例如是由封裝母板110上的銲罩層所構成,即,將封裝母板110的銲罩層加厚,以形成具有足夠厚度的格柵牆112。此時的格柵牆112的厚度在圖中以H1示之。當然,本實施例的格柵牆112也可以是藉由額外的製程被形成在封裝母板110的承載面110a上。然而,若採用封裝母板110原有的銲罩層來構成格柵牆112,則不需要增加額外的製程步驟,即不會增加製程的成本負擔。
接著,如圖1B所示,在每個凹部114內形成一第一底膠120,並且如圖1C所示,分別接合第一晶片130至每一凹部114,其中每一第一晶片130內具有多個穿矽導孔132,而第一晶片130例如是採熱壓方式透過多個凸塊134接合至封裝母板110。在第一晶片130與封裝母板110接合後,第一底膠120會填滿第一晶片130與封裝母板110之間的空隙,並且包覆凸塊134。
此外,前述圖1B與1C所繪示的兩個步驟的順序是可以交換的。請參考圖1B’以及1C’,本實施例也可以選擇先接合第一晶片130至每一凹部114(如圖1B’所示),再將第一底膠120填入到凹部114內(如圖1C’所示),使第一底膠120填滿第一晶片130與封裝母板110之間的空隙,並且包覆凸塊134。
在本實施例中,凹部132的尺寸除了必須能夠容納第一晶片130之外,也應保留出膠(即容納第一晶片130底部之多餘的第一底膠120)或供點膠(dispensing underfill)的寬度。換言之,可預先估算可能多餘之第一底膠120的量來調整第一晶片130與凹部114內壁的間隙,或是保留足以讓點膠機台的點膠頭(dispensing head)190將底膠材料填入凹部114的間隙。此間隙例如約為1.0毫米(mm)。
然後,如圖1D所示,形成一披覆層140於載具10上,此披覆層140覆蓋封裝母板110、格柵牆112以及第一晶片130。此披覆層140可提供平坦的表面,以利進行後續的研磨製程。
接著,如圖1E所示,由載具10上方來薄化披覆層140、格柵牆112以及第一晶片130,直到位於格柵牆112上方以及第一晶片130上方的披覆層140被完全移除,且第一晶片130內的穿矽導孔132的一端132a被暴露出來。此時,格柵牆112的頂面112a會與第一晶片130的頂面130a實質上相互齊平。被薄化後的第一晶片130的頂面130a距離承載面110a的高度在圖中以H2表示。在本實施例中,為了確保格柵牆112上方以及第一晶片130上方的披覆層140可在此步驟之後被完全移除,因此原先圖1A所形成的披覆層140的厚度H1必須大於被薄化後的第一晶片130的頂面130a的高度H2。
另外,本實施例在圖1B或1C’所填入的第一底膠120的量是可以被調整的。更詳細而言,若要在圖1E所示的步驟中,使第一底膠120上方的披覆層140也被完全移除,則如圖1C或1C’所示的第一底膠120的高度H3便需高於薄化後的第一晶片130的頂面130a的高度H2。如此,在進行圖1E所示的步驟之後,第一底膠120會填滿凹部114。
然後,如圖1F所示,可選擇性地在披覆層140、格柵牆112以及第一晶片130上全面覆蓋一保護層150。並且,如圖1G所示,對每一穿矽導孔132突出第一晶片130的該端132a進行表面加工(surface finish),以形成一表面處理層(surface finish layer)136。
之後,如圖1G所示,在第一晶片130上方形成一第二底膠160,並且如圖1H所示,分別接合第二晶片170至每一第一晶片130的穿矽導孔132。在第二晶片170與第一晶片130接合後,第二底膠160會填滿第一晶片130與第二晶片170之間的空隙。
此外,前述圖1G與1H所繪示的兩個步驟的順序是可以交換的。請參考圖1G’以及1H’,本實施例也可以選擇先接合第二晶片170至第一晶片130(如圖1G’所示),再藉由點膠機台的點膠頭190將底膠材料填入第一晶片130與第二晶片170之間的空隙,以形成第二底膠160。
在圖1H’所繪示的點膠製程中,由於第一晶片130旁具有相同高度的格柵牆112,因此有利於進行點膠製程。特別是,當如圖1H’所示,第二晶片170的尺寸大於第一晶片130的尺寸時,位於第一晶片130外圍的格柵牆112仍可提供完整的平面,因此底膠材料可以順利沿著格柵牆112與第二晶片170之間的空隙填入第一晶片130與第二晶片170之間。相較於習知的製程,本實施例的製程更適用於大尺寸之上層晶片(如第二晶片170)與小尺寸之下層晶片(如第一晶片130)的堆疊及點膠製程,並可有效控制出膠量與溢膠問題。
接著,如圖1I所示,本實施例可以選擇性地在封裝母板10上形成一封裝膠體180。此封裝膠體180覆蓋格柵牆112與第二晶片170。在本發明之其他實施例中,也選擇不形成封裝膠體180。
然後,如圖1J所示,分離載具10與封裝母板110,即,使封裝母板110的底部脫離載具10上的黏著層12。並且,如圖1K所示,裁切封裝母板110,以獲得相互獨立的多個封裝單元100,其中封裝母板110被裁切為多個封裝基材119,而格柵牆112被裁切為圍繞第一晶片130的側牆117。並且,在封裝基材119的底部形成多個銲球188。此外,若在前述步驟中選擇形成封裝膠體180,則在裁切封裝母板110時,亦同時裁切封裝膠體180,使得封裝膠體180的側面180a、側牆117的側面117a以及封裝基材119的側面119a實質上相互齊平。
經由前述製程可以得到如圖1J所示的封裝結構(即封裝單元)100,其中第二晶片170的尺寸大於第一晶片130的尺寸,且第二晶片170上覆蓋封裝膠體180。
圖2繪示本發明之另一實施例的一種封裝結構。如圖2所示,封裝結構200與前述實施例之封裝結構100類似,兩者主要的差異在於封裝結構200的第二晶片270的尺寸小於第一晶片230的尺寸。此外,封裝結構200同樣可採用前述實施例之製程步驟來製作,此處不再重複贅述。
圖3繪示本發明之又一實施例的一種封裝結構。如圖3所示,封裝結構300與前述實施例之封裝結構100類似,兩者主要的差異在於封裝結構300不具有封裝膠體。當採用前述實施例之製程步驟來製作本實施例的封裝結構300時,係省略了圖1I所示的形成封裝膠體180的步驟,而形成此不具有封裝膠體的封裝結構300。
圖4繪示本發明之再一實施例的一種封裝結構。如圖4所示,封裝結構400與前述實施例之封裝結構200類似,兩者主要的差異在於封裝結構400不具有封裝膠體。當採用前述實施例之製程步驟來製作本實施例的封裝結構400時,係省略了圖1I所示的形成封裝膠體180的步驟,而形成此不具有封裝膠體的封裝結構400。
綜上所述,本發明形成具有足夠厚度的柵格牆,且柵格牆的厚度較佳被控制在大於薄化後的下層晶片的厚度。當研磨下層晶片至穿矽導孔的一端被裸露時,原先位於格柵牆上方以及下層晶片上方的披覆層已在研磨過程中被完全移除,因此不會有披覆層殘留及其衍生的污染問題,甚至可省去一道移除殘留披覆層的清洗步驟,從而可大幅提升製程良率與效率。此外,本發明的半導體封裝製程適用於大尺寸之上層晶片與小尺寸之下層晶片的堆疊,可在上下層晶片接合後填入底膠,並可有效控制出膠量與溢膠問題。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10...載具
12...黏著層
100...封裝結構
110...封裝母板
110a...承載面
112...格柵牆
112a...格柵牆的頂面
114...凹部
117...側牆
117a...側牆的側面
119...封裝基材
119a...封裝基材的側面
120...第一底膠
130...第一晶片
130a...第一晶片的頂面
132...穿矽導孔
132a...穿矽導孔的一端
134...凸塊
136...表面處理層
140...披覆層
150...保護層
160...第二底膠
170...第二晶片
180...封裝膠體
180a...封裝膠體的側面
188...銲球
190...點膠頭
200...封裝結構
270...第二晶片
230...第一晶片
300...封裝結構
400...封裝結構
H1...格柵牆的厚度
H2...第一晶片的厚度
H3...第一底膠的高度
圖1A-1K依序繪示依據本發明之一實施例的一種半導體封裝製程。
圖2繪示本發明之另一實施例的一種封裝結構。
圖3繪示本發明之又一實施例的一種封裝結構。
圖4繪示本發明之再一實施例的一種封裝結構。
100...封裝結構
117...側牆
117a...側牆的側面
119...封裝基材
119a...封裝基材的側面
130...第一晶片
170...第二晶片
180...封裝膠體
180a...封裝膠體的側面
188...銲球
Claims (15)
- 一種半導體封裝製程,包括:配置一封裝母板於一載具上,該封裝母板具有遠離該載具的一承載面以及立於該承載面上的一格柵牆,該格柵牆以及該承載面共同定義出多個凹部;分別接合多個第一晶片至該封裝母板的該些凹部,每一第一晶片內具有多個穿矽導孔;形成一第一底膠於每一第一晶片與相應的該封裝母板之間;形成一披覆層於該載具上,該披覆層覆蓋該封裝母板的該格柵牆、該第一底膠以及該些第一晶片,以在該載具的上方提供一平坦表面;由該載具上方的該平坦表面來薄化該披覆層以及該格柵牆,直至位於該格柵牆上方以及該些第一晶片上方的該披覆層被完全移除;暴露出每一第一晶片內的該些穿矽導孔的一端;接合多個第二晶片至該些第一晶片;形成一第二底膠於每一第二晶片與相應的該第一晶片之間;分離該載具與該封裝母板;以及裁切該封裝母板,以獲得多個封裝單元,其中該封裝母板被裁切為多個封裝基材。
- 如申請專利範圍第1項所述之半導體封裝製程,其中該第一底膠是在每一第一晶片與該封裝母板接合前被預 先配置在該凹部內。
- 如申請專利範圍第1項所述之半導體封裝製程,其中該第一底膠是在每一第一晶片與該封裝母板接合後被填入每一第一晶片與該封裝母板之間。
- 如申請專利範圍第1項所述之半導體封裝製程,其中該第二底膠是在每一第二晶片與相應的該第一晶片接合前被預先配置在該第一晶片上。
- 如申請專利範圍第1項所述之半導體封裝製程,其中該第二底膠是在每一第二晶片與相應的該第一晶片接合後被填入每一第二晶片與相應的該第一晶片之間。
- 如申請專利範圍第1項所述之半導體封裝製程,其中在暴露出每一穿矽導孔的該端之後,更包括對每一穿矽導孔的該端進行表面加工。
- 如申請專利範圍第1項所述之半導體封裝製程,其中在覆晶接合該些第二晶片至該些第一晶片,並且形成該第二底膠之後,更包括形成一封裝膠體於該封裝母板上,該封裝膠體覆蓋該格柵牆與該些第二晶片,且在裁切該封裝母板的同時,裁切該封裝膠體。
- 如申請專利範圍第1項所述之半導體封裝製程,其中在薄化該披覆層以及該格柵牆之後,並且在暴露出每一第一晶片內的該些穿矽導孔的該端之前,更包括形成一保護層,該保護層覆蓋該些第一晶片、該格柵牆、該第一底膠以及該披覆層。
- 一種半導體封裝結構,包括: 一封裝基材,具有一承載面;一第一晶片,接合至該封裝基材,該第一晶片內具有多個穿矽導孔,該封裝基材的該承載面上立有圍繞該第一晶片的一側牆,且該側牆的頂面與該第一晶片的頂面實質上相互齊平;一第一底膠,配置於該第一晶片與該封裝基材之間;一第二晶片,配置於該第一晶片上方,並接合至該第一晶片的該些穿矽導孔;一第二底膠,配置於該第二晶片與該第一晶片之間;以及一保護層,配置於該第二底膠與該第一晶片之間,並且延伸覆蓋該第一底膠以及該側牆。
- 如申請專利範圍第9項所述之半導體封裝結構,其中該側牆與該封裝基材的該承載面共同定義出一凹部,且該第一底膠填滿該凹部。
- 如申請專利範圍第9項所述之半導體封裝結構,其中該第二晶片的尺寸大於該第一晶片的尺寸。
- 如申請專利範圍第9項所述之半導體封裝結構,更包括一表面處理層,配置於每一穿矽導孔突出該第一晶片的一端上。
- 如申請專利範圍第9項所述之半導體封裝結構,更包括:多個銲球,配置於該封裝基材的底部。
- 如申請專利範圍第9項所述之半導體封裝結構, 更包括:一封裝膠體,配置於該封裝基材上,且該封裝膠體覆蓋該側牆與該第二晶片。
- 如申請專利範圍第14項所述之半導體封裝結構,其中該封裝膠體的側面、該側牆的側面以及該封裝基材的側面實質上相互齊平。
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US9312214B2 (en) * | 2011-09-22 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages having polymer-containing substrates and methods of forming same |
US20150262902A1 (en) | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
US9355997B2 (en) | 2014-03-12 | 2016-05-31 | Invensas Corporation | Integrated circuit assemblies with reinforcement frames, and methods of manufacture |
US9165793B1 (en) | 2014-05-02 | 2015-10-20 | Invensas Corporation | Making electrical components in handle wafers of integrated circuit packages |
US9741649B2 (en) | 2014-06-04 | 2017-08-22 | Invensas Corporation | Integrated interposer solutions for 2D and 3D IC packaging |
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