TW201803039A - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法

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Publication number
TW201803039A
TW201803039A TW106110594A TW106110594A TW201803039A TW 201803039 A TW201803039 A TW 201803039A TW 106110594 A TW106110594 A TW 106110594A TW 106110594 A TW106110594 A TW 106110594A TW 201803039 A TW201803039 A TW 201803039A
Authority
TW
Taiwan
Prior art keywords
layer
die
semiconductor
dielectric material
dielectric
Prior art date
Application number
TW106110594A
Other languages
English (en)
Inventor
陳衿良
游濟陽
何冠霖
梁裕民
Original Assignee
台灣積體電路製造股份有限公司
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Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201803039A publication Critical patent/TW201803039A/zh

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Abstract

本揭露提供一種半導體裝置。半導體封裝裝置包含具有一第一表面的一第一半導體晶粒。該半導體封裝裝置亦包含環繞該第一半導體晶粒的介電材料，其中該介電材料包括與該第一表面實質齊平的一表面。該半導體封裝裝置另包含一覆蓋層，覆蓋該第一半導體晶粒的該第一表面與該介電材料的該表面。該覆蓋層與切割膠帶之間的黏著性小於該介電材料與該切割膠帶之間的黏著性。

Description

半導體結構及其製造方法
本揭露係關於一種半導體結構及其製造方法。
積體電路(integrated circuit，IC)發展的顯著趨勢係縮小IC組件的尺寸。這些集成改良本質上是二維的(2D)，其中IC係形成且互連於半導體晶圓的表面上。雖然微影的顯著改良對於2D IC形成有較大的影響，然而在二維中所能達成的密度仍有物理限制。同樣地，當在一晶片中放入更多裝置時，需要更複雜的設計與更高的成本。 在嘗試進一步增加電路密度過程中，已發展三維(3D)IC。例如，堆疊兩個晶粒；以及在各晶粒之間形成電連接。而後，該堆疊的晶粒藉由使用線接合與/或傳導墊而接合至載體基板。在另一範例中，發展基板上覆晶圓-晶圓上覆晶片(chip-on-wafer-on-substrate，CoWoS)的技術，其中晶粒電連接至晶圓基板，而後經由傳導凸塊而與另一基板進行接合操作。
本揭露的一些實施例提供一種半導體封裝裝置，包括一第一半導體晶粒，包括一第一表面；一介電層，環繞該第一半導體晶粒，該介電材料包括與該第一表面實質齊平的一表面；以及一覆蓋層，覆蓋該第一半導體晶粒的該第一表面與該介電材料的該表面，其中該覆蓋層與一切割膠帶之間的黏著性小於該介電材料與該切割膠帶之間的黏著性。
本揭露提供了數個不同的實施方法或實施例，可用於實現本發明的不同特徵。為簡化說明起見，本揭露也同時描述了特定零組件與佈置的範例。請注意提供這些特定範例的目的僅在於示範，而非予以任何限制。舉例而言，在以下說明第一特徵如何在第二特徵上或上方的敘述中，可能會包括某些實施例，其中第一特徵與第二特徵為直接接觸，而敘述中也可能包括其他不同實施例，其中第一特徵與第二特徵中間另有其他特徵，以致於第一特徵與第二特徵並不直接接觸。此外，本揭露中的各種範例可能使用重複的參考數字和/或文字註記，以使文件更加簡單化和明確，這些重複的參考數字與註記不代表不同的實施例與/或配置之間的關聯性。 另外，本揭露在使用與空間相關的敘述詞彙，如“在...之下”，“低”，“下”，“上方”，“之上”，“下”，“頂”，“底”和類似詞彙時，為便於敘述，其用法均在於描述圖示中一個元件或特徵與另一個（或多個）元件或特徵的相對關係。除了圖示中所顯示的角度方向外，這些空間相對詞彙也用來描述該裝置在使用中以及操作時的可能角度和方向。該裝置的角度方向可能不同（旋轉90度或其它方位），而在本揭露所使用的這些空間相關敘述可以同樣方式加以解釋。 本揭露提供半導體裝置及其製造方法，其中覆蓋層形成於晶圓上覆晶片(chip-on-wafer (CoW)晶粒並且作為CoW晶粒與切割膠帶之間的界面。覆蓋層可協助弱化切割膠帶與CoW晶粒之間的附著，以利於晶粒自切割膠帶的分離操作。本揭露說明形成半導體封裝裝置的中間階段。亦討論一些實施例的一些變異。在本揭露中，相同的元件符號用以表相同元件。 圖1至圖7係根據本揭露之不同實施例說明製造半導體封裝裝置之中間階段的剖面示意圖。在一些實施例中，圖1至圖7係關於CoW製程形成CoW晶粒之製造製程中間階段的剖面示意圖。 參閱圖1，繪示用於CoW製程的晶圓131與一些半導體晶粒130。該等晶粒130配置為群組，並且各組可配置為相同半導體晶粒的陣列。或者，一組內的該等晶粒130可為不同結構與功能之不同半導體晶粒的聚集。例如，各組晶粒130可包括具有可編程的記憶體儲存之微處理器裝置，例如快閃記憶體或EEPROM裝置，或是具有專用處理器的微處理器，例如基帶收發器、圖形處理器、快取記憶體裝置、記憶體管理裝置、以及用於感測器應用之類比數位轉換器。 各個晶粒130包括基鈑(或稱為晶粒基板)132。基板132包含半導體材料，例如矽。在一實施例中，基板132可包含其他半導體材料，例如矽鍺、碳化矽、砷化鎵、或類似物。基板132可為p型半導體基板(受體型)或n型半導體基板(供體型)。或者，基板132包含另一元素半導體，例如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、與/或銻化銦；或合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、與/或GaInAsP；或其組合。在另一替代中，晶粒基板132為絕緣體上半導體(semiconductor-on-insulator，SOI)。在其他替代中，基板132可包含摻雜的外延層(doped epi layer)、梯度半導體層、與/或位於不同形式之另一半導體層上方的半導體層，例如矽鍺層上的矽層。 可在晶粒基板132中，形成各種組件，例如主動裝置、被動組件、傳導部、或絕絕材料。此外，各個晶粒130包括一或多個連接終端134，稱為傳導墊或接墊。晶粒基板132的包埋組件係經由連接終端134而電耦合至外部電路或裝置。 在連接終端134上沉積介電層136或鈍化層。可藉由合適製成，例如化學氣相沉積(chemical vapor deposition，CVD)、物理氣相沉積(physical vapor deposition，PVD)、原子層沉積(atomic layer deposition，ALD)、或類似者，初始形成毯層，而提供介電層136。而後，在光阻(未分別繪示)上進行微影與蝕刻製程，以暴露連接終端134，因而於其上形成個別開口。移除介電材料之不想要的部分，造成介電層136成形。可藉由各種介電材料形成介電層136，並且介電層136可為例如氧化物(例如Ge氧化物)、氮氧化物(例如GaP氮氧化物)、二氧化矽(SiO2 )、含氮的氧化物(例如含氮的SiO2 )、摻雜氮的氧化物(例如摻雜N2 的SiO2 )、氮氧化矽(Six Oy Nz )、聚合物材料、以及類似物。 再者，傳導層沉積於連接終端134上，並且被圖案化以形成凸塊下金屬層(under bump metallization，UBM)138，其亦稱為球限金屬層(ball-limiting metallurgy，BLM)。UBM 138定義在回焊操作之後形成於其上之連接器的尺寸，例如傳導凸塊，並且與該連接器反應，因而對於該連接器與下方結構之間提供有效的黏著(adhesion)與阻障。在本揭露中，UBM 138在連接終端134與連接器140之間提供額外的黏著。在一些實施例中，UBM 138可增加連接器140的可焊性(solderability)。例如，UBM 138的材料包含鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)、銅(Cu)、銅合金、鎳(Ni)、錫(Sn)、金(Au)、或其組合。在一些實施例中，UBM 138包括具有不同傳導材料子層的層狀結構。 在形成UBM 138之後，形成連接器140。連接器140由傳導材料形成，例如錫、銅、鎳或類似物。連接器140可實施為傳導凸塊，例如微凸塊或受控的塌陷晶片連接(controlled collapse chip connection，C4)凸塊。藉由任何合適的操作，例如植球、網印操作中的焊膏、無電或電鍍方式、受控的塌陷晶片連接(C4)鍍製程或C4NP(C4新製程)焊料轉移，而形成連接器140。 晶圓131包括基板材料例如矽或其他合適的基板材料104，例如陶瓷、玻璃、塑膠、樹脂或環氧化合物。此外，晶圓131包含沿著垂直方向的貫穿基板通路(through substrate via，TSV)106，該垂直方向係垂直於晶圓131的表面。在一實施例中，TSV 106可自第一表面131A延伸至第二表面131B，其中若晶圓131被切割，則TSV 106亦被視為貫穿中介通路(through interposer via，TIV)。在一實施例中，晶圓131為中介晶圓(interposer wafer)，對於相鄰晶粒或裝置提供互連特徵。在晶圓131為中介晶圓的實施例中，除了TSV 106，可無主動或被動裝置形成於該晶圓中。 在一實施例中，載體102係配置於晶圓131之下。在後續製程中，載體102握持且支撐晶圓131，並且在後續操作中，載體102可被薄化、移除、或自晶圓131釋出。載體102係由任何可剝除的或容易移除的材料形成，例如薄膜、膠帶、液體黏著物、以及類似物。 在晶圓131的第二表面131B上方，形成重佈層(redistribution layer (RDL)120。RDL 120包含圖案化的導體108與117，以及至少一介電層112。介電層112用於將傳導特徵108與117電性絕緣。介電層112係由介電材料製成，包含例如氧化物或氮化物。圖案化的導體108與117經配置成為橫向延伸的傳導線108與垂直延伸的傳導通路117，共同組成晶粒130之重新佈線的傳導布局(re-routed conductive layout)。再者，該等傳導線108耦合該等TSV106，以產生電連接。該等傳導線108與117由適合用於互連的傳導材料製成，例如銅、銀、鋁、鎢、其組合、或類似物。由於晶粒130被允許經由RDL 120而彼此通訊，因而藉由使用RDL 120，改變晶粒130或傳導凸塊圖案而不修飾系統板(system board)。因此，RDL 120可改變新晶粒的佈局或新凸塊圖案用於特定功能。此變化性節省成本並且允許晶粒或晶粒供應商的任何變化。在本實施例中，繪示一層傳導線108，僅作為說明之用。RDL 120的變化與修飾仍在本揭露的範圍內，例如經由傳導通路117互連的多層傳導線以及形成於其間的多層介電材料112。 另一傳導層形成於RDL 120中，而後被圖案化以形成傳導墊115。傳導墊115係由傳導材料製成，例如鋁、銅、銅合金、或鎳。而後，在傳導墊115上形成介電層114，可作為RDL 120之保護層。例如，可藉由化學氣相沉積(CVD)、原子層沉積(ALD)、旋塗、蒸鍍、或類似者，形成介電層114。而後，進行微影與蝕刻製程，以暴露傳導墊115，因而形成多個開口。傳導層配置於傳導墊117上，而後被圖案化以形成UBM 119。UBM 119接觸傳導墊115並且受到介電層114支撐。 連接器118形成於RDL 120的UBM 119上。連接器118係用於電耦合外部裝置與晶圓131，該外部裝置例如晶粒130。連接器118可實施為傳導凸塊，例如微凸塊或受控的塌陷晶片連接(C4)凸塊。連接器118係由傳導材料形成，例如錫、銅、鎳、或類似物。可藉由蒸鍍、電鍍製程、植球、網印操作中的焊膏、無電或電鍍方式、C4鍍製程或C4NP焊料轉移，形成連接器118。一旦形成，連接器118對準個別晶粒130之對應的連接器140，以輔助後續的接合操作。 參閱圖2，該等晶粒130經由個別連接器142而接合至晶圓131。可於各種製程中，進行接合操作。例如，使用熱回焊製程，使得圖1中的該等連接器140與118變軟。在冷卻期間之後，連接器140與118熔化，因而再晶粒130與晶圓131之間形成合併的連接器142。該等連接器142對於晶粒130與晶圓131之間提供附接與電連接。在一些實施例中，連接器142可為傳導凸塊，例如微凸塊或受控的塌陷晶片連接(C4)凸塊。在一些實施例中，連接器142形成為球形或是非球形。 在形成連接器142之後，底膠填充層150填充晶粒130與晶圓131之間的一些空間。在一些實施例中，底膠填充層150填充連接器142之間的間隙。在一些實施例中，底膠填充層150覆蓋RDL 120的上表面。在一些實施例中，底膠填充層150包括側壁，與晶粒130的側壁交會。底膠填充層150提供柔順的材料環繞該等連接器142以及提供晶粒130與晶圓131之間的黏著。再者，底膠填充層150在熱循環過程中提供應力釋放，以防止連接器142與晶粒130破裂。 在一些例子中，底膠填充層150包括介電材料，並且可選自於囊封或成形材料。在一些實施例中，底膠填充層150包含例如柔順的環氧化物(compliant epoxy)，其在室溫為液體，並且特別是在溫度升高時具有快速硬化時間且在分配期間具有低黏性。在一些實施例中，使用注射器或針以分配底膠填充層150的介電材料。 在一些實施例中，底膠填充層150包含與RDL 120相鄰的第一表面，大於與晶粒130相鄰的第二表面。在一些實施例中，底膠填充層150包含錐形側壁。在一實施例中，底膠填充層150可包含自介電層114向上傾斜至介電層136的側壁，因而密封晶粒130與晶圓131之間的間隙。 參閱圖2，介電材料152形成於晶圓131的RDL 120上方並且環繞該等晶粒130。所形成的介電材料152可作為環繞該等晶粒130、該等連接器142或RDL 120的囊封層。根據一些實施例，介電材料152覆蓋介電層136與晶粒130的側壁。根據一些實施例，介電材料152覆蓋底膠填充層150的側壁。在一些實施例中，介電材料152環繞各個晶粒130的周圍。 介電材料152可為模塑料樹脂，例如聚亞醯胺、聚苯硫醚(polyphenylene sulphide，PPS)、聚二醚酮(polyether ether ketone，PEEK)、聚醚碸(polyethersulfone，PES)、抗熱結晶樹脂、或其組合。在一些實施例中，可用各種介電材料形成介電材料152，例如可為氧化物(例如Ge氧化物)、氮氧化物(例如GaP氮氧化物)、二氧化矽(SiO2 )、含氮的氧化物(例如含氮的SiO2 )、摻雜氮的氧化物(例如摻雜N2 的SiO2 )、氮氧化矽(Six Oy Nz )、以及類似物。在一些實施例中，介電材料152可為保護性材料，例如聚苯并噁唑(polybenzoxazole，PBO)、聚亞醯胺(polyimide，PI)、苯并環丁烯(benzocyclobutene (BCB)、氧化矽、氮化矽、氮氧化矽、或任何其他合適的保護性材料。 在一些例子中，在一操作中移除介電材料152的一部分，該操作亦稱為背面研磨製程。將介電材料152的上表面152A平坦化，其中藉由平坦化製程研磨過多的成形材料，例如化學機械拋光(chemical mechanical polishing，CMP)或其他機械製程。因此，暴露各個晶粒130的上表面130A。在一些實施例中，上表面130A係與上表面152A齊平。在一些實施例中，上表面130A與上表面152A交會。換言之，上表面130A與152A係以共平面方式配置。 參閱圖3，在介電材料152與該等晶粒130上方，形成覆蓋層144。在一些實施例中，覆蓋層144覆蓋由晶粒130的上表面130A與介電材料152的上表面152A組成的表面。可形成覆蓋層144以完全覆蓋該等晶粒130的各個上表面130A。在一實施例中，覆蓋層144持續延伸於晶粒130之群組上方。因此，覆蓋層144覆蓋晶粒130之間的上表面。覆蓋層144局部接觸該等晶粒130並且局部接觸介電層152。 覆蓋層144可由均質材料形成。在一些實施例中，覆蓋層144由傳導材料形成，例如Ti、Cu、Ni、Al、Ag、其組合、其合金、或其他合適的材料。在一些實施例中，覆蓋層144係由金屬基底或焊料基底材料形成，例如氧化鋁、氮化硼、氮化鋁、或類似者。可藉由使用各種技術，例如高密度離子化金屬電漿(ionized metal plasma，IMP)沉積、高密度電感耦合電漿(inductively coupled plasma (ICP) deposition)沉積、濺鍍、PVD、CVD、低壓化學氣相沉積(low-pressure chemical vapor deposition，LPCVD)、電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition，PECVD)、電化學鍍製程、無電鍍製程、以及類似者，形成覆蓋層144。 在一實施例中，覆蓋層144為薄膜，並且作為異表面(hetero-surface)與上方組件之間的界面層。該異表面可包含晶粒130的上表面130A以及介電層152的上表面152A。在一實施例中，覆蓋層144可不對於該等晶粒130提供任何電連接，因而可與該等晶粒130或介電材料152電性絕緣。在一些實施例中，所形成的覆蓋層144厚度可足以輔助黏著至該等晶粒130或介電材料152。在一些實施例中，所形成的覆蓋層144厚度約0.05微米至約3.0微米。在一些實施例中，所形成的覆蓋層144厚度約0.1微米至約1.0微米。在一些實施例中，所形成的覆蓋層144厚度約0.1微米至約0.5微米。 在一實施例中，覆蓋層144可另有利於該等晶粒130的散熱。在覆蓋層144接觸該等晶粒130的實施例中，該等晶粒130產生的熱可經由覆蓋層144而有效散出。在一些實施例中，覆蓋層144的熱傳導性大於約100 Watt/m*K。在一些實施例中，覆蓋層144的熱傳導性大於約400 Watt/m*K。在一些實施例中，覆蓋層144的熱傳導性為約100 Watt/m*K與約400 Watt/m*K之間。 接著，如圖4所示，圖3的接合結構翻轉，並且提供另一載體160用於支撐該接合結構。此外，自晶圓131釋出或移除圖3的載體102。在該等TSV 106包埋在晶圓131之基板材料104中的一些實施例中，可進行凹陷或薄化操作，以自晶圓131的表面暴露該等TSV 106。該薄化操作可包含蝕刻操作，例如乾式蝕刻或濕式蝕刻操作、研磨、或CMP製程。 參閱圖5，於個別暴露的TSV 106上方形成多個傳導墊162。在一些實施例中，傳導墊162由傳導材料形成，例如鋁、銅、鎢、或類似物。可使用例如CVD或PVD製程，形成傳導墊162，然而亦可使用其他合適的材料與方法。關於一例示操作，可藉由初始形成傳導層於晶圓131之暴露的表面131A上方，而進行傳導墊162的形成。而後，於該傳導層上方，形成或配置圖案化光阻(未分別繪示)。藉由以光阻為圖案化遮罩，移除傳導層之不想要有的部分而形成該等傳導墊162。此外，在傳導墊162形成之後，可藉由使用蝕刻操作，進行移除操作，用於移除該圖案化的光阻。 在圖6中，可在該等傳導墊162上方，形成介電層164。在一些實施例中，介電層164被圖案化因而具有開口，以暴露該等傳導墊162。在一些實施例中，介電層164可形成為鈍化層。可藉由各種技術，例如CVD、LPCVD、PECVD、濺鍍、與物理氣相沉積、熱成長、以及類似者，形成圖案化的介電層164。可用各種介電材料形成圖案化的介電層106，以及該圖案化的介電層106可為例如氧化物(例如Ge氧化物)、氮氧化物(例如GaP氮氧化物)、二氧化矽(SiO2 )、含氮的氧化物(例如含氮的SiO2 )、摻雜氮的氧化物(例如摻雜N2 的SiO2 )、氮氧化矽(Six Oy Nz )、以及類似物。 再者，在該等傳導墊162上方，形成數個連接器168。該等連接器168經由該等傳導墊162而電耦合該等TSV 106與外部組件或裝置。該等連接器168可為接點凸塊，例如受控的塌陷晶片連接(C4)凸塊、球柵陣列凸塊、或微凸塊。連接器168可包括傳導材料，例如錫、銅、鎢、金、銀、鎳、或類似物。根據一些實施例，UBM 166形成於個別介電層164與連接器168之間。UBM 166的材料與形成製程可類似於圖1所述與繪示之UBM，例如用於形成連接器140的UBM 138或是用於連接器118的UBM 119。 參閱圖7，自接合的半導體結構173，移除圖6的載體160。包括晶粒130與晶圓131之接合的半導體結構173，如圖7所示，可稱為CoW晶粒(例如晶粒173-1與173-2)，其可用於後續操作形成基板上CoW(CoW-on-substrate，CoWoS)封裝。 參考圖1至2與圖8至11，以下說明根據各種操作製造半導體封裝結構的另一實施例。在繪示剖面圖之不同圖式中，用於不同操作之相同的元件符號可代表相同元件。 參閱圖8，圖2所示之接合結構被翻轉，並且配置於另一載體161上方。一旦接合結構被放置，晶圓131被薄化因而暴露TSV 106，如圖9所示。在一實施例中，自晶圓131初始移除或釋放載體102，而後對於基板材料104進行凹陷操作。因此，自晶圓131暴露該等TSV 106的頂部。 在圖10中，該等傳導墊162、介電層164與UBM 166依序形成於彼此上方。本揭露所使用之傳導墊162、介電層164與UBM 166的材料與形成操作可與圖5至6所述與繪示之相同元件類似。 圖11係說明移除載體161的剖面示意圖。再者，晶粒173的接合結構被翻轉，而後放置於支撐件上方或是配置於腔室(未分別繪示)中。在一實施例中，可使用清理化學物質或去離子水(deionized，DI)水，進行一或多個清理操作。此外，於介電材料152與晶粒130上方，形成覆蓋層144。本實施例使用的覆蓋層144之材料與形成操作可類似於圖3所述與繪示之相同元件。在一實施例中，該等晶粒173可被再次翻轉，因而覆蓋層144可面對膠帶，稍後將說明該膠帶。 接著，CoW晶粒173係位於膠帶170上方，如圖12所示。在一些實施例中，膠帶170可為晶粒附接膜(die attach film，DAF)、乾膜或切割膠帶。膠帶170包括黏著材料，以握持且固定該等晶粒173。該等晶粒173經由覆蓋層144而附接至膠帶170。在一實施例中，膠帶170於覆蓋層144附接至該等晶粒173。接著，對於CoW晶粒173進行切割或單粒化操作。在一些實施例中，藉由使用切割刀169，進行切割操作。然而，可替代使用雷射，用於進行單粒化操作。因此，各個單粒化的CoW晶粒173包含晶粒130群組以及對應的分段晶圓131，其亦可稱為中介基板(interposer substrate)131。因此，單粒化的CoW晶粒173包括沿著對應中介基板131的多個晶粒130，並且可另包含其他元件，例如RDL 120、連接器142、傳導墊162等，如圖1至圖6所述與繪示。 參閱圖12，一旦完成單粒化操作，CoW晶粒173被切割且彼此分離。單粒化操作中使用的斷裂機構(breaking mechanism)可切割穿過晶圓131、介電層112與114、介電材料152、以及可能穿過膠帶170的深度。再者，該斷裂機構可切割穿過膠帶170與介電材料152之間的覆蓋層144。由於在單粒化操作之前，皆已形成介電層152與覆蓋層144，因而在同一斷裂作用過程中，形成個別CoW晶粒173之介電材料152的側壁與覆蓋層144的側壁。在一實施例中，關於個別的CoW晶粒173-1或173-2，介電材料152的側壁對準覆蓋層144的側壁。同樣地，關於個別的CoW晶粒173-1或173-2，在一實施例中，覆蓋層144的側壁對準RDL 120的側壁。在一實施例中，覆蓋層144的側壁對準中介基板131的側壁。 在圖13中，藉由使用分離工具，自膠帶170抬起個別CoW晶粒173(晶粒173-1或173-2)。在一些實施例中，取放工具可用於拾起個別CoW晶粒173，並且自膠帶170將其移除。如一例示實施例，可使用抽吸機構(suction mechanism)或推出銷(ejection pin)，以升起目標晶粒173。藉由脫離工具的協助，個別晶粒173的覆蓋層144可自膠帶170脫離。膠帶170(例如乾膜)與覆蓋層144之間的黏著性質決定CoW晶粒173的成功脫離可能性。在一些實施例中，覆蓋層144與膠帶170之間的表面能量經管理而被最佳化，以利於脫離製程。在一些實施例中，覆蓋層144與切割膠帶170之間的黏著性低於介電材料152與切割膠帶170之間的黏著性。 在一些實施例中，覆蓋層144的材料經選擇為不與膠帶170交聯。可在室溫或升高的溫度中，形成交聯。在一些實施例中，覆蓋層144的材料經選擇為與膠帶170的交聯小於介電材料152與膠帶170的交聯。 在現有的製造封裝結構製程程中，膠帶170直接接觸晶粒130的表面130A與介電層152的表面152A(亦即無覆蓋層144)。由於與不同材料的不同黏著力，膠帶170之整個接觸表面的黏著力可非均勻。例如，表面130A通常由矽基底材料製成，其黏著力(或釋放力)約為50 mN/20mm。鑑於上述，介電材料152與膠帶170之間所不希望有的黏著可能造成脫離失敗。相對地，包含例如鎳之覆蓋層可提供約20 mN/20mm的黏著力。因此，覆蓋層144的導入可在CoW晶粒與膠帶170之間提供均勻的低黏著力。覆蓋層144分隔介電材料152與膠帶170，以防止介電材料152與膠帶170之間的黏性。因此，可改良脫離製程。 在一實施例中，覆蓋層144與乾膜170之間的表面能量不同於介電材料152與乾膜170之間的表面能量。在一實施例中，覆蓋層144與乾膜170之間的表面能量小於介電材料152與乾膜170之間的表面能量。 參閱圖14，提供另一基板174。基板174包含半導體材料，例如矽。在一實施例中，基板174可包含其他半導體材料，例如矽鍺、碳化矽、砷化鎵、或類似物。在本實施例中，基板174為p型半導體基板(受體型)或n型半導體基板(供體型)。或者，基板174包含另一元素半導體，例如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、與/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP與/或GaInAsP；或其組合。在另一替代中，基板174為絕緣體上半導體(SOI)。在其他替代中，基板174可包含摻雜的外延層(doped epi layer)、梯度半導體層、與/或在不同型之另一半導體層上方的半導體層，例如在矽鍺層上的矽層。 此外，在基板174的頂表面上方形成一些傳導墊176。CoW晶粒173經由連接器168而電接合至基板173的傳導墊176。圖14的接合結構代表基板上CoW(CoWoS)封裝裝置。 參閱圖15，介電層178囊封CoWoS結構。在一實施例中，介電層178橫向環繞CoW晶粒173、連接器168與傳導墊176。在一些實施例中，介電材料178環繞且接觸覆蓋層144。在一些實施例中，介電材料178覆蓋覆蓋層144的側壁。在一實施例中，介電材料178包括一側壁，自基板174的頂表面174A延伸至覆蓋層144的上表面144A，該上表面144遠離晶粒130。 介電材料178可為底膠填充材料。或者，介電材料178可為模塑料樹脂，例如聚亞醯胺、PPS、PEEK、PES、抗熱結晶樹脂、或其組合。在一些實施例中，介電材料178可為氧化物(例如Ge氧化物)、氮氧化物(例如GaP氮氧化物)、二氧化矽(SiO2 )、含氮的氧化物(例如含氮的SiO2 )、摻雜氮的氧化物(例如摻雜N2 的SiO2 )、氮氧化矽(Six Oy Nz )、以及類似物。 在圖16中，熱界面材料(thermal interface material，TIM)180係位於覆蓋層144上方。在藉由介電材料178成形CoW晶粒173之後，可分配TIM 180。TIM 180可由熱傳導材料形成。例如，TIM 180由相變化材料形成，並且在晶粒130的正常工作溫度下加熱時，可變為類液相(quasi-liquid phase)。相對地，覆蓋層144的材料經選擇為例如晶粒130的工作溫度範圍下不會造成相變化。在一實施例中，TIM 180的熔化溫度小於覆蓋層144。 再者，在一實施例中，散熱器182位於TIM 180上方。TIM 180可夾在散熱器182與覆蓋層144之間。在一實施例中，當受熱與熔化時，TIM 180被允許流動於覆蓋層144、介電材料178、散熱器182或基板174所定義的空間186中。在一實施例中，空間186可朝向基板174的上表面174A延伸。在一些實施例中，散熱器182覆蓋CoW晶粒137、TIM 180、介電層178、以及基板174。使用散熱器182或TIM 180改良封裝的CoWoS晶粒185的熱效能並且降低晶粒130工作溫度。 在一些實施例中，連接器184形成於基板174的底表面174B上，表面174B遠離CoW晶粒173。連接器184可形成為微凸塊、受控的塌陷晶片凸塊或球柵陣列(BGA)凸塊，並且可連接至另一半導體晶粒、裝置、或印刷電路板。 本揭露提供一種半導體裝置。半導體封裝裝置包含具有第一表面的第一半導體晶粒。半導體封裝裝置亦包含環繞第一半導體晶粒的介電材料，其中該介電材料包括與該第一表面實質齊平的一表面。半導體封裝裝置另包含一覆蓋層，覆蓋該第一半導體晶粒的該第一表面以及該介電材料的該表面。該覆蓋層與切割膠帶之間的黏著性小於該介電材料與該切割膠帶之間的黏著性。 本揭露提供一種半導體封裝裝置。該半導體封裝裝置包括一半導體晶粒。該半導體封裝裝置另包含第一介電材料，該第一介電材料橫向環繞該半導體晶粒且包含遠離該半導體晶粒的一側壁。該半導體封裝裝置亦包含一覆蓋層，覆蓋該第一介電材料的上表面，其中該覆蓋層的側壁對準該第一介電材料的該側壁。該覆蓋層與切割膠帶之間的黏著性小於該介電材料與該切割膠帶之間的黏著性。 本揭露提供一種形成半導體封裝的方法，該方法包括提供一半導體晶粒；橫向囊封該半導體晶粒；形成一層於該半導體晶粒的上表面與該介電材料的上表面上，其中該覆蓋層與切割膠帶之間的黏著性小於該介電材料與該切割膠帶之間的黏著性；經由該層而附接該半導體晶粒至該切割膠帶，並且對於該半導體晶粒進行單粒化；以及自該膠帶移除單粒化的半導體晶粒。 前述內容概述一些實施方式的特徵，因而熟知此技藝之人士可更加理解本揭露之各方面。熟知此技藝之人士應理解可輕易使用本揭露作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本揭露揭示內容的精神與範圍，並且熟知此技藝之人士可進行各種變化、取代與替換，而不脫離本揭露之精神與範圍。
102‧‧‧載體
104‧‧‧基板材料
106‧‧‧貫穿基板通路
108‧‧‧傳導線
112‧‧‧介電層
114‧‧‧介電層
115‧‧‧傳導墊
117‧‧‧傳導通路
118‧‧‧連接器
119‧‧‧凸塊下金屬層
120‧‧‧重佈層
130‧‧‧晶粒
130A‧‧‧表面
131‧‧‧晶圓
131A‧‧‧第一表面
131B‧‧‧第二表面
132‧‧‧基板
134‧‧‧連接終端
136‧‧‧介電層
138‧‧‧凸塊下金屬層
140‧‧‧連接器
142‧‧‧連接器
144‧‧‧覆蓋層
150‧‧‧底膠填充層
152‧‧‧介電材料
152A‧‧‧上表面
160‧‧‧載體
161‧‧‧載體
162‧‧‧傳導墊
164‧‧‧介電層
166‧‧‧凸塊下金屬層
168‧‧‧連接器
170‧‧‧膠帶
173‧‧‧半導體結構
173-1‧‧‧晶粒
173-2‧‧‧晶粒
174‧‧‧基板
174A‧‧‧頂表面
176‧‧‧傳導墊
178‧‧‧介電層
180‧‧‧熱界面材料
182‧‧‧散熱器
184‧‧‧連接器
185‧‧‧CoWoS晶粒
186‧‧‧空間
為協助讀者達到最佳理解效果，建議在閱讀本揭露時同時參考附件圖示及其詳細文字敘述說明。請注意為遵循業界標準作法，本專利說明書中的圖式不一定按照正確的比例繪製。在某些圖式中，尺寸可能刻意放大或縮小，以協助讀者清楚了解其中的討論內容。 圖1至圖7係根據本揭露之不同實施例說明製造半導體封裝裝置之中間階段的剖面示意圖。 圖8至圖11係根據本揭露之不同實施例說明製造半導體封裝裝置之中間階段的剖面示意圖。 圖12至圖16係根據本揭露之不同實施例說明製造半導體封裝裝置之中間階段的剖面示意圖。
104‧‧‧基板材料
106‧‧‧貫穿基板通路
108‧‧‧傳導線
112‧‧‧介電層
114‧‧‧介電層
115‧‧‧傳導墊
117‧‧‧傳導通路
120‧‧‧重佈層
130‧‧‧晶粒
131‧‧‧晶圓
136‧‧‧介電層
138‧‧‧凸塊下金屬層
140‧‧‧連接器
150‧‧‧底膠填充層
152‧‧‧介電材料
162‧‧‧傳導墊
164‧‧‧介電層
166‧‧‧凸塊下金屬層
168‧‧‧連接器
173-1‧‧‧晶粒
173-2‧‧‧晶粒

Claims (1)

  1. 一種半導體封裝裝置，包括： 一第一半導體晶粒，包括一第一表面； 一介電層，環繞該第一半導體晶粒，該介電材料包括與該第一表面實質齊平的一表面；以及 一覆蓋層，覆蓋該第一半導體晶粒的該第一表面與該介電材料的該表面，其中該覆蓋層與一切割膠帶之間的黏著性小於該介電材料與該切割膠帶之間的黏著性。
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