TW201639112A - 半導體元件及製造方法 - Google Patents
半導體元件及製造方法 Download PDFInfo
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- TW201639112A TW201639112A TW104136625A TW104136625A TW201639112A TW 201639112 A TW201639112 A TW 201639112A TW 104136625 A TW104136625 A TW 104136625A TW 104136625 A TW104136625 A TW 104136625A TW 201639112 A TW201639112 A TW 201639112A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 171
- 238000000034 method Methods 0.000 title abstract description 125
- 239000000463 material Substances 0.000 claims abstract description 67
- 239000011241 protective layer Substances 0.000 claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 193
- 229920000642 polymer Polymers 0.000 claims description 41
- 239000004020 conductor Substances 0.000 claims description 29
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 238000004806 packaging method and process Methods 0.000 claims description 5
- 239000008393 encapsulating agent Substances 0.000 abstract description 2
- 230000008569 process Effects 0.000 description 91
- 239000000758 substrate Substances 0.000 description 63
- 229920002120 photoresistant polymer Polymers 0.000 description 44
- 238000002161 passivation Methods 0.000 description 27
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 239000012790 adhesive layer Substances 0.000 description 13
- 238000000465 moulding Methods 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- 229920002577 polybenzoxazole Polymers 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 10
- 238000005553 drilling Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000009713 electroplating Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000008859 change Effects 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 238000000059 patterning Methods 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004696 Poly ether ether ketone Substances 0.000 description 2
- 239000004695 Polyether sulfone Substances 0.000 description 2
- 239000004734 Polyphenylene sulfide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- JUPQTSLXMOCDHR-UHFFFAOYSA-N benzene-1,4-diol;bis(4-fluorophenyl)methanone Chemical compound OC1=CC=C(O)C=C1.C1=CC(F)=CC=C1C(=O)C1=CC=C(F)C=C1 JUPQTSLXMOCDHR-UHFFFAOYSA-N 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000003999 initiator Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920003208 poly(ethylene sulfide) Polymers 0.000 description 2
- 229920000768 polyamine Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920006393 polyether sulfone Polymers 0.000 description 2
- 229920002530 polyetherether ketone Polymers 0.000 description 2
- -1 polymethylene Polymers 0.000 description 2
- 229920000069 polyphenylene sulfide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229920000800 acrylic rubber Polymers 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004414 compression moulding compound Substances 0.000 description 1
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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Abstract
本揭露提供一半導體元件和製造方法。一可回銲導電材料被置放與該貫穿通路電性連接,其中該貫穿通路延伸貫穿一封裝物。於該可回銲材料上形成一保護層。在一實施例中,在該保護層中形成一開口以曝露該可回銲材料。在另一實施例中形成該保護層以使該可回銲材料延伸遠離該保護層。
Description
本發明係有關於半導體元件,且特別是有關於半導體元件之製造方法。
半導體產業在近年歷經快速發展,其可歸功於不同電子元件整合
密度之持續改良(如電晶體、二極體、電阻及電容等)。該整合密度之持續改良絕大多數歸功於最小特徵尺寸之持續縮小(例如半導體製程節點持續縮小邁向20奈米以下),因此更多元件可被整合於單一面積中。有鑑於近年在小尺寸、高速、高頻寬、以及低功耗、低延遲等要求日趨嚴苛,在半導體晶粒封裝技術上也相對追求更小更先進。
在半導體技術持續演進的同時,堆疊式(stacked)及銲線結合式
(bonded)之半導體元件逐漸成為有效縮小半導體元件之一方法。在一堆疊式半導體元件中,主動電路如邏輯(logic)、記憶體(memory)、處理器(processor)及類似電路等係至少部分形成於複數個獨立基板(substrate)上,之後再互相以銲線實體附著結合以形成一工作元件。該銲線製程(bonding process)係利用精密技術以達到預期之成效。
本揭露提供一半導體元件,包括:一第一半導體晶粒,其封裝於一封裝物中;一貫穿通路,其延伸貫穿該封裝物且與該第一半導體
晶粒橫向分離;一第一可回銲導電材料,其電性連接該貫穿通路;以及一保護層,其至少部分覆蓋該第一可回銲導電材料及該第一半導體晶粒,其中該保護層具有一開口以曝露該第一可回銲導電材料。
本揭露亦提供一半導體元件,包括:一第一貫穿通路,其
延伸貫穿一封裝物;一第一半導體晶粒,其延伸貫穿該封裝物,其中至少部分之該封裝物係位於該第一貫穿通路與該第一半導體晶粒之間;一保護層,其覆蓋該第一貫穿通路及該第一半導體晶粒,其中該保護層具有一第一高度垂直於該第一半導體晶粒之一主要表面;以及一第一可回銲材料,其延伸貫穿該保護層,該第一可回銲材料具有一第二高度垂直於該第一半導體晶粒之該主要表面,該第二高度係大於該第一高度。
本揭露更提供一製造一半導體元件之方法,其包括:封裝
一第一半導體晶粒及一貫穿通路於一封裝物中,其中該封裝步驟將至少部分之封裝物置放於該第一半導體晶粒與該貫穿通路之間;置放一第一可回銲材料而電性連接該貫穿通路;以及在置放該第一可回銲材料後形成一保護層,以密封至少部分之該第一可回銲材料,其中該保護層曝露該第一可回銲材料。
101、605‧‧‧載具基板
103‧‧‧黏著層
105‧‧‧聚合物層
107‧‧‧第一晶種層
109‧‧‧光阻
111‧‧‧貫穿通路
201、301、1005、1007‧‧‧半導體元件
203、303、1003‧‧‧基板
205、305‧‧‧金屬層
207、307、1009‧‧‧接觸點
209、309、505、1013‧‧‧外部連接點
211、311、503、1603‧‧‧鈍化層
401、1011‧‧‧封裝體
501、1601‧‧‧重佈層
601‧‧‧環結構
603‧‧‧紫外膠帶
607‧‧‧黏著劑
703、903‧‧‧開口
801‧‧‧背面球形接墊
901‧‧‧背面保護層
1000‧‧‧第一封裝
1015‧‧‧貫穿基板通路
1017‧‧‧銲線
1100‧‧‧集成扇出層疊封裝(InFO-POP)結構
1305、1701‧‧‧頸部
為協助讀者達到最佳理解效果,建議在閱讀本揭露時同時參考附件圖示及其詳細文字敘述說明。請注意為遵循業界標準作法,本專利說明書中的數個圖式非按照正確的比例繪製。在數個圖式中,尺寸可能刻意放大或縮小,以協助讀者清楚了解其中的討論內容。
圖1 為根據數個實施例,有關形成貫穿通路之示意圖。
圖2 為根據數個實施例,有關一第一半導體元件實施例之示意圖。
圖3 為根據數個實施例,在該些貫穿通路之間置放該第一半導體元件之示意圖。
圖4 為根據數個實施例,一封裝該第一半導體元件及該些貫穿通路之示意圖。
圖5 為根據數個實施例,有關形成一重佈層及外部連接之示意圖。
圖6A及圖6B 為根據個實施例,有關剝離(debond)一載具晶圓(carrier wafer)之示意圖。
圖7A及圖7B 為根據數個實施例,有關一暴露該些貫穿通路之示意圖。
圖8 為根據數個實施例,有關一置放一可回銲材料之示意圖。
圖9 為根據數個實施例,有關一置放一保護層之示意圖。
圖10 為根據數個實施例,有關另一封裝之銲線示意圖。
圖11 為根據數個實施例,有關一半導體基板去框(singulation)之示意圖。
圖12至圖13B 為根據數個實施例,有關該可回銲材料自該保護層延伸之一實施例示意圖。
圖14及圖15 為根據數個實施例,其不具備一聚合物層之示意圖。
圖16至圖18 為根據數個實施例,有關一使用一重佈層之實施例示意圖。
本說明書提供了數個不同的實施方法或實施例,可用於實現本發明的不同特徵。為簡化說明起見,本說明書中也同時描述了特定零組件與佈置的範例。請注意提供這些特定範例的目的僅在於示範,而非對本發明予以任何限制。舉例而言,在以下說明第一特徵如何基於或取代第二特徵而來的敘述中,可能會包括數個實施例,其中第一特徵與第二特徵為直接接觸,敘述中也可能包括其他不同實施例,其中第一特徵與第二特徵中間另有額外特徵,以致於第
一特徵與第二特徵並不直接接觸。此外,本說明書中的各種範例可能使用重複的參考數字或文字註記,以使文件更加簡單化和明確,這些重複的參考數字與註記不代表不同的實施例與配置內容之間有任何關聯。
另外,本文件在使用與空間相關的敘述詞彙,如“在...之下”,“低”,
“下”,“上方”,“之上”,“下”,“頂”,“底”和類似詞彙時,為便於理解,其用法均在於描述附件圖示中一個元件或特徵與另一個(或多個)元件或特徵的相對關係。除了圖示中所顯示的角度方向外,這些空間相對詞彙也用來描述該裝置在使用中以及操作時的可能角度和方向。當該裝置的角度方向可能不同(旋轉90度或其它方位)時,此時即可根據所使用的空間相關敘述來加以解釋與理解。
參照圖1所示之具有一黏著層(adhesive layer)103之一第一載
具基板(first carrier substrate)101、一聚合物層(polymer layer)105、及一位於該第一載具基板101上之第一晶種層(first seed layer)107。該第一載具基板101包括以矽為主之材料,例如玻璃或氧化矽,或其他材料如氧化鋁,或是上述該些材料之組合物或類似物等。該第一載具基板101係為平面以容納該些半導體元件附著其上,如一第一半導體元件201及一第二半導體元件301等(圖1未標示該些半導體元件,其於圖2A至圖3中標示說明之)。
該黏著層103係位於該第一載具基板101上,以協助上層覆蓋元
件(如該聚合物層105)之附著。根據一實施例,該黏著層103可包括一紫外光膠(ultra-violet glue),當暴露於紫外光時其黏著特性會隨之消失。也可使用其他種類之黏著物,例如壓感黏著劑(pressure sensitive adhesive)、輻射固化黏著劑(radiation curable adhesive)、環氧樹脂(epoxy)、或是上述該些材料之組合物或類似物等。該黏著層103係以半液態或膠狀型態而位於該第一載具基板101上,其可隨壓力變化而改變其形狀。
該聚合物層105係位於該黏著層103上,當該些第一半導體元件
201及第二半導體元件301附著之後,其用以保護該些第一半導體元件201及第二半導體元件301。根據一實施例,該聚合物層105係為聚苯并噁唑
(polybenzoxazole PBO),然而其他合適材料如聚亞醯胺(polyimide)或聚亞醯胺衍生物等,亦為可使用之材料。該聚合物層105可藉由一旋轉塗佈製程(spin-coating process)來置放,以達到介於0.5微米至10微米間,例如5微米之厚度,其他合適之製程方法及厚度亦為可使用。
該第一晶種層107形成於該聚合物層105上。根據一實施例,該第一晶種層107係為一導電材料之薄層,其可於後續步驟中輔助一厚層之形成。該第一晶種層107包括一厚度約1000埃之鈦層,及其後厚度約5000埃之一銅層。根據擬用之不同材料,該第一晶種層107可利用不同製程方法形成,如濺鍍(sputtering)、蒸鍍(evaporation)、或電漿輔助化學氣相沈積(PECVD)等。該第一晶種層107之形成厚度係介於0.3微米至1微米間,例如0.5微米。
圖1為該第一晶種層107上之一光阻109之置放與蝕刻示意圖。根據一實施例,該光阻109係以一旋轉塗佈製程置放於該第一晶種層107之上,其厚度介於50微米至250微米間,例如120微米。當置放完成後,可將該光阻109暴露於一蝕刻能量源(例如一蝕刻光源)以誘發蝕刻化學反應,並造成該光阻109暴露於該蝕刻光源下之部分出現物理變化。之後於該光阻109之暴露部分使用一顯影劑(developer)以利用該物理變化,並根據目標圖樣選擇性地去除該光阻109之暴露部分或未暴露部分二者之一。
根據一實施例,形成於該光阻109之該圖樣係為針對該貫穿通路111之一圖樣。該貫穿通路111之形成係為一置放安排方式,其位於該些後續附著元件如該第一半導體元件201及該第二半導體元件301之不同二側。然而有關該貫穿通路111圖樣之其他適當置放安排亦可使用,例如另一置放方式,其中該第一半導體元件201及該第二半導體元件301位於該貫穿通路111之相反二側等。
根據一實施例,該貫穿通路111係形成於該光阻109中。根據一實施例,該貫穿通路111包括一或多種導電材料,例如銅(copper)、鎢(tungsten)、或其他類似之導電材料等,其形成方式包括電鍍(electroplating)、無電電鍍
(electroless plating)、或類似方式等。根據一實施例,使用一電鍍製程,其中該
第一晶種層107及該光阻109係部分或全部浸沒於一電鍍溶液中。該第一晶種層107之表面係導電連接於一外部直流電源供應(external DC power supply)之負極,以使該第一晶種層107作為電鍍製程中之一陰極。一堅固導電陽極如銅陽極等,亦浸沒於該電鍍溶液中並連接於該電源供應之一正極。該陽極之原子溶解於該電鍍溶液中,而溶解之原子會被該陰極如該第一晶種層107等吸收,並在該光阻109開口處之中之該第一晶種層107之該暴露導電區域進行電鍍。
當該貫穿通路111藉由該光阻109及該第一晶種層107形成後,
即可以一如圖3所示之合適製程去除該光阻109(未示於圖1)。根據一實施例,可利用一電漿灰化(plasma ashing)製程去除該光阻109,其中該光阻之溫度可持續升高,直到該光阻109達到熱分解並可被去除為止。其他合適之製程方法如濕式去除(wet strip)等亦可被使用。去除該光阻109後即可暴露出位於該第一晶種層107下方之部分。
當該第一晶種層107之部分暴露後,即可如圖3所示將其加以
去除(未示於圖1)。根據一實施例,當該第一晶種層107之暴露部分(即未被該貫穿通路111覆蓋之該些部分)可藉由一濕式蝕刻(wet etching)或一乾式蝕刻(dry etching)加以去除。舉例而言在一乾式蝕刻製程中,該貫穿通路111可作為光罩將反應物導向該第一晶種層107。根據另一實施例,可藉由噴灑或其他方式塗佈蝕刻劑並與該第一晶種層107接觸,以去除該第一晶種層107之暴露部分。在該第一晶種層107之暴露部分被蝕刻去除後,可暴露部分之該聚合物層105介於該貫穿通路111間。
圖2所示係一第一半導體元件201,其附著於該貫穿通路111間
之該聚合物層105上(未示於圖2而於圖3中說明之)。根據一實施例,該第一半導體元件201包括一第一基板203、第一主動元件(未單獨圖示)、第一金屬層205、第一接觸點207、一第一鈍化層211、及第一外部連接點209等。該第一基板203包括已摻雜或未摻雜之塊狀矽(bulk silicon)、或一絕緣層上矽基板
(silicon-on-insulator SOI substrate)之一主動層等。一般而言,一絕緣層上矽基板包括一層之矽材料如矽、鍺、矽鍺、絕緣層上矽(SOI)、絕緣層上矽鍺(silicon germanium on insulator)、或其組合材料等。其他可被使用之基板包括多層基板、梯度基板(gradient substrate)、或複合定位基板(hybrid orientation substrate)等。
該些第一主動元件包括多種主動及被動元件如電容、電阻、電感及其他可用來實現該第一半導體元件201之設計功能與結構之相關元件等。該些第一主動元件可藉由任一合適之製程形成於該第一基板203之內或其上。
該第一金屬層205形成於該第一基板203及該些第一主動元件之上,其係設計用以連接不同之主動元件以形成工作電路。根據一實施例,該第一金屬層205係以任一合適之製程形成,例如沈積(deposition)、鑲嵌(damascene)、雙重鑲嵌(dual damascene)等,其中該第一金屬層205係由交錯之介電層與導電材料層組合而成。根據一實施例,可能有四層之金屬層,其間隔至少一層間介電質層(interlayer dielectric layer ILD)而與該第一基板203分離,其中該第一金屬層205之確實數量係根據該第一半導體元件201之設計而定。
該第一接觸點207係形成於該第一金屬層205之上且與該第一金屬層205導電連接。該第一接觸點207可包括鋁,而其他材料如銅等亦可被接受使用。該第一接觸點207係以一沈積製程如濺鍍(sputtering)等以形成一層之材料(未示於圖中),其後以一合適製程如光罩及蝕刻等將該材料層之部分加以去除,以形成該第一接觸點207。然而亦可使用其他合適之製程方法以形成該第一接觸點207。該第一接觸點207之形成厚度係介於0.5微米至4微米間,例如1.45微米。
該第一鈍化層211形成於該第一基板203,且覆蓋於該第一金屬層205及該第一接觸點207之上。該第一鈍化層211可由一或多種合適之介電材料組成,如氧化矽(silicon oxide)、氮化矽(silicon nitride)、低K介電質如碳摻雜氧化物(carbon doped oxide)、極低K介電質如多孔碳摻雜二氧化矽(porous
carbon doped silicon dioxide)、以上材料之組合或類似物等。該第一鈍化層211可經由一製程如化學氣相沉積(chemical vapor deposition CVD)等形成,其他合適之製程方法亦可使用,以形成一厚度介於0.5微米至5微米間,例如大約9.25千埃左右之厚度。
該第一外部連接點209可形成以提供該第一接觸點207及一重
佈層501(未示於圖2而於圖5中說明之)間之導電接觸區域。根據一實施例,該第一外部連接點209係為導電柱體,其最初形成方式係於該第一鈍化層211之上形成厚度介於5微米至20微米間,例如大約10微米左右厚度之一光阻(未示於圖中)。該光阻可被圖樣化(patterned)以暴露部分之該第一鈍化層211而讓該些導電柱體延伸進入其中。該光阻在圖樣化後可作為去除該第一鈍化層211適當區域之一光罩,以暴露下方第一接觸點207之部分區域,其係與該第一外部連接點209接觸連接。
該第一外部連接點209可形成於該第一鈍化層211及該光阻二
者之開口中。該第一外部連接點209可由一導電材料如銅等形成,其他導電材料如鎳、金、合金、以上材料之組合物、或類似材料等亦可被使用。此外,該第一外部連接點209可由一製程如電鍍等形成,其中電流流經該第一接觸點207之導電區域,且該些導電區域係預計形成該第一外部連接點209之區域,且該第一接觸點207浸沒於一溶液中。該溶液及該電流可在該開口沈積例如銅,以填充(fill)及/或填滿(overfill)該光阻及該第一鈍化層211之該些開口,以形成該第一外部連接點209。在該第一鈍化層211開口外之該些多餘導電材料及光阻可以例如灰化製程(ashing process)、化學機械拋光(CMP)製程、二者之組合,或類似製程等加以去除。
然而如同熟知此技藝人士所理解,上述形成該第一外部連接點
209之過程僅為其中之一種方法,而非用以限制實施例之實施方式。同時,上述之方法僅為描述本實施例之用,其他可用於形成該第一外部連接點209之合適製程亦可被使用。所有合適之製程均應被視為包括於實施例之一部分。
一晶粒附接膜(die attach film DAF)217位於該第一基板203之
一相反側,以協助附著該第一半導體元件201於該聚合物層105上。根據一實施例,該晶粒附接膜217係為一環氧樹脂(epoxy resin)、酚樹脂(phenol resin)、丙烯酸橡膠(acrylic rubber)、二氧化矽填充劑(silica filler)、或上述材料之組合物等,並由一疊片壓製技術(lamination technique)處理。然而,其他合適之替代材料與形成製程方法亦可被使用。
圖3所示係將該第一半導體元件201及該第二半導體元件301
置放於該聚合物層105上之一種方式。根據一實施例,該第二半導體元件301包括一第二基板303、第二主動元件(未單獨圖示)、第二金屬層305、第二接觸點307、一第二鈍化層311、及第二外部連接點309等。根據一實施例,該第二基板303、該些第二主動元件、該些第二金屬層305、該些第二接觸點307、該第二鈍化層311、及該些第二外部連接點309係類似於該第一基板203、該些第一主動元件、該些第一金屬層205、該些第一接觸點207、該第一鈍化層211、及該些第一外部連接點209,或者也可能並不類似。
根據一實施例,該第一半導體元件201及該第二半導體元件301
可藉由一取放(pick and place)製程置放於該聚合物層105上方。然而,其他可置放該第一半導體元件201及該第二半導體元件301之合適製程方法亦可被使用。
圖4為針對該些貫穿通路111、該第一半導體元件201及該第二
半導體元件301之一封裝示意圖。該封裝可於一成型裝置(molding device)進行(該元件未示於圖4中),其可包括一頂模部分(top molding portion)及一與頂模分離之底模部分(bottom molding portion)。當該頂模部分下降至與該底模部分相鄰時,可形成一針對該載具基板(carrier substrate)101、該貫穿通路111、該第一半導體元件201及該第二半導體元件301之模穴(molding cavity)。
在封裝過程中,該頂模部分係位於該底模部分相鄰區域,藉此將
該載具基板101、該貫穿通路111、該第一半導體元件201及該第二半導體元件
301封閉於該模穴內。上述封閉完成後,該頂模部分與該底模部分可形成一氣密封印(airtight seal)以控制該模穴內氣體之進出。於上述封印完成後置放一封裝體401於該模穴內。該封裝體401可為一模塑料樹脂(molding compound resin)例如聚亞醯胺(polyimide)、PPS、PEEK、PES、抗熱晶體樹脂(heat resistant crystal resin)、上述材料之組合物、或類似材料等。該封裝體401可於該頂模部分與該底模部分對準之前,先行置放於該模穴內,或經由一注射孔(injection port)注入(inject)該模穴內。
當該封裝體401置放於該模穴內且封裝完成該載具基板101、該
貫穿通路111、該第一半導體元件201及該第二半導體元件301時,可對該封裝體401進行固化(cured)以硬化該封裝體401並提供最佳保護效果。上述該固化製程實際上至少部分根據該封裝體401所選擇的材料而定,在一實施例中係選擇使用模塑料作為該封裝體401,該固化步驟可在一製程中進行,如將該封裝體401加熱至約100℃至約130℃,例如約125℃,持續約60秒至約3000秒,例如約600秒。此外,引發劑(initiator)及/或催化劑(catalyst)亦可被添加於該封裝體401中,以便更佳控制該固化製程。
然而如同熟知此技藝人士所理解,上述說明之該固化製程僅為其
中之一種方法,而非用以限制本實施例之實施方式。其他固化製程,如照射(irradiation)或將該封裝體401置於環境溫度下硬化等方法亦可被使用。所有合適之固化製程均應被視為包括於本揭露實施例之一部分。
圖4所示為該封裝體401之一減薄化(thinning),以暴露該些貫
穿通路111、該第一半導體元件201及該第二半導體元件301等供後續處理。該減薄化可藉由例如一機械研磨(mechanical grinding)或化學機械拋光(chemical mechanical polishing CMP)製程進行,其中藉由使用化學蝕刻劑及研磨物等與該封裝體401產生化學反應,以研磨去除該些封裝體401、該第一半導體元件201及該第二半導體元件301等,直到暴露該些貫穿通路111、該些第一外部連接點209(位於該第一半導體元件201上)、及該些第二外部連接點309(位於該第
二半導體元件301上)為止。因此,該第一半導體元件201、該第二半導體元件301、及該些貫穿通路111可能有一平坦表面,其與該封裝體401亦係為一平面。
然而上述說明之該化學機械拋光製程僅為所描述之其中一種實
施例,而非用以限制實施例之實施方式。亦可使用其他合適之去除製程以減薄化該封裝體401、該第一半導體元件201、及該第二半導體元件301、並暴露該些貫穿通路111。舉例而言可使用一系列之化學蝕刻。亦可使用上述製程及其他合適之去除製程以減薄化該封裝體401、該第一半導體元件201、及該第二半導體元件301等,所有該些製程均應被視為包括於實施例之一部分。
圖5所示為一重佈層(redistribution layer RDL)501之一形成,
以連接該第一半導體元件201、該第二半導體元件301、該些貫穿通路111、及該些第三外部連接點505等。藉由利用該重佈層501以連接該第一半導體元件201及該第二半導體元件301,該第一半導體元件201及該第二半導體元件301之接點數目(pin count)可超過1000。
根據一實施例,該重佈層501之形成可利用一合適之製程如化學
氣相沈積(CVD)或濺鍍(sputtering)先形成一鈦銅合金(titanium copper alloy)晶種層(seed layer)(未示於圖中)。之後形成一光阻(未示於圖中)以覆蓋該晶種層,圖像化該光阻以暴露該晶種層之該些部分,其位於該重佈層501預定之位置。
當形成並圖像化該光阻後,可利用一沈積製程如電鍍,將一導電
材料例如銅形成於該晶種層上。該導電材料之形成厚度係介於1微米至10微米間,例如5微米。請注意此處所討論可用以形成該導電材料之材料及方法僅為示範例。亦可利用其他合適之該些材料如銅鋁或金,及其他合適之成形製程如化學氣相沉積(CVD)或物理氣相沉積(PVD)等以形成該重佈層501。
當形成該導電材料後,可利用一合適之去除製程如灰化(ashing)
以去除該光阻。此外當該光阻去除後,可選擇一合適之蝕刻製程並利用該導電材料作為一光罩,以去除該晶種層被該光阻所覆蓋之該些部分。
圖5所示為位於該重佈層501上之一第三鈍化層503之一形成
方式,其可保護及隔離該些重佈層501及其他位於下方之結構。根據一實施例,該第三鈍化層503係為聚苯并噁唑(polybenzoxazole PBO),然而其他合適材料如聚亞醯胺(polyimide)或聚亞醯胺衍生物等,亦係可使用之材料。該第三鈍化層503可藉由一旋轉塗佈製程(spin-coating process)來置放,以達到介於5微米至25微米間,例如7微米之厚度。其他合適之製程方法及厚度亦係可使用。
根據一實施例,從該第三鈍化層503起至該聚合物層105之結構
厚度係小於或等於約200微米。在上述該厚度持續縮小的情況下,其可被運用於各種小尺寸之應用,如手機或相關類似應用等,同時仍可維持其必要功能。
然而如同熟知此技藝人士所理解,上述該結構之實際厚度係至少部分取決於其單元之整體設計,因此任何合適之厚度均可被接受使用。
此外圖5所示僅為一獨立之重佈層501,其目的在詳細說明,而
非用以限制實施例之施行方式。任何適當數目之該些導電與鈍化層,例如三個重佈層501等,均可藉由重複上述製程之方式形成該重佈層501。任何適當數目之層均係可接受。
圖5更說明一第三外部連接點505之形成方式,其與該重佈層
501導電連接。根據一實施例,當形成該第三鈍化層503後,去除該第三鈍化層503之部分區域以形成貫穿該鈍化層503之一開口,其暴露至少部分之下方該重佈層501。該開口係提供該重佈層501及該些第三外部連接點505間之導電接觸。該開口可藉由一合適之蝕刻光罩及蝕刻製程形成,亦可利用其他合適之製程以暴露該重佈層501之該些部分。
根據一實施例,該些第三外部連接點505位於該重佈層501上並
貫穿該第三鈍化層503,其可為包括共熔材料(eutectic material)如銲錫(solder)
等之一球柵陣列封裝(ball grid array BGA),其他合適之材料亦可被接受使用。另於該些第三外部連接點505與該重佈層501之間可選擇使用一球凸塊底金屬層(under bump metallization)。根據一實施例,該些第三外部連接點505係為錫球(solder ball),而該外部連接點505可利用一長球(ball drop)方法形成,如直接長球製程(direct ball drop process)等。此外該些錫球之形成方式係先利用任一合適製程如蒸鍍(evaporation)、電鍍(electroplating)、印刷(printing)、或銲錫轉換(solder transfer)等,以形成一錫層(layer of tin),之後進行一回銲(reflow)以型塑該些錫球材料為擬用之凸塊形狀(bump shape)。當形成該些第三外部連接點505後,可進行一測試以確認該結構係合適可進行後續處理。
圖6A係自該第一半導體元件201及該第二半導體元件301剝離(debonding)該第一載具基板101之一示意圖。根據一實施例,該些第三外部連接點505及該結構係附著於一環結構601,其中該結構包括該第一半導體元件201及該第二半導體元件301等,。該環結構601可為一金屬環,其目的在於進行該剝離過程中間及結束後提供該結構支撐及穩定性。根據一實施例,該些第三外部連接點505、該第一半導體元件201及該第二半導體元件301係以一紫外膠帶(ultraviolet tape)603附著於該環結構601,其他合適之附著或黏著方式亦可被接受使用。
當該些第三外部連接點505及該結構,其包括該第一半導體元件201及該第二半導體元件301等,附著於該環結構601時,可利用一熱製程將該第一載具基板101自包括該第一半導體元件201及該第二半導體元件301等之該結構剝離,而該熱製程係改變該黏著層103之黏著特性。根據一特定實施例,可利用一能量源例如一紫外雷射(ultraviolet laser)、一二氧化碳雷射(carbon dioxide CO2 laser)、或一紅外雷射(infrared IR laser)等加以照射並加熱該黏著層103,直到該黏著層103損失至少部分之黏著特性。進行上述該些步驟後,該第一載具基板101及該黏著層103可與該結構實體隔離並自包括該些第三外部連接點505、該第一半導體元件201及該第二半導體元件301之該結構去除。
圖6B係自該第一半導體元件201及該第二半導體元件301剝
離該第一載具基板101另一實施例之示意圖。根據此一實施例,利用一第一黏著劑607將該些第三外部連接點505附著於一第二載具基板605。根據一實施例,該第二載具基板605係類似於該第一載具基板101,但也可能係不同。當上述該附著完成後,可照射該黏著層103以實體去除該黏著層103及該第一載具基板101。
圖7A係使用該環結構601之一實施例示意圖,其所示係該聚合
物層105之一圖樣化以暴露該些貫穿通路111(及相關之該第一晶種層107)。根據一實施例,該聚合物層105係以一雷射鑽孔方法(laser drilling method)加以圖像化。在上述該方法中,可先行沈積一保護層於該聚合物層105之上,該保護層可為例如未示於圖7A之一光熱轉換層(light-to-heat conversion LTHC layer)或一水溶性保護膜層(hogomax layer)等。當保護完成後,導引一雷射照射於該聚合物層105之部分,該些部分係擬被去除以暴露下方之該些貫穿通路111。
在雷射鑽孔過程中,該鑽孔能量範圍係在0.1微焦耳至約30微焦耳之間,且該鑽孔角度係在0度(垂直於該聚合物層105)至垂直於該聚合物層105約85度角之間。根據一實施例,該圖樣化之形成係於該貫穿通路111上形成該些第一開口703,其有介於約100微米至約300微米,例如200微米左右之一第一寬度。
根據另一實施例,該聚合物層105之圖樣化係先於該聚合物層
105上使用一光阻,再將該光阻暴露於一蝕刻能量源(例如一蝕刻光源)以誘發蝕刻化學反應,並造成該光阻暴露於該蝕刻光源下之部分出現物理變化。之後於該光阻之暴露部分使用一顯影劑(developer)以利用該物理變化,並根據目標圖樣選擇性地去除該光阻之暴露部分或未暴露部分二者之一,同時以一乾蝕刻製程去除該聚合物層105下方之暴露部分。然而其他可用以圖樣化該聚合物層105之合適方法均係可接受被使用。
圖7B所示係另一實施例,其可暴露該些貫穿通路111以用於後
續連接。根據上述該實施例,完整去除該聚合物層105之全部以暴露該些貫穿通路111(及相關之第一晶種層107)。根據一實施例,該聚合物層105之去除可利用一回蝕製程(etch back process),並以蝕刻劑(etchant)去除該聚合物層105,直到暴露該些貫穿通路111為止。舉例而言根據一實施例,該聚合物層105係為聚苯并噁唑(PBO),可於一濕蝕刻製程(wet etch process)中以一蝕刻劑去除該聚合物層105。
然而如同熟知此技藝人士所理解,上述說明之該濕蝕刻製程僅為
其中之一種方法,而非用以限制之實施方式。其他合適之去除方法,如化學機械拋光(CMP)、低能量剝離(low debond energy)(其可導致一部分之光熱轉換LTHC層保留於該聚合物層105上)、或無水溶性保護膜製程(hogomax free process)等亦可被接受使用,以降低該保護層相關成本費用。所有合適之製程均應被視為包括於實施例之一部分。
在圖7A及圖8所示實施例係為一位於該第一開口703內之背
面球形接墊(backside ball pad)801之一置放方式,其係用以保護已暴露之該些貫穿通路111。根據一實施例,該些背面球形接墊801包括一導電材料如銲膏上銲錫(solder on paste)或銲錫氧化保護(oxygen solder protection OSP),其他合適之材料亦可被接受使用之。根據一實施例,可藉由一模板(stencil)方式使用該些背面球形接墊801,其他合適之使用方式亦可被接受使用之,之後進行回銲以形成一凸塊形狀。
圖8所示為可使用於該些背面球形接墊801之一選擇性整平
(leveling)或打磨(coining)製程。根據一實施例,該些背面球形接墊801之型塑可利用位於每一該些背面球形接墊801周圍之一模板(stencil)及可施加壓力之一加壓機(press)以具體改變部分該些背面球形接墊801之形狀,並使該些背面球形接墊801之頂表面平坦化。
圖9所示係一覆蓋於該些背面球形接墊801上之一背面保護層
901之一置放及圖像化,其可有效密封位於該些背面球形接墊801及該貫穿通路111間之接合,以防止水氣侵入。根據一實施例,該背面保護層901係一保護材料如聚苯并噁唑(PBO)、防銲劑(Solder Resistance SR)、壓片複合膠帶(Lamination Compound LC)tape、Ajinomoto形成膜(ABF)、非導電膏(non-conductive paste NCP)、非導電膜(non-conductive film NCF)、圖形化底膠填充(patterned underfill PUF)或改善翹曲黏著劑(warpage improvement adhesive WIA)、液態壓模化合物(liquid molding compund)V9、上述材料之組合、或類似物等。其他合適之材料亦可被接受使用之。該背面保護層901之使用可利用一製程如網面印刷(screen printing)、壓合(lamination)、spin coating(旋轉塗佈)、或類似方法等,其厚度介於1微米至200微米左右。
如圖9所示,當該背面保護層901被置放完成後,其即可被圖樣
化以暴露該些背面球形接墊801。根據一實施例,該背面保護層901之圖樣化可利用一製程如雷射鑽孔,其中雷射係導向照射於該背面保護層901之該些擬去除部分,以暴露該些背面球形接墊801。在雷射鑽孔過程中,該鑽孔能量範圍係在0.1微焦耳至約30微焦耳之間,且該鑽孔角度係在0度(垂直於該背面保護層901)至垂直於該背面保護層901約85度角之間。根據一實施例,利用圖樣化形成一第二開口903於該些背面球形接墊801上方,該第二開口903之直徑介於約30微米至300微米左右,例如150微米。
根據另一實施例,該背面保護層901之圖樣化係先於該背面保護層901上使用一光阻,再將該光阻暴露於一蝕刻能量源(例如一蝕刻光源)以誘發蝕刻化學反應,並造成該光阻暴露於該蝕刻光源下之部分出現物理變化。之後於該光阻之暴露部分使用一顯影劑(developer)以利用該物理變化,並根據目標圖樣選擇性地去除該光阻之暴露部分或未暴露部分二者之一,同時以一乾蝕刻製程去除該背面保護層901下方之暴露部分。然而其他可用以圖樣化該背面保護層901之合適方法均係可被接受使用。
藉由利用一光學蝕刻製程以圖樣化該背面保護層901,可控制該
第二開口903之形狀。舉例而言利用一光學蝕刻製程,可控制在該第二開口903形成過程中所形成之該些側壁,使其具有一大於75°之第一角度α1。如此可確保該背面保護層901在維持該些背面球形接墊801有效密封之同時仍可提供該些背面球形接墊801與其他結構間之有效連接。
圖10所示係該些背面球形接墊801與一第一封裝1000之一銲
線附著(bonding)。根據一實施例,該第一封裝1000包括一第三基板1003、一第三半導體元件1005、一第四半導體元件1007(其與該第三半導體元件附著連接)、第三接觸點1009、一第二封裝體1011、及第四外部連接點1013等。根據一實施例,該第三基板1003係為一封裝基板,其包括如貫穿基板通路(through substrate vias)1015之內部連接(internal interconnects),其可連接該第三半導體元件1005及該第四半導體元件1007至該些背面球形接墊801。
該第三基板1003亦可係一中介層(interposer),其可作為一中間
基板以連接該第三半導體元件1005及該第四半導體元件1007至該些背面球形接墊801。根據本實施例,該第三基板1003可為一摻雜或未摻雜矽基板(silicon substrate),或為一絕緣層上矽基板(silicon-on-insulator SOI substrate)之一主動層等。同時,該第三基板1003亦可為一玻璃基板(glass substrate)、一陶瓷基板(ceramic substrate)、一聚合物基板(polymer substrate),或其他可提供合適保護及/或中間連接功能之基板。上述該些材料及其他可用於該第三基板1003之合適材料亦可被接受使用。
該第三半導體元件1005可為一半導體元件,其設計目的係作為
一邏輯晶粒(logic die)、一中央處理器晶粒、一記憶體晶粒如一隨機存取記憶體晶粒,上述之組合或類似物等。根據一實施例,該第三半導體元件1005包括該些積體電路元件如電晶體、電容、電感、電阻、第一金屬層(未示於圖中)、類似物,及其他有預定之特定功能者。根據一實施例,該第三半導體元件1005係被設計與製造以與該第一半導體元件201一併或同時運行。
該第四半導體元件1007係類似於該第三半導體元件1005。舉例
而言,該第四半導體元件1007可為一半導體元件,其具一特定之設計目的(如一記憶體晶粒),並包括針對一預定功能之積體電路元件。根據一實施例,該第四半導體元件1007係被設計及製造以與該第一半導體元件201及/或該第三半導體元件1005一併或同時運行。
該第四半導體元件1007係附著於該第三半導體元件1005上。根
據一實施例,該第四半導體元件1007係實體附著於該第三半導體元件1005上,例如利用一黏著劑(adhesive)等。根據一實施例,該第四半導體元件1007及該第三半導體元件1005可藉由例如銲線(wire bonds)1017等與該第三基板1003導電連接,其他合適之導電附著方法亦可被接受使用之。
此外,該第四半導體元件1007與該第三半導體元件1005係為實
體附著並彼此導電連接。根據一實施例,該第四半導體元件1007包括第四外部連接點(未示於圖10中),其連接於該第三半導體元件1005上之第五外部連接點(同樣未示於圖10中),以使該第四半導體元件1007與該第三半導體元件1005彼此互相連接。
該第三接觸點1009可形成於該第三基板1003上,以提供該第三
半導體元件1005與該些第四外部連接點1013間之導電連接。根據一實施例,該第三接觸點1009係形成於該第三基板1003上,且其於該基板之內有例如貫穿基板通路(through substrate vias)1015之導電通路。該第三接觸點1009可包括鋁,而其他替代材料如銅等亦可被使用。該第三接觸點1009係以一沈積製程如濺鍍(sputtering)等以形成一層之材料(未示於圖中),該材料層之部分其後以一合適製程如光罩及蝕刻等加以去除,以形成該第三接觸點1009。此外亦可使用其他合適之製程方法以形成該第三接觸點1009。該第三接觸點1009之形成厚度係介於0.5微米至4微米間,例如1.45微米。
可使用該第二封裝體1011以封裝並保護該第三半導體元件1005、
該第四半導體元件1007、及該第三基板1003等。根據一實施例,該第二封裝體
1011可為一模塑料樹脂(molding compound resin),其以一封膠裝置(molding device)(未示於圖10)置放之。舉例而言,該第三基板1003、該第三半導體元件1005、及該第四半導體元件1007等可位於封膠裝置(molding device)之一模穴(cavity)中,且其可被隔絕密封之。該第二封裝體1011可於隔絕密封該模穴之前先行置放於該模穴內,或其後經由一注射孔(injection port)注入(inject)該模穴內。根據一實施例,該第二封裝體1011可為一模塑料樹脂(molding compound resin)例如聚亞醯胺(polyimide)、PPS、PEEK、PES、抗熱晶體樹脂(heat resistant crystal resin)、上述材料之組合物、或類似材料等。
當該第二封裝體1011已位於該模穴內且封裝完成該第三基板
1003、該第三半導體元件1005及該第四半導體元件1007等之周圍區域時,即可對該第二封裝體1011進行固化(cured)以硬化該第二封裝體1011並提供最佳保護效果。上述該固化製程在實際上至少部分得根據該第二封裝體1011所選擇的材料而定,在一實施例中選擇使用模塑料作為該第二封裝體1011,該固化步驟可在一製程中進行,如將該第二封裝體1011加熱至約100℃至約130℃,例如約125℃,持續約60秒至約3000秒,例如約600秒。此外,引發劑(initiator)及/或催化劑(catalyst)亦可被添加於該封裝體401中,以便更佳控制該固化製程。
然而如同熟知此技藝人士所理解,上述說明之該固化製程僅為其
中之一種方法,而非用以限制之實施方式。其他固化製程,如照射(irradiation)或將該第二封裝體1011置於環境溫度下硬化等方法亦可被使用。所有合適之固化製程均應被視為包括於實施例之一部分。
根據一實施例,可形成該些第四外部連接點1013以提供一外部
連接,其連接該第三基板1003及該些背面球形接墊801。該些第四外部連接點1013可為微凸塊(microbump)或控制塌陷高度晶片連接(controlled collapse chip connection C4)之接點凸塊(contact bump),其包括如錫(tin),或其他合適材料如銀或銅。根據一實施例,該些第四外部連接點1013係為銲錫凸塊(tin solder
bump),此外該些第四外部連接點1013之形成方式係先利用任一合適製程如蒸鍍(evaporation)、電鍍(electroplating)、印刷(printing)、銲錫轉換(solder transfer)、或銲球置放(ball placement)等,以形成一厚度約為100微米之錫層(layer of tin)。
當該錫層於該結構上形成後,即可進行一回銲以型塑該材料為擬用之凸塊形狀。
當該些第四外部連接點1013形成後,該些第四外部連接點1013
被對準置放且與該些背面球形接墊801實體連接,而後進行一附著銲線製程(bonding)。舉例而言,根據一實施例,該些第四外部連接點1013係為錫凸塊(solder bump),該附著製程包括一回銲製程,其中該些第四外部連接點1013之溫度將會升高,直到該些第四外部連接點1013液態化且可流動,而當該些第四外部連接點1013重新凝固時即可使該第一封裝1000與該些背面球形接墊801相互附著連接。
圖10所示為該第二封裝1019與該些背面球形接墊801之另一
銲線附著。根據一實施例,該第二封裝1019類似於該第一封裝1000,且可利用類似製程與該些背面球形接墊801銲線附著。然而,該第二封裝1019亦可能不同於該第一封裝1000。
圖11所示係該第三外部連接點505自該環結構601之一剝離,
及該結構之一去框(singulation)以形成一第一集成扇出層疊封裝(fan out package-on-package InFO-POP)結構。根據一實施例,該第三外部連接點505可自該環結構601剝離,其剝離係首先利用一第二紫外膠帶(ultraviolet tape)將該第一封裝1000與該第二封裝1019附著於一第二環結構。當附著完成後,該第二紫外膠帶603可以紫外輻射照射之,伺其喪失黏著性後,該第三外部連接點505即可與該環結構601實體分離。
當完成該剝離後,可進行該結構之一去框以形成該第一集成扇出
層疊封裝(InFO-POP)結構1100。根據一實施例,該去框可利用一鋸齒刀片(未示於圖中)切片貫穿介於該些貫穿通路111間之該封裝物401及該聚合物層105,
同時將一區域自其他區域分離以形成該第一半導體元件201之該第一集成扇出層疊封裝(InFO-POP)結構1100。然而如同熟知此技藝人士所理解,上述利用一鋸齒刀片將該第一集成扇出層疊封裝(InFO-POP)去框之說明僅為其中之一種方法,而非用以限制之實施方式。其他可用以去框該第一集成扇出層疊封裝(InFO-POP)結構1100之合適方法如利用一或多次蝕刻以分離該第一集成扇出層疊封裝(InFO-POP)結構1100等亦可被使用。上述該些方法及其他可用以去框該第一集成扇出層疊封裝(InFO-POP)結構1100之合適方法均可被接受使用。
藉由上述先在該些背面球形接墊801上形成該背面保護層901,
之後再於該背面保護層901開口之作法,可減少或去除水氣滲透侵入該些背面球形接墊801及其底下結構(如該些貫穿通路111)間之接面。特別是一般以雷射鑽孔形成一大開口後再以一球狀接頭填充該開口所導致之常見問題亦可因此避免。如此一來,常見於背面連接之壓片脫落(delamination)及品質不良等問題亦可望降低或避免再次發生。此外亦可避免因水氣滲透而導致該些貫穿通路111有銅氧化之問題。
根據以上所述,其亦可避免使用其他保護結構。根據一特定實施
例,透過避免水氣滲透及其他品質不良等因素,該些結構如底膠填充(underfill)等即非保護結構時之必要。當該底膠填充非為必要而可避免使用時,該底膠填充材料及相關執行步驟之高成本等亦可望減少。如此一來整體製程可更具效率,整體元件成本也可望進一步降低。
圖12所示係另一實施例,其中該些背面球形接墊801係自該背
面保護層901延伸展開。在此實施例中,在該聚合物層105之圖樣化後(如圖7A所示),該些背面球形接墊801係置放並回銲於該聚合物層105之該第一開口703。該些背面球形接墊801之形成係如圖8所示。然而根據一實施例,該些背面球形接墊801係形成以具有介於約10微米至100微米間,例如20微米之一第一高度H1。
當該些背面球形接墊801形成後,可於該聚合物層105上及該些
背面球形接墊801之間形成該背面保護層901,其至少覆蓋部分之該些背面球形接墊801。根據一實施例,該背面保護層901之形成係如圖9所示。然而在此實施例中,該背面保護層901係形成以具有較該些背面球形接墊801為低之一頂表面。舉例而言根據一實施例,該些背面球形接墊801具有約20微米之該第一高度H1,該背面保護層901具有介於約10微米至80微米間,例如40微米之一第二高度H2。
圖13A所示係為本實施例中形成該第一集成扇出層疊封裝(InFO-POP)結構1100之製程其餘部分。其中,該第一封裝1000之該些第四外部連接點1013係對準並附著於該些背面球形接墊801,且該第一集成扇出層疊封裝(InFO-POP)結構1100係與該結構其餘部分分離(singulated)。根據一實施例,該銲線(bonding)及該去框(singulation)係以圖10至圖11所示之方式進行之,而其他合適之方法亦可被接受使用。
圖13B係圖13A所示之實施例中,介於該些背面球形接墊801及該些第四外部連接點1013間之一實際接點之一特寫圖。由於該背面保護層901係形成於置放該些背面球形接墊801之後,該背面保護層901實際上會形成延伸介於該些背面球形接墊801及該些第四外部連接點1013間之一頸部(在圖16B中以標示1305之虛線圓圈表示之)。
藉由利用一實施例,其背面球形接墊801係從該背面保護層901延伸展開,因此不需要一雷射鑽孔或一光蝕刻製程以形成一貫穿該背面保護層901之該第二開口903。因此上述該些製程即非必要。
圖14所示係另一實施例,其中該些背面球形接墊801係從該背面保護層901延伸展開,且不需該聚合物層105之存在。在此實施例中,在去除該聚合物層105後(如圖7B所示),可如圖12中所示形成該些背面球形接墊801,並與該些貫穿通路111(包括該第一晶種層107)直接接觸。此外該些背面
球形接墊801係形成以具有介於約10微米至100微米間,例如20微米之該第一高度H1。
當形成該些背面球形接墊801後,可形成該背面保護層901並與
該封裝體401直接接觸(因為該聚合物層105已被去除)。在此實施例中,該背面保護層901之形成係如圖12所述,其形成以具有較該些背面球形接墊801為低之一頂表面,例如具有一第二高度H2。
圖15所示係為本實施例中形成該第一集成扇出層疊封裝(InFO-POP)結構1100之製程其餘部分。其中,該第一封裝1000之該些第四外部連接點1013係對準並銲線附著於該些背面球形接墊801,且該第一集成扇出層疊封裝(InFO-POP)結構1100係與該結構其餘部分分離(singulated)。根據一實施例,該銲線附著(bonding)及該去框(singulation)係如圖10至圖11之方式進行之,而其他合適之方法亦可被接受使用。
藉由在形成該些背面球形接墊801之前先行去除該聚合物層105,則在其他實施例中使用之雷射鑽孔製程即非必要。因此即可避免該複雜雷射鑽孔製程及其成本,同時減少可能因此導致之意外損害。
圖16所示係利用一或多個背面重佈層(backside redistribution layer RDL)1601之另一實施例。根據此一實施例,當該封裝物401被去除且該貫穿通路111被暴露之後,可形成該背面重佈層1601於該第一半導體元件201之上且與已暴露之該些貫穿通路111互相導電連接。根據一實施例,該重佈層1601之形成可利用一合適之製程如化學氣相沈積(CVD)或濺鍍(sputtering)先形成一鈦銅合金(titanium copper alloy)晶種層(seed layer)(未示於圖中)。之後形成一光阻(未示於圖中)以覆蓋該晶種層,圖像化該光阻以暴露該晶種層之該些部分,其位於該重佈層1601預定之位置。
當形成並圖像化該光阻後,可利用一沈積製程如電鍍,將一導電材料例如銅形成於該晶種層上。該導電材料之形成厚度係介於1微米至10微米間,例如5微米。請注意此處所討論可用以形成該導電材料之材料及方法僅為
示範例。亦可利用其他合適之該些材料如銅鋁或金,及其他合適之成形製程如化學氣相沉積(CVD)或物理氣相沉積(PVD)等亦可使用以形成該重佈層1601。
當形成該導電材料後,可利用一合適之去除製程如灰化(ashing)
以去除該光阻。此外當該光阻去除後,可選擇一合適之蝕刻製程並利用該導電材料作為一光罩,以去除該晶種層被該光阻所覆蓋之該些部分。
圖16所示為位於該重佈層1601上之一第四鈍化層1603之一形
成,其用以保護及隔離該些重佈層1601及其他位於下方之結構。根據一實施例,該第四鈍化層1603係為聚苯并噁唑(polybenzoxazole PBO),然而其他合適材料如聚亞醯胺(polyimide)或聚亞醯胺衍生物等,亦係可使用之材料。該第四鈍化層1603可藉由一旋轉塗佈製程(spin-coating process)來置放,以達到介於5微米至25微米間,例如7微米之厚度。其他合適之製程方法及厚度亦係可使用。
藉由利用該重佈層1601,置放該些背面球形接墊801時即不需要
準確地定位於該貫穿通路111之上。如此一來,可基於整體設計而安排該些背面球形接墊801之置放位置。同時亦可有效達成元件之微小化。此外根據此處所敘述之實施例,藉由密封結合處以防止水氣滲透之方法可減少或去除該重佈層1601之壓片脫落(delamination)問題。
圖17A所示係另一實施例,其係利用圖13A中所述之實施例及
該重佈層1601。此外圖17B所示係介於該些背面球形接墊801及該些第四外部連接點1013間之該接點之一特寫圖。如圖13B中所述之實施例,因為該些背面球形接墊801係於置放該背面保護層901之前先行形成,該背面保護層901實際上將形成延伸介於該些背面球形接墊801及該些第四外部連接點1013間之一第二頸部(在圖17A中以標示1701之虛線圓圈表示之)。該頸部有助於密封該些背面球形接墊801,以防止水氣滲透。此外,該頸部除如同圖17A之實施例所述範圍,其亦可見於其他該些實施例,其中該背面保護層901係形成於該些背面球形接墊801之後。
圖18所示係另一實施例,其中該重佈層1601係於去除該聚合物層105之後形成。根據本實施例,在去除該聚合物層105後(如圖7B所述),該重佈層1601係於形成該些背面球形接墊801及該背面保護層901之前形成。藉由形成該重佈層1601,該些背面球形接墊801可置放於任一預定之位置。
根據一實施例,提供一半導體元件其包括由一封裝物封裝之一第一半導體晶粒。一貫穿通路,其延伸貫穿該封裝物且與該第一半導體晶粒橫向分離;一第一可回銲導電材料,其與該貫穿通路導電連接,及一保護層,其至少部分覆蓋該第一可回銲導電材料及該第一半導體晶粒,其中該保護層具有一開口以曝露該第一可回銲導電材料。
根據另一實施例,一半導體元件包括延伸貫穿一封裝物之一第一貫穿通路,及延伸貫穿該封裝物之一第一半導體晶粒,其中至少部分之該封裝物係位於該第一貫穿通路與該第一半導體晶粒之間。一保護層,其覆蓋該第一貫穿通路及該第一半導體晶粒,其中該保護層具有一第一高度垂直於該第一半導體晶粒之一主要表面。一第一可回銲材料,其延伸貫穿該保護層,該第一可回銲材料具有一第二高度垂直於該第一半導體晶粒之該主要表面,該第二高度係大於該第一高度。
根據另一實施例,製造一半導體元件之一方法包括封裝一第一半導體晶粒及一貫穿通路於一封裝物中,其中該封裝步驟將至少部分之封裝物置放於該第一半導體晶粒與該貫穿通路之間。置放一第一可回銲材料,其與該貫穿通路導電連接,在置放該第一可回銲材料之後形成一保護層,以密封至少部分之該第一可回銲材料,其中該保護層曝露該第一可回銲材料。
前述內容概述一些實施方式的特徵,因而熟知此技藝之人士可更加理解本揭露之各方面。熟知此技藝之人士應理解可輕易使用本揭露作為基礎,用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本揭露揭示內容的精神與範圍,並且熟
知此技藝之人士可進行各種變化、取代與替換,而不脫離本揭露之精神與範圍。
101‧‧‧第一載具基板
103‧‧‧黏著層
105‧‧‧聚合物層
107‧‧‧第一晶種層
111‧‧‧貫穿通路
201‧‧‧第一半導體元件
301‧‧‧第二半導體元件
303‧‧‧第二基板
305‧‧‧第二金屬層
307‧‧‧第二接觸點
309‧‧‧第二外部連接點
311‧‧‧第二鈍化層
Claims (10)
- 一半導體元件,包括:一第一半導體晶粒,其封裝於一封裝物中;一貫穿通路,其延伸貫穿該封裝物且與該第一半導體晶粒橫向分離;一第一可回銲導電材料,其電性連接該貫穿通路;以及一保護層,其至少部分覆蓋該第一可回銲導電材料及該第一半導體晶粒之,其中該保護層具有一開口以曝露該第一可回銲導電材料。
- 如申請專利範圍第1項所述之半導體元件,還包括一重佈層,其位於該貫穿通路與該第一可回銲導電材料之間。
- 如申請專利範圍第1項所述之半導體元件,其中該開口之一側壁具有至少75°之角度。
- 如申請專利範圍第1項所述之半導體元件,還包括一聚合物層,其位於該第一半導體晶粒與該保護層之間。
- 如申請專利範圍第1項中所述之半導體元件,還包括一第二可回銲導電材料,其延伸貫穿該開口且實體接觸該第一可回銲導電材料。
- 如申請專利範圍第1項中所述之半導體元件,其中該保護層實體接觸一相鄰於該第一半導體晶粒之黏晶薄膜。
- 一半導體元件,包括:一第一貫穿通路,其延伸貫穿一封裝物; 一第一半導體晶粒,其延伸貫穿該封裝物,其中至少部分之該封裝物係位於該第一貫穿通路與該第一半導體晶粒之間;一保護層,其覆蓋該第一貫穿通路及該第一半導體晶粒,其中該保護層具有一第一高度垂直於該第一半導體晶粒之一主要表面;以及一第一可回銲材料,其延伸貫穿該保護層,該第一可回銲材料具有一第二高度垂直於該第一半導體晶粒之該主要表面,該第二高度係大於該第一高度。
- 如申請專利範圍第8項所述之半導體元件,還包括一第一封裝體接合該第一可回銲材料。
- 如申請專利範圍第8項所述之半導體元件,其中該保護層實體接觸該封裝物。
- 一製造一半導體元件之方法,其包括:封裝一第一半導體晶粒及一貫穿通路於一封裝物中,其中該封裝步驟將至少部分之封裝物置放於該第一半導體晶粒與該貫穿通路之間;置放一第一可回銲材料而電性連接該貫穿通路;以及在置放該第一可回銲材料後形成一保護層,以密封至少部分之該第一可回銲材料,其中該保護層曝露該第一可回銲材料。
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DE102015106053A1 (de) | 2016-07-28 |
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US10103132B2 (en) | 2018-10-16 |
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