CN103187388A - 封装的半导体器件及封装半导体器件的方法 - Google Patents

封装的半导体器件及封装半导体器件的方法 Download PDF

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CN103187388A
CN103187388A CN2012101919442A CN201210191944A CN103187388A CN 103187388 A CN103187388 A CN 103187388A CN 2012101919442 A CN2012101919442 A CN 2012101919442A CN 201210191944 A CN201210191944 A CN 201210191944A CN 103187388 A CN103187388 A CN 103187388A
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semiconductor device
contact pad
insulating barrier
moulding compound
encapsulation
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CN103187388B (zh
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林俊成
洪瑞斌
刘乃玮
茅一超
施婉婷
董簪华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了在半导体器件衬底上形成模塑料使晶圆级封装(WLP)中的扇出结构成为可能的机制。该机制包括覆盖包围接触焊盘的绝缘层的部分表面。该机制改善了封装件的可靠性和封装工艺的工艺控制。该机制还降低了界面分层的风险，以及在后续加工期间绝缘层的过度除气。该机制还改善了平坦化终点的确定。通过利用接触焊盘和绝缘层之间的保护层，可以降低铜的外扩散并且也可以改善接触焊盘和绝缘层之间的粘着性。本发明提供了封装的半导体器件及封装半导体器件的方法。

Description

封装的半导体器件及封装半导体器件的方法
相关申请的交叉参考
本申请涉及以下共同待决和普通转让的专利申请：于2011年9月8日提交的名称为“Packaging Methods and Structures Using a Die Attach Film(采用管芯接合膜的封装方法和结构)”的序列号13/228,244，将其全部内容并入本申请。
技术领域
本发明涉及半导体封装，具体而言，涉及封装的半导体器件及封装半导体器件的方法。
背景技术
半导体器件用于各种电子应用，诸如个人电脑、手机、数码相机、以及其他电子设备。通常通过在半导体衬底上方按顺序沉积绝缘或者介电层、导电层、和半导电层的材料，以及采用光刻图案化各种材料层以在其上形成电路元件和元件来制造半导体器件。
半导体产业通过不断减小最小部件尺寸来不断提高各种电子元件(例如，晶体管、二极管、电阻器、电容器等等)的集成密度，这容许将更多的元件集成到给定的区域中。在某些应用中，这些更小的电子元件同样需要比过去的封装件利用更少面积的更小的封装件。
因此，已经开始开发新的封装技术诸如晶圆级封装(WLP)，其中将集成电路(IC)设置在具有用于与IC和其他电气元件建立连接的布线的载具上。这些用于半导体的相对新型的封装技术面临制造挑战。
发明内容
一方面，本发明涉及一种封装的半导体器件，包括：接触焊盘，位于半导体管芯上；绝缘层，包围所述接触焊盘；以及模塑料，包围所述绝缘层，其中，所述模塑料与所述绝缘层的两个邻近的且非线性的表面相接触。
在所述的封装的半导体器件中，布线层设置在所述接触焊盘上并物理连接至所述接触焊盘，其中，所述布线层延伸到所述半导体管芯的边界之外。
在所述的封装的半导体器件中，包围所述接触焊盘的所述绝缘层具有薄部和厚部，并且其中，所述薄部的厚度处于约1μm至约30μm的范围内。
在所述的封装的半导体器件中，保护层位于所述接触焊盘和所述绝缘层之间。
在所述的封装的半导体器件中，所述保护层是铜扩散阻挡件。
在所述的封装的半导体器件中，所述保护层的厚度处于约50nm至约2μm的范围内。
在所述的封装的半导体器件中，所述保护层也位于所述绝缘层和下面的另一绝缘层之间。
在所述的封装的半导体器件中，所述保护层是介电材料并且包括选自由SiN、SiC、SiCN、SiCO、TEOS、SiO2或低-k电介质组成的组的材料。
在所述的封装的半导体器件中，所述介电材料也改善了所述接触焊盘和所述绝缘层之间的粘着性。
在所述的封装的半导体器件中，所述保护层是导电材料并且由选自由Ta、TaN、Ti、TiN、Co、和Mn组成的组的材料制成。
在所述的封装的半导体器件中，所述接触焊盘是铜柱并且在下面具有凸块下金属化层。
在所述的封装的半导体器件中，所述接触焊盘的厚度大于所述绝缘层的厚度。
另一方面，本发明还提供了一种封装的半导体器件，包括：接触焊盘，位于半导体管芯上；绝缘层，包围所述接触焊盘；保护层，其中，所述保护层位于所述接触焊盘和所述绝缘层之间；以及模塑料，包围所述绝缘层，其中，所述模塑料与所述绝缘层的两个邻近的且非线性的表面相接触。
又一个方面，本发明提供了一种封装半导体器件的方法，所述方法包括：提供半导体器件，其中，所述半导体器件具有接触焊盘；在所述半导体器件上方形成绝缘层，其中，所述接触焊盘的厚度大于所述绝缘层的厚度；形成模塑料以覆盖所述半导体器件以及位于所述半导体器件和相邻的半导体器件之间的间隔，其中，这两个半导体器件都位于载具晶圆上；以及通过去除位于所述接合焊盘上方的所述模塑料和所述绝缘层来平坦化所述半导体器件的表面。
所述的方法还包括：在所述半导体器件上方形成再分布层(RDL)，其中，将所述RDL连接至所述接触焊盘，并且其中，所述RDL延伸到所述半导体器件的边界之外。
所述的方法还包括：在所述接触焊盘和所述绝缘层之间形成保护层。
在所述的方法中，所述保护层的厚度处于约50nm至约2μm的范围内。
在所述的方法中，通过研磨实施平坦化所述表面。
在所述的方法中，所述接触焊盘是铜柱并且具有处于约1μm至约35μm范围内的厚度。
在所述的方法中，通过蚀刻去除未包围所述接触焊盘的所述保护层。
附图说明
为了更充分地理解本发明及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1A至图1H是根据一些实施例的在各个封装阶段的扇出晶圆级封装件(FO-WLP)中的半导体器件的剖视图。
图1I是根据一些实施例的图1H的封装的半导体器件的放大剖视图。
图2A至图2C是根据一些实施例的分别在图1B、图1C和图1D中描述的扇出晶圆级封装件(FO-WLP)中的半导体器件的一部分的放大剖视图。
图3A至图3B是根据一些实施例的在各个封装阶段的扇出晶圆级封装件(FO-WLP)中的半导体器件的顺序加工的剖视图。
图3C是根据一些实施例的封装的半导体器件的放大剖视图。
图4A至图4B是根据一些实施例的在各个封装阶段的扇出晶圆级封装件(FO-WLP)中的半导体器件的剖视图。
图4C是根据一些实施例的封装的半导体器件的放大剖视图。
图5A至图5B是根据一些实施例的在各个封装阶段的扇出晶圆级封装件(FO-WLP)中的半导体器件的剖视图。
除非另有说明，不同附图中对应的标号和符号通常指对应的部件。绘制附图用于清楚地示出实施例的相关方面，并且不必须按比例绘制。
具体实施方式
在下面详细论述了本发明实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅仅是制造和使用本发明的示例性具体方式，而不用于限制本发明的范围。
图1A至图1I是根据本发明实施例的在各个封装阶段的半导体器件的剖视图。首先参考图1A，提供了载具晶圆100。作为实例，载具晶圆100可以包含玻璃、氧化硅、氧化铝等等。载具晶圆100的厚度可以介于约几密耳至几十密耳之间，并且在一些实施例中可以包括约300mm的直径。载具晶圆100作为在封装半导体器件或者管芯104(参见图1B)期间加工的用于扇出的载具晶圆起作用，扇出意为超出半导体管芯边界之外的电连接。
在一些实施例中，在载具晶圆100上方形成管芯接合膜(DAF)102，如图1A中所示。DAF 102可以包含聚合物，并且在一些实施例中包含热塑性材料。DAF 102可以是液体，例如粘稠液体，该液体在应用时为液体但在室温下形成固体，以及可以在加热时变成半液体，并且在升高的温度下可以变成粘性的从而作为粘着剂起作用。
接下来，如图1B中所示，将多个管芯104接合至DAF 102。作为实例，根据管芯104的尺寸、载具晶圆100的尺寸、以及具体用途，可以将几十个管芯104或者几百个管芯104或者更多的管芯接合至DAF 102。在本文中，出于论述的目的，管芯104具有正面103a和背面103b。管芯104的正面103a在本文中也被称为第一面，以及背面103b在本文中也被称为第二面。管芯104包括先前已经在半导体衬底上制造的半导体器件或者集成电路。管芯104可以包括一层或多层电路和/或在其上形成的电子功能元件，并且可以包括例如(未示出)导线、通孔、电容器、二极管、晶体管、电阻器、电感器、和/或其他电气元件。在制造之后，将管芯104彼此分离开并且准备进行封装。例如，可以使用拾取和放置机将管芯104放置在载具晶圆100上的预定位置中。如图1B中所示，将管芯104的背面103b接合至DAF 102。
接下来，实施封装工艺以封装多个管芯104中的每一个。在如图1A至图1I所描述的一些实施例中，为了封装管芯104，首先，在多个管芯104上方以及在DAF 102的暴露部分的上方形成模塑料106，如图1C中所示。如所示，可以在载具晶圆100上方将模塑料106模制到管芯104和DAF 102上。模塑料106的顶面可以高于(如图1C中所示)、齐平于(如图1D中所示)、或者略微低于管芯104的顶面104a。如所示，模塑料106填充至多个管芯104之间的间隙中。下面将论述模塑形成工艺的更多细节。
接下来，可以实施平坦化工艺(诸如研磨工艺)平坦化多个管芯104的顶面104a，从而可以至少减少并且可能基本上消除管芯104的顶面104a中的任何不均匀。如果模塑料106包括位于管芯104的顶面104a上的部分，通过研磨工艺也去除了模塑料106的这些部分，如图1D中所示。因此，模塑料106的剩余部分的顶面106a与多个管芯104的顶面104a齐平。此外，还可以通过研磨工艺将多个管芯104的高度或厚度减小至预定的高度。
例如在管芯104的正面103a上，在多个管芯104的顶面104a上方形成布线层108，如图1E中所示。布线层108可以包括一个或多个再分布层(RDL)，将参考图1I在本文中对其作进一步论述。RDL层被一个或多个介电层包围。部分RDL可以延伸到管芯104的边界之外。结果，可以实现更好的连接性和设计灵活性。RDL使用于晶圆级封装(WLP)的扇出设计成为可能。
图1E中示出的结构包括例如位于包括多个管芯104的载具晶圆100上方的重建晶圆。在部分布线层108的上方形成多个焊球110，如图1F中所示。在制造和封装工艺的该阶段，可以例如通过实施电气和功能测试可选地对封装的管芯104进行测试。
在一些实施例中，封装的管芯104包括模塑料106、布线层108、焊球110、以及DAF 102。在其他实施例中，去除了DAF 102，从而封装的管芯包括模塑料106、布线层108和焊球110。
接下来，根据一些实施例，如图1G中所示，从封装的管芯104去除至少载具晶圆100。例如，在从封装的管芯104剥离(debonding)载具晶圆100的工艺期间，模塑料106和布线层108支撑管芯104。在图1A至图1I中示出的实施例中，如所示，DAF 102保留在管芯104的背面103b上。可选地，可以例如采用光(激光)或者热工艺在去除载具晶圆100时或者以分开的加工步骤去除DAF 102。
然后在分离线(singulation line)114处分离或者分开封装的管芯104，形成独立的封装的管芯104，在下文中也被称为封装的半导体器件120，如图1H中所示。在封装的半导体器件120内邻近管芯104的边缘在布线层108和DAF 102之间设置模塑料106，其保护管芯104的边缘。为了将封装的管芯104与邻近的封装的管芯104分离开，也如图1G中所示，可以对管芯104的正面103a上的焊球110施加带112。带112包括在分离工艺期间支撑封装的管芯104的切割带。然后从带112去除封装的半导体器件120，如图1H中所示。
图1I是根据一些实施例的图1H中示出的封装的半导体器件120的放大剖视图。图1I也示出了可以在去除载具晶圆100之后在DAF 102上方施加的可选带122。在一些实施例中，可选带122可以包括适合于用激光打标标记的标记带。在其他实施例中，DAF 102可以包括适合于例如用激光标记的材料，并且带122可以不包含在结构中。在形成焊球110之后，可以对管芯104实施测试，并且例如，可以对带122或者DAF 102进行标记以表明测试的结果。也可以出于其他各种原因在分离之前或者之后对封装的管芯104进行标记。
根据一些实施例，图1I还示出了管芯104和布线层108的更详细的视图。管芯104和布线层108的视图是示例性的；可选地，管芯104和布线层108可以包括其他结构、布局和/或设计。在示出的实施例中，管芯104包括包含硅或者其他半导体材料的衬底124。绝缘层126a和126b可以包含在衬底124上设置的钝化层。可以在衬底的导电部件(诸如金属焊盘127、插塞、通孔、或者导线)上方形成管芯104的接触焊盘128从而与衬底124的电气元件(未示出)形成电接触。接触焊盘128可以在形成绝缘层126c中，该绝缘层126c可以包含聚合物层或其他绝缘材料。
布线层108可以包括包含有聚合物或者其他绝缘材料的绝缘层132a和132b。如所示，可以在绝缘层132a和132b内形成RDL 130，其中部分RDL130与管芯104上的接触焊盘128形成电接触。如所示，可以在部分RDL 130和绝缘层132b上形成可选的凸块下金属化(UBM)结构(或层)134。UBM结构134有利于例如连接和形成焊球110。在于2011年9月8日提交的名称为“Packaging Methods and Structures Using a Die Attach Film(采用管芯接合膜的封装方法和结构)”的美国专利申请第13/228,244号中描述了封装半导体器件的方法的更多细节。
图2A是根据一些实施例的图1B的区域150的放大图。区域150是管芯104的一部分并且包括如图1I中描述的衬底124。如上所述，在衬底124中具有器件，该衬底124包含硅和/或其他半导体材料。在衬底124上方具有绝缘层126a，该绝缘层126a隔离并分开导电结构(未示出)。绝缘层126a可以包括未掺杂氧化硅、低介电常数(低-k)电介质、掺杂介电膜、或者其组合。在一些实施例中，低-k电介质的介电常数可以小于3.5。在其他一些实施例中，低-k电介质的介电常数可以小于2.5。
图2A示出了区域150还包括金属焊盘127，该金属焊盘127可以由铝或者其他适用材料制成。通过互连结构(未示出)将金属焊盘127连接至衬底124上的器件。在金属焊盘127上形成接触焊盘128’。在一些实施例中，金属焊盘128’由铜制成并且在金属焊盘127以及UBM层129(为了简明在图1I中未示出)的上方形成。UBM层129可以包括铜扩散阻挡件，其可以是钛层、氮化钛层、钽层、或者氮化钽层。UBM层129还可以包括种子层，其可以包括铜或者铜合金。然而，也可以包括其他金属，诸如银、金、铝、及其组合。
在一些实施例中，接触焊盘128’是铜柱并且通过电镀形成。绝缘层126b用于将接触焊盘128’和UBM层129的一部分与金属焊盘127隔离开。绝缘层126b可以由一个或多个介电层制成，该一个或多个介电层可以包括氧化物、氮化物、聚酰亚胺、绝缘聚合物、或者其他适用材料。绝缘层126c’覆盖绝缘层126b和接触焊盘128’。如上所述，绝缘层126c’可以包括聚合物层或者其他绝缘材料。可以用于绝缘层126c的示例性聚合物材料可以包括环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等等，然而也可以使用其他相对较软的(通常为有机的)介电材料。
在一些实施例中，在绝缘层126b上方测量的接触焊盘128的高度D’处于约1μm至约25μm的范围内。在绝缘层126b上方测量的绝缘层126c’的高度H’处于约1μm至约30μm的范围内。
图2B是根据一些实施例的图1C的区域150’的放大图。图2B示出了模塑料106覆盖管芯104。如在上面图1I中描述和示出的，将在模塑料106上方构建部分扇出结构，诸如RDL 130。根据一些实施例，模塑料106最初是液体形式并且在载具晶圆100上分散之后干燥。例如，模塑料106可以包括环氧树脂、树脂、二氧化硅填充物或者其他添加物。
图2C是根据一些实施例的图1D的区域150”的放大图。图2C示出已经通过平坦化工艺(诸如研磨)去除了部分的模塑料106、绝缘层126c、以及可能一部分的金属焊盘128，从而从接触焊盘128’的表面去除多余的材料并平坦化图2B的衬底表面。之后，根据一些实施例，如图1I中所示，然后将未完成的封装件(在载具晶圆100上具有图2C的结构)送至进行上面图1E至图1H中描述的其他封装工艺以制造封装的衬底。界面142’位于接触焊盘128’和介电层126c’之间。
对未完成的封装件(在载具晶圆100上具有图2C的结构)实施的包括安装球110的以下工艺操作可能对封装的管芯120施加大的应力。如图2C中所示，绝缘层126c’和模塑料106之间的界面141’是线性的、或者垂直的。在一些实施例中，线性界面141’相对较弱并且在应力作用下可能导致分层(delamination)。此外，当对图2B的衬底实施平坦化操作以去除部分的模塑料106和绝缘层126c’，以及可能一部分的接触焊盘128’时，平坦化工艺终点的确定可能是富有挑战性的。当被去除的材料从模塑料106变到绝缘层126c’以及然后变到接触焊盘128’时，可以通过检测由平坦化工具(诸如研磨机)承受的不同扭矩力来确定平坦化工艺的终点。在一些实施例中，通过由平坦化工具检测接触焊盘128’来确定终点。当平坦化工具需要识别两种不同类型的表面(绝缘层126c’和接触焊盘128’)的接合时，确定平坦化工艺的终点是富有挑战性的。
除了上面论述的问题外，绝缘层126c’的暴露表面333’在后续加工中在形成绝缘层132a和RDL 130期间可以释放化学物质。如上所述，绝缘层126c’可以由聚合物制成，该聚合物在等离子体工艺、溅射工艺、或者光刻胶灰化作用下可以分解。绝缘层126c’释放的化学物质可以重新沉积在接触焊盘128’和RDL 130之间的界面334’上并且导致界面电阻增加。由于至少这些问题，根据一些实施例，需要改进图2A至图2C中示出的形成模塑结构的机制以及它们的导致形成封装的半导体器件的后续结构。
根据一些实施例，图3A示出图1C的区域150’的更详细的剖视图。图3A的接触焊盘128”的高度D”高于图2A中的高度D’。在一些实施例中，高度D”处于约1μm至约35μm的范围内。绝缘层126”的高度H’处于约1μm至约30μm的范围内。绝缘层126c”的表面145低于接触焊盘128”的表面434。如果通过分配(诸如通过旋转涂布工艺)含有聚合物或者聚合物的前体的液体来形成绝缘层126c”，在接触焊盘128”上方形成绝缘层126c”的薄层126c*。在一些实施例中，薄层126c*的厚度处于约0.01μm至约3μm的范围内。上面已经描述了适合用于形成绝缘层126c”的示例性聚合物材料。在一些实施例中，然后实施固化工艺以驱除出膜中的水分或者溶剂。图3A示出模塑料106覆盖具有绝缘层126c”的管芯104。
图3B是根据一些实施例的图1D的区域150”的放大图。图3B示出诸如通过研磨已去除并平坦化了部分的模塑料106、位于接触焊盘128”上方的介电层126c”以及接触焊盘128”。根据一些实施例，然后将未完成的衬底封装件送至进行诸如图1E至1H中所描述的另外的封装工艺以制造封装的半导体器件。图3C示出根据一些实施例的封装的半导体器件120’的更详细的剖视图。
对于图3B中示出的结构，模塑料106和介电层126c”之间的界面141”不是单一的线性界面。相反，根据一些实施例，如图3C中所示，界面141”具有彼此连接的三段，即线性表面141A”、141B”、和141C”。界面141”在机械强度上比上面描述的单一的线性界面141’强，并且可以承受更多的应力而不分层。此外，在去除部分的模塑料106和介电层126c*以及可能一部分的接触焊盘128”的平坦化工艺期间，在接触焊盘128”上方仅有一薄层介电层126c*。与加工在接触焊盘128”上方不具有该薄层介电层126c*的结构相比，这使得确定平坦化的终点更加容易且更加准确。因为，一旦扭矩力由于平坦化工具接触介电层126c*而发生变化，平坦化工具将很快与接触焊盘128”接触。终点的确定将更加精确。例如，可以设置扭矩力变化之后的固定时间来停止平坦化工艺。此外，也大大降低了接触焊盘128”的界面334”上的界面电阻较高的风险。这是因为介电层126c”的暴露表面333”(相比于图2C中所述的表面333’)大大减少了。因此，介电层126c”释放的化学物质的量也大大减少了。因此，使介电层126c”释放的化学物质再沉积在界面334”上的风险最小化。
对于一些封装件，如图2C中所示，涉及到在接触焊盘128’和介电层126c’之间的界面142’(参见图2C)处的分层。另外，如果接触焊盘128’、128”包括铜，对于一些封装件，还可能涉及到接触焊盘128’、128”的金属扩散。结果，根据一些实施例，如图4A中所示，可以沉积保护层135以包围接触焊盘128”。保护层135可以由介电材料制成，该介电材料包括SiN、SiC、SiCN、SiCO、TEOS、SiO2、低-k电介质等等。例如，低-k电介质可以具有小于约3.5的介电常数。保护层135也改善了介电层126c”和接触焊盘128”之间的粘着性。在一些实施例中，保护层135的厚度处于约50nm至约2μm的范围内。根据一些实施例，形成介电层126c”和模塑料106的工艺与上面在图3A和图3B中所述的工艺相似。然后，去除模塑料106、介电层126c”和保护层135位于接触焊盘128”上方的部分。
图4B示出了根据一些实施例的在平坦化以去除位于接触焊盘128”上方的材料之后的结构的剖视图。保护层135覆盖接触焊盘128”的侧壁并且减少接触焊盘128”中的铜的外扩散。此外，保护层135也改善了接触焊盘128”和介电层126c”之间的粘着性。图4C示出了根据一些实施例的封装的半导体器件120”的剖视图。
在一些实施例中，保护层135’可以由足以阻止铜扩散的导电材料(诸如Ta、TaN、Ti、TiN、Co、Mn、或其组合)制成。图5A示出了根据一些实施例覆盖位于衬底124上的接触焊盘128”的侧壁的保护层135’。保护层135’未覆盖介电层126b的表面。在形成介电层126c”之前，通过蚀刻去除位于介电层126b表面上方的保护层135’。在一些实施例中，蚀刻工艺是干法等离子体工艺。然后，在衬底上沉积模塑料106。然后通过平坦化去除模塑料106、介电层126c*、保护层135’位于接触焊盘128”上方的部分。图5B示出了根据一些实施例的在平坦化操作之后的图5A的剖视图。
提供了在半导体器件衬底上形成模塑料以使晶圆级封装(WLP)中的扇出结构成为可能的机制。该机制包括覆盖包围接触焊盘的绝缘层的部分表面。该机制改善了封装件的可靠性和封装工艺的工艺控制。该机制还降低界面分层的风险以及在后续加工期间绝缘层的过多除气。该机制还改善了平坦化终点的确定。通过利用接触焊盘和绝缘层之间的保护层，可以减少铜的外扩散并且也可以改善接触焊盘和绝缘层之间的粘着性。
在一些实施例中，提供了一种封装的半导体器件。该封装的半导体器件包括位于半导体管芯上的接触焊盘；以及包围接触焊盘的绝缘层。该封装的半导体器件还包括包围绝缘层的模塑料，并且该模塑料与绝缘层的两个邻近的且非线性的表面相接触。
在一些其他实施例中，提供了一种封装的半导体器件。该封装的半导体器件包括位于半导体管芯上的接触焊盘；以及包围接触焊盘的绝缘层。该封装的半导体器件还包括保护层；并且该保护层位于接触焊盘和绝缘层之间。该封装的半导体器件还包括包围绝缘层的模塑料，并且该模塑料与绝缘层的两个邻近的且非线性的表面相接触。
在又一些其他实施例中，提供了一种封装半导体器件的方法。该方法包括提供半导体器件，并且该半导体器件具有接触焊盘。该方法还包括在半导体器件上方形成绝缘层，并且接触焊盘的厚度大于绝缘层的厚度。该方法还包括形成模塑料以覆盖半导体器件以及半导体器件和相邻的半导体器件之间的间隔。这两个半导体器件都位于载具晶圆上。此外，该方法包括通过去除位于接触焊盘上方的模塑料和绝缘层来平坦化半导体器件的表面。
尽管已经详细地描述了本发明的实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明的精神和范围的情况下，在其中进行各种改变、替换和更改。例如，本领域技术人员将很容易理解，本文描述的部件、功能、工艺、和材料可以发生改变并且仍在本发明的范围内。而且，本申请的范围并不仅限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明将很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种封装的半导体器件，包括：
接触焊盘，位于半导体管芯上；
绝缘层，包围所述接触焊盘；以及
模塑料，包围所述绝缘层，其中，所述模塑料与所述绝缘层的两个邻近的且非线性的表面相接触。
2.根据权利要求1所述的封装的半导体器件，其中，布线层设置在所述接触焊盘上并物理连接至所述接触焊盘，其中，所述布线层延伸到所述半导体管芯的边界之外。
3.根据权利要求1所述的封装的半导体器件，其中，包围所述接触焊盘的所述绝缘层具有薄部和厚部，并且其中，所述薄部的厚度处于约1μm至约30μm的范围内。
4.根据权利要求1所述的封装的半导体器件，其中，保护层位于所述接触焊盘和所述绝缘层之间。
5.根据权利要求1所述的封装的半导体器件，其中，所述接触焊盘是铜柱并且在下面具有凸块下金属化层。
6.根据权利要求1所述的封装的半导体器件，其中，所述接触焊盘的厚度大于所述绝缘层的厚度。
7.一种封装的半导体器件，包括：
接触焊盘，位于半导体管芯上；
绝缘层，包围所述接触焊盘；
保护层，其中，所述保护层位于所述接触焊盘和所述绝缘层之间；以及
模塑料，包围所述绝缘层，其中，所述模塑料与所述绝缘层的两个邻近的且非线性的表面相接触。
8.一种封装半导体器件的方法，所述方法包括：
提供半导体器件，其中，所述半导体器件具有接触焊盘；
在所述半导体器件上方形成绝缘层，其中，所述接触焊盘的厚度大于所述绝缘层的厚度；
形成模塑料以覆盖所述半导体器件以及位于所述半导体器件和相邻的半导体器件之间的间隔，其中，这两个半导体器件都位于载具晶圆上；以及
通过去除位于所述接合焊盘上方的所述模塑料和所述绝缘层来平坦化所述半导体器件的表面。
9.根据权利要求8所述的方法，还包括：
在所述半导体器件上方形成再分布层(RDL)，其中，将所述RDL连接至所述接触焊盘，并且其中，所述RDL延伸到所述半导体器件的边界之外。
10.根据权利要求8所述的方法，还包括：
在所述接触焊盘和所述绝缘层之间形成保护层。
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US20150187605A1 (en) 2015-07-02
US9000584B2 (en) 2015-04-07

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