CN105321912B - 用于激光标刻的金属焊盘 - Google Patents

用于激光标刻的金属焊盘 Download PDF

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Publication number
CN105321912B
CN105321912B CN201410848102.9A CN201410848102A CN105321912B CN 105321912 B CN105321912 B CN 105321912B CN 201410848102 A CN201410848102 A CN 201410848102A CN 105321912 B CN105321912 B CN 105321912B
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Prior art keywords
packaging part
laser labelling
pad
dielectric layer
redistribution lines
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CN105321912A (zh
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苏安治
陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

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Abstract

本发明提供了一种封装件，包括器件管芯、将器件管芯模制在其中的模制材料、以及位于器件管芯和模制材料上面的多条再分布线。激光标记焊盘与多条再分布线中的一条共面，其中，激光标记焊盘和该多条再分布线中的一条由相同的导电材料形成。聚合物层位于激光标记焊盘和多条再分布线上方。胶带附接在聚合物层上方。激光标记穿过胶带和聚合物层。激光标记延伸至激光标记焊盘的顶面。本发明还提供了形成封装件的方法。

Description

用于激光标刻的金属焊盘
优先权声明和交叉引用
本申请要求以下临时提交的美国专利申请的权益：2014年5月30日提交的标题为“Metal pad for Laser Marking”的美国专利申请第62/005,692号，并且与2014年2月27日提交的标题为“Laser Marking in Packages”的美国专利申请第14/192,341号相关，其全部内容结合于此作为参考。
技术领域
本发明涉及集成电路器件，更具体地，涉及用于激光标刻的金属焊盘。
背景技术
在集成电路的封装中，存在各种类型的封装方法和结构。例如，在传统的叠层封装件(POP)工艺中，顶部封装件接合至底部封装件。顶部封装件和底部封装件也可以具有封装在其中的器件管芯。通过采用PoP工艺，提高了封装件的集成水平。
在现有的PoP工艺中，首先形成底部封装件，底部封装件包括接合至封装衬底的器件管芯。模塑料模制在封装衬底上，其中，器件管芯模制在模塑料中。封装衬底还包括形成在其上的焊料球，其中，焊料球和器件管芯位于封装衬底的同一侧上。焊料球用于将顶部封装件连接至底部封装件。
发明内容
为了解决现有技术中存在的问题，本发明提供了一种封装件，包括：第一封装件，包括：器件管芯；模制材料，将所述器件管芯模制在其中；多条再分布线，位于所述器件管芯和所述模制材料上面；激光标记焊盘，与所述多条再分布线中的一条共面，其中，所述激光标记焊盘和所述多条再分布线中的一条由相同的导电材料形成；聚合物层，位于所述激光标记焊盘和所述多条再分布线上方；胶带，位于所述聚合物层上方；以及激光标记，穿过所述胶带和所述聚合物层，其中，所述激光标记延伸至所述激光标记焊盘的顶面。
在上述封装件中，其中，所述封装件还包括：通孔，穿过所述模制材料；以及金属迹线，将所述激光标记焊盘连接至所述通孔。
在上述封装件中，其中，所述封装件还包括：通孔，穿过所述模制材料；以及金属迹线，将所述激光标记焊盘连接至所述通孔，其中，所述通孔电接地。
在上述封装件中，其中，所述激光标记包括在所述聚合物层和所述胶带中形成的沟槽，并且其中，所述封装件还包括：第二封装件，位于所述第一封装件上方；焊料区，将所述第一封装件接合至所述第二封装件；以及底部填充物，位于所述第一封装件和所述第二封装件之间的间隙中，其中，设置在所述聚合物层和所述胶带中的沟槽中的所述底部填充物的一部分形成所述激光标记。
在上述封装件中，其中，所述封装件还包括：额外的激光标记焊盘；额外的激光标记，穿过所述胶带和所述聚合物层，其中，所述额外的激光标记延伸至所述额外的激光标记焊盘的顶面；以及金属迹线，互连所述激光标记焊盘和所述额外的激光标记焊盘，其中，所述金属迹线窄于所述激光标记焊盘和所述额外的激光标记。
在上述封装件中，其中，所述激光标记焊盘包括位于其中的多个狭槽，所述多个狭槽穿过所述激光标记焊盘。
在上述封装件中，其中，所述激光标记焊盘以及所述激光标记与所述器件管芯未对准。
根据本发明的另一方面，提供了一种封装件，包括：第一封装件，包括：至少一个第一介电层；第一多条再分布线，位于所述至少一个第一介电层中；器件管芯，位于所述第一多条再分布线上方并且电连接至所述第一多条再分布线；模制材料，将所述器件管芯模制在其中；通孔，穿过所述模制材料；至少一个第二介电层，位于所述器件管芯上方；第二多条再分布线，位于所述至少一个第二介电层中，其中，所述第二多条再分布线中的一条通过所述通孔电连接至所述第一多条再分布线中的一条；金属焊盘，位于所述至少一个第二介电层中，其中，所述金属焊盘连接至所述通孔；第三介电层，位于所述至少一个第二介电层上面；以及激光标记，从所述第三介电层的顶面延伸至所述金属焊盘的顶面；以及第二封装件，位于所述第一封装件上方并且接合至所述第一封装件。
在上述封装件中，其中，所述封装件还包括：底部填充物，位于所述第一封装件和所述第二封装件之间的间隙中，其中，所述底部填充物的一部分填充所述激光标记。
在上述封装件中，其中，所述封装件还包括：底部填充物，位于所述第一封装件和所述第二封装件之间的间隙中，其中，所述底部填充物的一部分填充所述激光标记，其中，所述底部填充物与所述金属焊盘的顶面物理接触。
在上述封装件中，其中，所述金属焊盘电接地。
在上述封装件中，其中，所述封装件还包括位于所述第三介电层上面的胶带，其中，所述激光标记穿过所述胶带。
在上述封装件中，其中，所述封装件还包括位于所述第三介电层上面的胶带，其中，所述激光标记穿过所述胶带，其中，所述胶带和所述第三介电层由不同的材料形成。
在上述封装件中，其中，所述封装件还包括环绕所述金属焊盘的密封环，其中，所述密封环和所述金属焊盘位于相同的金属层中，并且其中，所述密封环是电浮置的。
根据本发明的又一方面，提供了一种形成封装件的方法，包括：形成第一封装件，所述第一封装件包括：至少一个第一介电层；第一多条再分布线，位于所述至少一个第一介电层中；器件管芯，位于所述第一多条再分布线上方并且电连接至所述第一多条再分布线；模制材料，将所述器件管芯模制在其中；通孔，穿过所述模制材料；至少一个第二介电层，位于所述器件管芯上方；第二多条再分布线，位于所述至少一个第二介电层中，其中，所述第二多条再分布线通过所述通孔电连接至所述第一多条再分布线；以及金属焊盘，位于所述至少一个第二介电层中；在所述至少一个第二介电层上面形成聚合物层；将胶带附接在所述聚合物层上方；以及实施激光标刻以在所述聚合物层和所述胶带中形成激光标记，所述金属焊盘的部分暴露于所述激光标记。
在上述方法中，其中，所述方法还包括：在所述聚合物层和所述胶带中形成开口以暴露多个金属焊盘；以及形成延伸到所述开口内的焊料区以连接到所述多个金属焊盘。
在上述方法中，其中，所述方法还包括：将第二封装件接合至所述第一封装件；以及将底部填充物填充到所述第一封装件和所述第二封装件之间的间隙内，其中，所述底部填充物设置在所述激光标记内。
在上述方法中，其中，所述方法还包括：将第二封装件接合至所述第一封装件；以及将底部填充物填充到所述第一封装件和所述第二封装件之间的间隙内，其中，所述底部填充物设置在所述激光标记内，其中，所述底部填充物与所述金属焊盘物理接触。
在上述方法中，其中，所述金属焊盘使所述激光标刻中使用的激光束停止。
在上述方法中，其中，所述金属焊盘通过金属部件电连接至所述通孔。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图7示出了根据一些实施例的封装件在形成中的中间阶段的截面图；
图8示出了根据一些实施例的封装件的顶视图，其中，多个激光标记焊盘彼此隔离；
图9示出了根据一些实施例的封装件的顶视图，其中，激光标记焊盘连接至通孔；
图10示出了根据一些实施例的封装件的顶视图，其中，激光标记和相应的激光标记焊盘与封装件中的器件管芯未对准；
图11示出了根据一些实施例的封装件的顶视图，其中，多个激光标记形成在大激光标记焊盘上方；以及
图12示出了根据一些实施例的封装件的顶视图，其中，大激光标记焊盘包括多个狭槽。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，本文可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例，提供了封装件以及在封装件中形成激光标记的方法。讨论了实施例的变化。贯穿各个视图和说明性实施例，相同的参考标号用于标示相同的元件。
图1示出了封装件100的截面图。根据本发明的一些实施例，封装件100包括器件管芯102，器件管芯102的前侧朝下并且接合至再分布线(RDL)112。在可选实施例中，封装件100包括一个以上的器件管芯。器件管芯102可以包括半导体衬底108和位于半导体衬底108的前表面(朝下的表面)上的集成电路器件104(例如，诸如有源器件，其可以包括金属氧化物半导体(MOS)晶体管或二极管)。器件管芯102可以是诸如中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯等的逻辑管芯。贯穿本发明的描述，图1中的器件管芯102的朝下的一侧称为器件管芯102的前侧，而图1中的器件管芯102的朝上的一侧称为器件管芯102的后侧。半导体衬底108的后表面108A也是器件管芯102的后表面。
器件管芯102模制在模制材料120中，模制材料120环绕器件管芯102。模制材料120可以是模塑料、模制底部填充物、树脂等。模制材料120的底面120A可以与器件管芯102的底端齐平。模制材料120的顶面120B可以与半导体衬底108的后表面108A齐平或高于半导体衬底108的后表面108A。根据本发明的一些实施例，半导体衬底108的后表面108A与管芯附接薄膜110重叠并且接触，管芯附接薄膜110是将器件管芯102附接至上面的介电层118的介电薄膜。器件管芯102还包括与RDL 112接触并且接合至RDL 112的金属柱/焊盘106(例如，金属柱/焊盘106可以包括铜柱)。金属柱106可以嵌入在器件管芯102的表面介电层(未标记)中。
封装件100包括位于器件管芯102下面的RDL 112和位于器件管芯102上面的RDL116。由于RDL 112位于器件管芯102的前侧上，所以RDL 112也称为前侧RDL。由于RDL 116位于器件管芯102的后侧上，所以RDL 116也称为后侧RDL。前侧RDL 112形成在一个或多个介电层114中，而后侧RDL 116形成在一个或多个介电层118中。虽然图1示出存在一层后侧RDL116和多层前侧RDL 112，但是，应该理解，构造RDL 112和116的层的数量由布线需求确定并且可以与示出的不同。RDL 112和116可以由铜、铝、镍、钛、钽、它们的合金和/或它们的多层形成。
根据本发明的一些实施例，介电层114和118由诸如聚合物的有机材料形成，聚合物可以进一步包括聚苯并恶唑(PBO)、苯并环丁烯(BCB)、聚酰亚胺、焊料掩模等。在可选实施例中，介电层114和118由诸如氧化硅、氮化硅、氮氧化硅等的无机材料形成。此外，一些介电层114和118可以是包括由不同材料形成的多个子层的复合层。例如，一个示例性介电层114或118可以包括氧化硅层和氮化硅层。
根据本发明的一些实施例，RDL 116和介电层118中的每个层的形成均包括：使用物理汽相沉积(PVD)形成毯状晶种层(未示出)，形成并图案化光刻胶(未示出)以覆盖毯状晶种层的一些部分，在光刻胶中的开口中镀RDL，以及然后去除光刻胶并且蚀刻晶种层的之前由去除的光刻胶覆盖的部分。
通孔122形成为穿过模制材料120。根据本发明的一些实施例，通孔122具有与模制材料120的顶面120B齐平的顶面和与模制材料120的底面120A齐平的底面。通孔122将前侧RDL 112电连接至后侧RDL 116。通孔122也可以与前侧RDL 112和后侧RDL 116物理接触。可以通过形成其中具有开口的图案化掩模(未示出)以及在图案化掩模中的开口中镀通孔122来形成通孔122。通孔122可以包括铜、铝、钛、镍、钯或它们的合金。
如图8至图12所示，通孔122可以形成为接近封装件100的外围，但是通孔122也可以形成在封装件100的任何其他位置处。根据本发明的一些实施例，通孔122可以与环绕激光标记焊盘128的环形件对准。
由非焊料金属材料形成的电连接件124形成在封装件100的底面处。根据本发明的一些实施例，电连接件124包括凸块下金属层(UBM)或金属焊盘。在可选实施例中，电连接件124包括诸如铜柱的金属柱。在整个说明书中，电连接件124是金属焊盘124，但是它们可以具有其他形式。金属焊盘124可以包括铜、铝、钛、镍、钯、金或它们的多层。如图1所示，根据本发明的一些实施例，金属焊盘124的底面突出于底部介电层114的底面之外。在可选实施例中，金属焊盘124的底面与底部介电层114的底面共面。焊料区126可以附接至金属焊盘124的底面。
在器件管芯102的后侧上，形成诸如RDL 116的导电部件(包括金属迹线、金属焊盘和金属通孔)。根据本发明的一些实施例，存在通过多个通孔互连的多层RDL 116。根据可选实施例，存在单层RDL 116。
还参照图1，形成金属焊盘128。由于金属焊盘128用于形成激光标记，此后金属焊盘128称为激光标记焊盘。根据本发明的一些实施例，激光标记焊盘128形成在RDL 116的顶层中。根据可选实施例，激光标记焊盘128形成在RDL层中而不是顶层中。激光标记焊盘128可以是电浮置的。可选地，激光标记焊盘128通过金属迹线144电连接至诸如RDL 116和/或通孔122的其他导电部件，金属迹线144是RDL 116的一部分。例如，激光标记焊盘128可以连接至电接地。激光标记焊盘128与RDL 116同时形成在相同的金属层中。
在一些示例性实施例中，形成密封环130以环绕激光标记焊盘128，其中，图8中可以找到示例性密封环130。如图1所示，密封环130与激光标记焊盘128形成在相同的金属层中。根据本发明的一些实施例，密封环130形成在单层RDL 116中。在可选实施例中，密封环130延伸到多层RDL 116内。密封环130可以是电浮置的并且可以由介电材料完全包围。在可选实施例中，密封环130电连接至诸如RDL 116和/或通孔122的其他导电部件。当形成激光标记焊盘128时，可以同时形成密封环130。因此，密封环130、RDL 116和激光标记焊盘128可以由相同的材料形成并且具有相同的组分。可选地，不形成环绕激光标记焊盘128的密封环。
根据一些实施例，激光标记焊盘128和密封环130的底面高于管芯附接薄膜110的顶面和模制材料120的顶面120B。一个介电层118(图1中标记为118A)形成在激光标记焊盘128和密封环130的下方，相应的介电层118A的顶面与激光标记焊盘128的底面接触。介电层118A的底面可以与管芯附接薄膜110的顶面和模制材料120的顶面接触。
也如图1所示，形成介电层131。介电层131的底部与介电层118的顶面接触。此外，介电层131的底面也与RDL 116和激光标记焊盘128的顶面接触。根据本发明的一些示例性实施例，介电层131由聚合物形成，并且因此在整个说明书中称为聚合物层131。应该理解，介电层131也可以由非聚合物材料形成。用于形成聚合物层131的示例性候选材料包括但不限于PBO、BCB、聚酰亚胺等。
参照图2，胶带133层压在聚合物层131上并且可以通过热固化附接至聚合物层131。胶带133可以为下面的封装件结构提供保护和加固。胶带133也阻挡光透入下面的封装件结构内，从而降低光的不利影响。胶带133也有助于在封装件的后续切割工艺期间减少碎屑。根据一些实施例，胶带133和聚合物层131可以由不同的材料形成。
参照图3，实施激光标刻以在胶带133和介电层131中形成激光标记132，其中，激光标记132包括在胶带133和介电层131中形成的沟槽。使用激光束134实施激光标刻，激光束134烧毁并去除胶带133和介电层131的部分。根据本发明的一些实施例，胶带133和介电层131的烧毁部分与激光标记焊盘128重叠。激光标记焊盘128用作保护层，其中，激光束134不能够穿过激光标记焊盘128损坏激光标记焊盘128下方的层和器件。因此，激光标记焊盘128具有防止激光束134到达下面的器件管芯102和下面的RDL 116(如果存在的话)的功能。
激光标记132可以包括字母、数字、图形或可以用于识别目的的任何其他符号。例如，图8示出了包括字母和数字的一些示例性激光标记132。激光标记132可以用于识别产品、制造顺序、相应封装件的批号、或用于追踪相应封装件的任何其他信息。在激光标刻之后，通过形成激光标记132的沟槽暴露激光标记焊盘128的一些部分。
图4示出了胶带133和介电层131的一些部分的去除以暴露金属焊盘116’，金属焊盘116’可以是RDL 116的部分。结果，在介电层131和胶带133中形成开口136。根据一些示例性实施例，通过使用激光束烧毁胶带133和介电层118来实现开口136的形成。根据可选实施例，通过光刻工艺形成开口136，其中，蚀刻胶带133和介电层131。在产生的结构中，开口136和激光标记132的底面可以是基本上共面的，也就是说，与激光标记焊盘128和RDL焊盘116’的顶面在同一水平面上。
图5示出了焊料区138的形成。根据本发明的一些实施例，实施植球步骤以使焊料球落入开口136(图4)中，随后实施回流工艺以回流焊料球，从而形成焊料区138。焊料区138包括与RDL焊盘116’的顶面接触的部分并且也可以包括开口136外部的一些部分。在可选实施例中，跳过焊料区形成步骤。相反，如图6所示，由附接至封装件组件200的焊料区提供用于形成焊料区138’(图6)的焊料。
图6示出了封装件200与封装件100的接合。根据本发明的一些实施例，封装件200包括封装衬底202和接合至封装衬底202的器件管芯204。可以通过引线接合、倒装芯片接合等来实现器件管芯204与封装衬底202的接合。根据一些示例性实施例，器件管芯204包括诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。
在接合工艺中，回流如图5所示的焊料区138以形成如图6所示的焊料区138’。在接合工艺之后，在封装件200和封装件100之间存在间隙，并且激光标记132暴露于间隙。
参照图7，根据本发明的一些实施例，在接合封装件200之后，将底部填充物140填充到封装件100和封装件200之间的间隙内。在这些实施例中，激光标记132(图4)的沟槽也填充有底部填充物140。因此，激光标记132的沟槽中的底部填充物140的部分可选地称为激光标记132’。激光标记132’可以从胶带133的顶面延伸至激光标记焊盘128的顶面。此外，激光标记132’可以与激光标记焊盘128的顶面物理接触。在可选实施例中，在封装件100和封装件200之间的间隙内未填充底部填充物，并因此在最终的封装件中(例如，在使用和导通封装件时)，激光标记132仍为沟槽(参照图6)。在这些实施例中，激光标记焊盘128的一些部分可以通过激光标记132暴露于空气。
在如图7所示的封装件中，激光标记焊盘128可以被包括介电层118和131的介电材料以及底部填充物140完全包围并且与包括介电层118和131的介电材料以及底部填充物140接触。
图8示出了根据一些实施例的封装件100的顶视图。如图8所示，激光标记132可以与激光标记焊盘128重叠，其中，所有激光标记132均形成在激光标记焊盘128上。根据本发明的一些实施例，形成密封环130，并且密封环130形成环绕激光标记焊盘128的环形件。在一些示例性实施例中，存在彼此物理分离的多个离散的激光标记焊盘128。根据一些实施例，离散的激光标记焊盘128也可以彼此电隔离。可以根据封装件100的尺寸和激光标记132的期望尺寸选择激光标记焊盘128的尺寸。例如，激光标记焊盘的长度“a”和宽度“b”可以在约1mm至约5mm的范围内，并且相邻的激光标记焊盘128之间的间距“S”可以大于约500μm。然而，应该理解，在整个说明书中列举的值仅是实例并且可以改变为不同的值。
如图7和图8的组合所示，根据一些示例性实施例，离散的激光标记焊盘128的每个部分均完全包围在介电材料中，在这些示例性实施例中，离散的激光标记焊盘128的表面不与导电材料接触。例如，如图7所示，离散的激光标记焊盘128的底面和侧壁表面与介电层118接触。离散的激光标记焊盘128的顶面与聚合物层131接触。此外，离散的激光标记焊盘128的顶面的一些部分与底部填充物140(如在图7中的实施例中)或空气(如在图6中的实施例中)接触。
在激光标刻期间，产生热量并且热量导致不期望地烧毁激光标记焊盘128周围的介电层，从而引起介电层118和RDL 116的变形以及其他可靠性问题。因此，期望激光标记焊盘128中产生的热量快速耗散至其他区域和部件，从而使得激光标记焊盘128的温度限制在层118、131和133的燃烧/变形温度之下。在一些实施例中，密封环130可以耗散热量。为了提高散热效率，密封环130可以具有较大的宽度W1，例如大于约20μm，以提供低热电阻，从而使得密封环130的过热部分可以将热量快速耗散至密封环130的其他部分。在可选实施例中，不形成密封环130。
此外，如在图9中示出的实施例中，为了提高散热效率，激光标记焊盘128的一些或全部通过金属迹线142互连。因此，当实施激光标刻以在激光标记焊盘128中的一个上方形成激光标记132时，可以将热量耗散至相邻的激光标记焊盘128。根据一些示例性实施例，金属迹线142的宽度W2大于约20μm或为100μm以上以提供更好的散热。宽度W2还小于激光标记焊盘128的宽度b。
除了金属迹线142之外，可以形成额外的金属迹线144以进一步将热量耗散至附近的部件。例如，如图9所示，金属迹线144将金属焊盘128连接至一些通孔122(标记为122A)，从而使得在激光标刻工艺期间，通孔122A用作散热部件以帮助降低激光标记焊盘128的温度。在图7中也可以找到示例性金属迹线144，图7示出，激光标记焊盘128中的一个连接至通孔122A。根据一些实施例，通孔122A连接至电接地。在可选实施例中，通孔122A是用于运载缓变信号(具有低频率，例如小于约1MHz或1kHz)的信号通孔。
在图8和图9中，激光标记焊盘128和激光标记132直接形成在器件管芯102上方并且与器件管芯102重叠。如图10所示，在可选实施例中，图10也示出了封装件100的顶视图，激光标记焊盘128和激光标记132与器件管芯102不对准。在这些实施例中，由于激光标记焊盘128和器件管芯102之间的增大的距离，从激光标记焊盘128耗散的热量不太可能不利地影响器件管芯102。
图11和图12示出了根据额外的实施例的封装件100的顶视图，其中，激光标记焊盘128是占据封装件100的有效面积的大激光标记焊盘，其中，激光标记焊盘128可以具有形成在其上的多个激光标记132。如图11所示，在这些实施例中，大激光标记焊盘128可以是固体金属焊盘。在如图12所示的实施例中，又存在单个激光标记焊盘128，在激光标记焊盘128中形成有多个狭槽146。狭槽146穿过激光标记焊盘128。多个狭槽146帮助减小封装件100中的应力，其中，由于激光标记焊盘128和周围的介电材料118、131和140的热膨胀系数(CTE)之间的差别，所以产生了应力。由于激光标记焊盘128的较大面积，所以图11和图12中的实施例具有激光标刻中的良好的热耗散的有利特征。
可以调整激光标记焊盘128和狭槽146的面积，从而使得激光标记焊盘128的金属层中的金属密度不会过高。金属密度是所有金属部件(包括RDL 116和激光标记焊盘128)的总面积除以封装件100的面积的比率。在一些示例性实施例中，将金属密度控制为低于约50％。
本发明的实施例具有若干有利特征。通过形成激光标记焊盘，激光标记焊盘控制激光标刻的深度。防止封装件中的器件管芯和再分布线受到由激光标刻引起的可能的损坏。由于可以在形成封装件的再分布线的同时形成激光标记焊盘，所以本发明的实施例不引起额外的制造成本。
根据本发明的一些实施例，一种封装件包括器件管芯、将器件管芯模制在其中的模制材料、以及位于器件管芯和模制材料上面的多条再分布线。激光标记焊盘与多条再分布线中的一条共面，其中，激光标记焊盘和该多条再分布线中的一条由相同的导电材料形成。胶带附接在聚合物层上方。激光标记穿过胶带和聚合物层。激光标记延伸至激光标记焊盘的顶面。
根据本发明的可选实施例，一种封装件包括第一封装件和第二封装件。第一封装件包括至少一个第一介电层、位于至少一个第一介电层中的第一多条再分布线、位于第一多条再分布线上方并且电连接至第一多条再分布线的器件管芯、将器件管芯模制在其中的模制材料、穿过模制材料的通孔、位于器件管芯上方的至少一个第二介电层、以及位于至少一个第二介电层中的第二多条再分布线。第二多条再分布线中的一条通过通孔电连接至第一多条再分布线中的一条。该封装件还包括位于至少一个第二介电层中的金属焊盘，其中，金属焊盘连接至通孔，第三介电层位于至少一个第二介电层上面，激光标记从第三介电层的顶面延伸至金属焊盘的顶面，而第二封装件位于第一封装件上方并且接合至第一封装件。
根据本发明的又可选实施例，一种方法包括：形成封装件，封装件包括至少一个第一介电层、位于至少一个第一介电层中的第一多条再分布线、位于第一多条再分布线上方并且电连接至第一多条再分布线的器件管芯、将器件管芯模制在其中的模制材料、穿过模制材料的通孔、位于器件管芯上方的至少一个第二介电层、位于至少一个第二介电层中的第二多条再分布线，其中第二多条再分布线通过通孔电连接至第一多条再分布线，以及位于至少一个第二介电层中的金属焊盘。在至少一个第二介电层上面形成聚合物层，将胶带附接至聚合物层上方。该方法还包括实施激光标刻以在聚合物层和胶带中形成激光标记，金属焊盘的部分暴露于激光标记。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种封装件，包括：
第一封装件，包括：
器件管芯；
模制材料，将所述器件管芯模制在其中；
多条再分布线，位于所述器件管芯和所述模制材料上面；
激光标记焊盘，与所述多条再分布线中的一条共面，其中，所述激光标记焊盘和所述多条再分布线中的一条由相同的导电材料形成；
聚合物层，位于所述激光标记焊盘和所述多条再分布线上方；
胶带，位于所述聚合物层上方；以及
激光标记，穿过所述胶带和所述聚合物层，其中，所述激光标记延伸至所述激光标记焊盘的顶面。
2.根据权利要求1所述的封装件，还包括：
通孔，穿过所述模制材料；以及
金属迹线，将所述激光标记焊盘连接至所述通孔。
3.根据权利要求2所述的封装件，其中，所述通孔电接地。
4.根据权利要求1所述的封装件，其中，所述激光标记包括在所述聚合物层和所述胶带中形成的沟槽，并且其中，所述封装件还包括：
第二封装件，位于所述第一封装件上方；
焊料区，将所述第一封装件接合至所述第二封装件；以及
底部填充物，位于所述第一封装件和所述第二封装件之间的间隙中，其中，设置在所述聚合物层和所述胶带中的沟槽中的所述底部填充物的一部分形成所述激光标记。
5.根据权利要求1所述的封装件，还包括：
额外的激光标记焊盘；
额外的激光标记，穿过所述胶带和所述聚合物层，其中，所述额外的激光标记延伸至所述额外的激光标记焊盘的顶面；以及
金属迹线，互连所述激光标记焊盘和所述额外的激光标记焊盘，其中，所述金属迹线窄于所述激光标记焊盘和所述额外的激光标记。
6.根据权利要求1所述的封装件，其中，所述激光标记焊盘包括位于其中的多个狭槽，所述多个狭槽穿过所述激光标记焊盘。
7.根据权利要求1所述的封装件，其中，所述激光标记焊盘以及所述激光标记与所述器件管芯未对准。
8.一种封装件，包括：
第一封装件，包括：
至少一个第一介电层；
第一多条再分布线，位于所述至少一个第一介电层中；
器件管芯，位于所述第一多条再分布线上方并且电连接至所述第一多条再分布线；
模制材料，将所述器件管芯模制在其中；
通孔，穿过所述模制材料；
至少一个第二介电层，位于所述器件管芯上方；
第二多条再分布线，位于所述至少一个第二介电层中，其中，所述第二多条再分布线中的一条通过所述通孔电连接至所述第一多条再分布线中的一条；
金属焊盘，位于所述至少一个第二介电层中，其中，所述金属焊盘连接至所述通孔；
第三介电层，位于所述至少一个第二介电层上面；以及
激光标记，从所述第三介电层的顶面延伸至所述金属焊盘的顶面；以及
第二封装件，位于所述第一封装件上方并且接合至所述第一封装件。
9.根据权利要求8所述的封装件，还包括：
底部填充物，位于所述第一封装件和所述第二封装件之间的间隙中，其中，所述底部填充物的一部分填充所述激光标记。
10.根据权利要求9所述的封装件，其中，所述底部填充物与所述金属焊盘的顶面物理接触。
11.根据权利要求8所述的封装件，其中，所述金属焊盘电接地。
12.根据权利要求8所述的封装件，还包括位于所述第三介电层上面的胶带，其中，所述激光标记穿过所述胶带。
13.根据权利要求12所述的封装件，其中，所述胶带和所述第三介电层由不同的材料形成。
14.根据权利要求8所述的封装件，还包括环绕所述金属焊盘的密封环，其中，所述密封环和所述金属焊盘位于相同的金属层中，并且其中，所述密封环是电浮置的。
15.一种形成封装件的方法，包括：
形成第一封装件，所述第一封装件包括：
至少一个第一介电层；
第一多条再分布线，位于所述至少一个第一介电层中；
器件管芯，位于所述第一多条再分布线上方并且电连接至所述第一多条再分布线；
模制材料，将所述器件管芯模制在其中；
通孔，穿过所述模制材料；
至少一个第二介电层，位于所述器件管芯上方；
第二多条再分布线，位于所述至少一个第二介电层中，其中，所述第二多条再分布线通过所述通孔电连接至所述第一多条再分布线；以及金属焊盘，位于所述至少一个第二介电层中；
在所述至少一个第二介电层上面形成聚合物层；
将胶带附接在所述聚合物层上方；以及
实施激光标刻以在所述聚合物层和所述胶带中形成激光标记，所述金属焊盘的部分暴露于所述激光标记。
16.根据权利要求15所述的方法，还包括：
在所述聚合物层和所述胶带中形成开口以暴露多个金属焊盘；以及
形成延伸到所述开口内的焊料区以连接到所述多个金属焊盘。
17.根据权利要求15所述的方法，还包括：
将第二封装件接合至所述第一封装件；以及
将底部填充物填充到所述第一封装件和所述第二封装件之间的间隙内，其中，所述底部填充物设置在所述激光标记内。
18.根据权利要求17所述的方法，其中，所述底部填充物与所述金属焊盘物理接触。
19.根据权利要求15所述的方法，其中，所述金属焊盘使所述激光标刻中使用的激光束停止。
20.根据权利要求15所述的方法，其中，所述金属焊盘通过金属部件电连接至所述通孔。
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