US9401308B2 - Packaging devices, methods of manufacture thereof, and packaging methods - Google Patents

Packaging devices, methods of manufacture thereof, and packaging methods Download PDF

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Publication number
US9401308B2
US9401308B2 US13/934,562 US201313934562A US9401308B2 US 9401308 B2 US9401308 B2 US 9401308B2 US 201313934562 A US201313934562 A US 201313934562A US 9401308 B2 US9401308 B2 US 9401308B2
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Prior art keywords
substrate
ppi
conductive bump
molding material
coupling
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US13/934,562
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US20140264846A1 (en
Inventor
Hsien-Wei Chen
Tsung-Yuan Yu
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US201361777709P priority Critical
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US13/934,562 priority patent/US9401308B2/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, HSIEN-WEI, TU, TSUNG-YUAN
Priority claimed from US13/939,966 external-priority patent/US9287143B2/en
Priority claimed from DE201310109531 external-priority patent/DE102013109531A1/en
Priority claimed from KR1020130149954A external-priority patent/KR101589796B1/en
Priority claimed from US14/198,262 external-priority patent/US9368398B2/en
Publication of US20140264846A1 publication Critical patent/US20140264846A1/en
Publication of US9401308B2 publication Critical patent/US9401308B2/en
Application granted granted Critical
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/206Length ranges
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H01L2924/20Parameters
    • H01L2924/207Diameter ranges

Abstract

Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater.

Description

REFERENCE TO RELATED APPLICATIONS

This application relates to the following co-pending and commonly assigned patent applications: Ser. No. 13/349,405, filed Jan. 12, 2012, entitled “Package on Package Interconnect Structure;” Ser. No. 13/751,289, filed Jan. 28, 2013, entitled “System and Method for an Improved Fine Pitch Joint;” Ser. No. 13/838,748, filed Mar. 15, 2013, entitled “Interconnect Structures and Methods of Forming Same;” Ser. No. 13/868,554, filed Apr. 23, 2013, entitled “Apparatus and Method for Wafer Separation;” Ser. No. 13/913,599, filed Jun. 10, 2013, entitled “Interconnect Joint Protective Layer Apparatus and Method;” Ser. No. 13/914,426, filed Jun. 10, 2013, entitled “Interconnect Structures and Methods of Forming Same” and Ser. No. 13/939,966, filed Jul. 11, 2013, entitled “Apparatus and Method for Package Reinforcement.”

This application claims the benefit of U.S. Provisional Application No. 61/777,709, filed on Mar. 12, 2013, and entitled “Packaging Devices, Methods of Manufacture Thereof, and Packaging Device Design Methods,” which application is incorporated herein by reference.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged separately, in multi-chip modules, or in other types of packaging, for example.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components such as integrated circuit dies also require smaller packages that utilize less area than packages of the past, in some applications.

One type of smaller packages for semiconductor devices that has been developed are wafer level packages (WLPs), in which integrated circuits are packaged in packages that typically include a redistribution layer (RDL) or post passivation interconnect (PPI) that is used to fan-out wiring for contact pads of the package so that electrical contacts can be made on a larger pitch than contact pads of the integrated circuit. WLPs are often used to package integrated circuits (ICs) demanding high speed, high density, and greater pin count, as examples.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view illustrating a portion of a packaging device in accordance with some embodiments of the present disclosure;

FIG. 2 is a cross-sectional view illustrating a portion of a packaging device in accordance with other embodiments of the present disclosure;

FIG. 3 is a cross-sectional view illustrating a portion of a packaging device in accordance with yet other embodiments of the present disclosure;

FIG. 4 is a cross-sectional view of a packaging device including the portions of the packaging devices shown in FIGS. 1, 2, and 3 in accordance with some embodiments; and

FIG. 5 is a flow chart illustrating a method of manufacturing a packaging device in accordance with some embodiments.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of some of the embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

Some embodiments of the present disclosure are related to packaging devices, methods of manufacture thereof, and design methods for packaging devices for semiconductor devices. Novel packaging devices will be described herein that have an optimized amount of molding thickness and optimized contact pad widths that reduce stress and strain on conductive bumps of the packaging devices, resulting in packages with improved reliability.

FIG. 1 is a cross-sectional view illustrating a portion 130 of a packaging device in accordance with some embodiments of the present disclosure. The packaging device comprises a WLP 100 in some embodiments. The packaging device includes a first substrate 102 and a second substrate 126 coupled to the first substrate 102 by a conductive bump 120. Only one conductive bump 120 is shown; however, in some embodiments, the packaging device includes a plurality of the conductive bumps 120 (see FIG. 4). A width B of contact pads 128 disposed on the second substrate 126 and a thickness h of a molding material 124 disposed on the first substrate 102 are optimized in accordance with some embodiments of the present disclosure, in order to reduce stress on the conductive bump 120 and other portions of the packaging device, to be described further herein.

To manufacture the packaging device, the first substrate 102 is provided. The first substrate 102 may comprise silicon, other types of bulk semiconductor material, or other materials, as examples. The first substrate 102 may include one or more integrated circuits formed thereon, not shown. The first substrate 102 comprises a plurality of integrated circuit regions in some embodiments, for example. The integrated circuit regions may contain active and passive devices, conductive layers, and dielectric layers according to the electrical design of the integrated circuits, as examples.

A plurality of packaging devices is formed across the surface of the first substrate 102 in accordance with some embodiments. The packaging devices are formed over the first substrate 102 when the first substrate 102 is in a wafer form, for example. The packaging devices are later singulated to form individual packaging devices, e.g., before or after the packaging devices are used to package integrated circuit dies.

A conductive layer is formed over the first substrate 102 as a contact pad 104 using a patterning and deposition process over the first substrate 102. The contact pad 104 may comprise aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), other electrically conductive materials, or multiple layers or combinations thereof, as examples. The contact pad 104 may be formed using an electrolytic plating or electro-less plating process, for example. A plurality of the contact pads 104 (not shown) are formed over the surface of the first substrate 102, and the contact pads 104 may be of the same size or of different sizes.

A passivation layer 106 may be formed over the surface of the first substrate 102 and over the top surface of the contact pad 104 and first substrate 102 for structural support and physical isolation. The passivation layer 106 comprises silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), other insulating materials, or combinations or multiple layers thereof, as examples. An opening in the passivation layer 106 may be made by removing a portion of passivation layer 106 using a mask-defined photoresist etching process to expose a portion of the contact pad 104, while leaving another portion of the contact pad 104 covered.

A polymer layer 108 may be formed on the passivation layer 106, following the contour of the passivation layer 106 and filling a part of the opening of the passivation layer 106 over the contact pad 104. The polymer layer 108 may not completely fill the opening of the passivation layer 106 over the contact pad 104; rather, it may be patterned to form an opening to expose a portion of the contact pad 104, while covering other portions of the contact pad 104. The patterning of the polymer layer 108 may include photolithography techniques. The polymer layer 108 may be formed of a polymer, such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, although other relatively soft, often organic, dielectric materials may also be used. Spin coating or other commonly used formation methods may be used to apply the polymer layer 108. The thickness of the polymer layer 108 may be between about 5 μm and about 30 μm, for example. Alternatively, the polymer layer 108 may comprise other dimensions.

A conductive material such as a metal is used to form interconnect wiring 110 over the polymer layer 108, following the contour of the polymer layer 108. The interconnect wiring 110 comprises a post-passivation interconnect (PPI) structure in some embodiments. The PPI structure 110 includes a PPI line 112 and a PPI pad 114 which are disposed over the polymer layer 108. The PPI line 112 and PPI pad 114 may have a thickness of less than about 30 μm, and may comprise a thickness of about 2 μm to about 10 μm in some embodiments, as examples. The PPI line 112 and PPI pad 114 may comprise a metal such as Ti, Al, Ni, nickel vanadium (NiV), Cu, or combinations or multiple layers thereof, as examples. The PPI line 112 and PPI pad 114 may be formed using electrolytic plating, electro-less plating, sputtering, chemical vapor deposition (CVD) methods, and/or photolithography processes, for example. The PPI line 112 and PPI pad 114 may comprise a single layer or multiple layers using an adhesion layer of Ti, TiW, Cr, or other materials, for example. Alternatively, the PPI line 112 and PPI pad 114 may comprise other materials and dimensions, and may be formed using other methods. The first substrate 102 is connected to a number of PPI lines 112 and PPI pads 114 to form a PPI structure 110 comprising a network (not shown) of PPI lines 112 and PPI pads 114, which may electrically connect to the contact pads 104 of the first substrate 102, for example.

In some embodiments, a blanket coating of conductive material may be formed over the polymer layer 108 and the exposed portion of the contact pad 104, and the conductive material is patterned using lithography, e.g., by forming a layer of photoresist (not shown) over the conductive material, patterning the photoresist, and using the photoresist as an etch mask during an etch process for the conductive material, forming the conductive material into the desired patterns and shapes of the PPI lines 112 and PPI pads 114. The layer of photoresist is then removed. In other embodiments, a seed layer (also not shown) is formed over the polymer layer 108 and exposed portion of the contact pad 104, and a layer of photoresist is formed over the seed layer. The photoresist is patterned with the desired patterns and shapes of the PPI lines 112 and PPI pads 114. The conductive material is then plated onto the seed layer through the patterns in the photoresist. The photoresist is removed, and the seed layer is removed from over the polymer layer 108. Alternatively, other methods may be used to form the PPI lines 112 and PPI pads 114. In some embodiments, the PPI lines 112 and PPI pads 114 are simultaneously formed and are integral to one another; e.g., the PPI lines 112 and PPI pads 114 are formed from a single piece of conductive material.

Only one PPI line 112 and PPI pad 114 are shown in the drawings; however, a plurality of PPI lines 112 and PPI pads 114 are formed across a surface of the packaging device and are used for making electrical connections to a plurality of contact pads 104 disposed over the first substrate 102. The PPI lines 112 and PPI pads 114 comprise a redistribution layer (RDL), post-passivation interconnect structure 110, or other interconnect routing structure of the packaging device in some embodiments, for example.

The PPI line 112 is a conductive line that extends over the underlying contact pad 104. The PPI line 112 fills an opening in the polymer layer 108 and the passivation layer 106 and forms an electrical connection with the contact pad 104. The PPI line 112 contacts the PPI pad 114. The PPI line 112 may have a narrow, wide, or tapered shape. The PPI line 112 may comprise a substantially constant thickness and width. The PPI line 112 terminates at the PPI pad 114; therefore, the bodies of the PPI line 112 and the PPI pad 114 may be formed as one piece.

A solder flux (not shown) may be applied to the PPI line 112 and PPI pad 114 in some embodiments to assist in the flow of the solder, such that a subsequently formed conductive bump 120 makes good physical and electrical contact with the PPI pad 114. The flux may be applied by brushing, spraying, a stencil, or other methods, as examples. The flux generally has an acidic component that removes oxide barriers from the solder surfaces, and an adhesive quality that helps to prevent an integrated circuit or other device from moving on the first substrate 102 surface during the packaging process using the packaging device.

A conductive bump 120 is formed over the PPI pad 114. The PPI pad 114 is used to connect to the conductive bump 120, forming a connection between the contact pad 104 to the conductive bump 120 by way of the PPI line 112 and the PPI pad 114. The conductive bump 120 may have a larger diameter or width C than the diameter or width of the PPI pad 114.

The conductive bump 120 comprises a eutectic material and may comprise a solder bump or a solder ball in some embodiments, as examples. The use of the word “solder” herein includes both lead-based and lead-free solders, such as Pb—Sn compositions for lead-based solder; lead-free solders including InSb; tin, silver, and copper (“SAC”) compositions; and other eutectic materials that have a common melting point and form conductive solder connections in electrical applications. For lead-free solder, SAC solders of varying compositions may be used, such as SAC 105 (Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC 305, and SAC 405, as examples. Lead-free conductive bumps 120 such as solder balls may be formed from SnCu compounds as well, without the use of silver (Ag). Alternatively, lead-free solder connectors may include tin and silver, Sn—Ag, without the use of copper. The conductive bump 120 may be one among an array of the conductive bumps 120 formed as a grid, often referred to as a ball grid array (BGA). The conductive bumps 120 may alternatively be arranged in other shapes and configurations. The conductive bumps 120 may comprise spherical conductive connectors and may also comprise non-spherical conductive connectors, for example.

Referring again to FIG. 1, the conductive bump 120 is attached in some embodiments using a solder ball drop process. The conductive bump 120 is mounted onto the PPI pad 114, and the eutectic material of the conductive bump 120 is re-flowed to attach the conductive bump 120 to the PPI pad 114.

A molding material 124 is formed over the PPI line 112, PPI pad 114, conductive bump 120, and exposed portions of the polymer layer 108 in some embodiments. The molding material 124 comprises a molding compound and may comprise epoxy, an organic polymer, or a polymer with a silica-based filler added, as examples. In some embodiments, the molding material 124 comprises a liquid molding compound (LMC) that is a gel-type liquid when applied. Alternatively, the molding material 124 may comprise other insulating materials. The molding material 124 extends over a top surface of the conductive bump 120 after applying the molding material 124 in some embodiments, and a top portion of the molding material 124 is then recessed so that a top portion of the conductive bump 120 is exposed. After the molding material 124 is applied, the molding material 124 is cured. In some embodiments, the molding material 124 shrinks during the curing process, which partially recesses the molding material 124. Additional molding material 124 is removed in some embodiments using a plasma treatment process or other type of process, to remove the molding material 124 from the conductive bump 120 to expose the conductive bump 120, for example. In other embodiments, the molding material 124 after curing does not require an additional processing step to recess the molding material 124, as another example.

Due to a meniscus effect in some embodiments, the molding material 124 is thicker proximate the conductive bump 120, as illustrated in FIG. 1. In other embodiments, the molding material 124 comprises substantially the same thickness h across the surface of the substrate 102, not shown in the drawings.

In some embodiments, the molding material 124 is formed over the PPI line 112, PPI pad 114, and exposed portions of the polymer layer 108 before the conductive bump 120 is coupled to the PPI pad 114. The molding material 124 is then cured, and openings are formed in the molding material 124 to expose at least portions of the PPI pad 114. The openings can be formed in the molding material 124 using a drilling process, such as a laser drilling process, by a photolithography process, or a direct patterning process of the molding material 124, as examples. Alternatively, the molding material 124 may be patterned using other methods to form the opening over the PPI pad 114. The conductive bump 120 is then coupled to the PPI pad 114 through the opening in the molding material 124.

A second substrate 126 is also provided. The second substrate 126 comprises a printed circuit board (PCB) in some embodiments. Alternatively, the second substrate 126 may comprise other types of substrates. The second substrate 126 includes a plurality of contact pads 128 coupled thereto or formed thereon, as shown in FIG. 1. The contact pads 128 may comprise Cu, Cu alloys, other metals, or multiple layers or combinations thereof, as examples. Alternatively, the contact pads 128 may comprise other materials. Each contact pad 128 comprises a width comprising dimension B.

A top surface of the molding material 124 contacts the conductive bump 120 at a height of the conductive bump 120 having a diameter or width comprising dimension C. Dimension C comprises a confined bump 120 diameter or width; for example, dimension C comprises a diameter or width of an upper-most portion of the conductive bump 120 that is confined by the molding material 124. In some embodiments, dimension C comprises a width of the conductive bump 120, e.g., in embodiments wherein the conductive bump 120 comprises a non-spherical connector.

The first substrate 102 is attached to the second substrate 126, as shown in FIG. 1. Each conductive bump 120 on the first substrate 102 is attached to one of the contact pads 128 on the second substrate 126. A ratio R of C:B comprises about 1.0 or greater in some embodiments.

In some embodiments, the conductive bump 120 comprises a shape of a partial conductive ball that is flat on a side coupled to the PPI pad 114 and substantially spherical on other surfaces, before attaching the conductive bump 120 to one of the contact pads 128 on the second substrate 126. After attaching the conductive bump 120 to one of the contact pads 128, the conductive bump 120 comprises two flat sides, one coupled to the PPI pad 114 and the other coupled to the contact pad 128, as illustrated in FIG. 1. The other surfaces of the conductive bump 120 (e.g., the sides of the conductive bump 120) may be substantially spherical or curved in some embodiments, as shown in FIG. 1. Alternatively, the other surfaces of the conductive bump 120 may be barrel-shaped, substantially straight, or may comprise other shapes, in accordance with some embodiments of the present disclosure.

The amount of molding material 124 (e.g., the thickness h of the molding material 124) is controlled or adjusted to achieve the ratio R of C:B comprising about 1.0 or greater, in some embodiments. In other embodiments, the width B of the contact pad 128 on the second substrate 126 is controlled or adjusted to achieve the ratio R of C:B comprising about 1.0 or greater. In some embodiments, the width B of the contact pad 128 on the second substrate 126 is chosen or selected to achieve the ratio R of C:B comprising about 1.0 or greater. In some embodiments, both the thickness h of the molding material 124 is controlled or adjusted, and also the width B of the contact pad 128 is chosen or selected, that achieves the ratio R of C:B comprising about 1.0 or greater, for example.

The contact pad 128 on the second substrate 126 comprises a width B of about 150 μm to about 300 μm in some embodiments. The diameter or width C of the conductive bump 120 comprises about 150 μm to about 300 μm in some embodiments. Alternatively, the width B of the contact pad 128 and the diameter or width C of the conductive bump 120 may comprise other dimensions or other relative dimensions.

The thickness h of the molding material 124 comprises about 50 μm to about 250 μm in some embodiments. A stand-off height H of the conductive bump 120 between the contact pad 128 on the second substrate 126 and the PPI pad 114 on the first substrate 102 comprises about 150 μm to about 250 μm in some embodiments. The thickness h of the molding material 124 is equal to about (½*H) in the embodiments shown in FIG. 1, for example. In some embodiments, the diameter or width C of the conductive bump 120 comprises a maximum diameter or width Cmax of the conductive bump 120, as illustrated in FIG. 1. In these embodiments, the ratio R of C:B may be about 1.3 or greater, for example.

In some embodiments, the thickness h of the molding material 124 is less than or greater than about (½*H). In other embodiments, the molding material 124 thickness h ranges from about (⅓*H) to about (⅔*H), as another example. In other embodiments, the molding material 124 thickness h is greater than about (⅔*H) or less than about (⅓*H).

For example, FIG. 2 is a cross-sectional view illustrating a portion 130 of a packaging device in accordance with some embodiments of the present disclosure, wherein the molding material 124 comprises a thickness h that is less than about (½*H). A top surface of the molding material 124 contacts the conductive bump 120 at a height of the conductive bump 120 having a diameter or width comprising dimension C, wherein dimension C is less than the maximum diameter or width Cmax of the conductive bump 120. In some embodiments, a width B of the contact pad 128 on the second substrate 126 can be selected to achieve a ratio of C:B of greater than or equal to 1.0, based on the thickness h of the molding material 124 that creates the confined bump diameter or width C of the conductive bump 120. The molding material 124 may comprise a thickness h of about (⅓*H) to less than about (½*H) in some embodiments. Alternatively, the molding material 124 may comprise a thickness h of less than about (⅓*H), in other embodiments.

FIG. 3 is a cross-sectional view illustrating a portion 130 of a packaging device in accordance with yet other embodiments of the present disclosure, wherein the molding material 124 comprises a thickness that is greater than about (½*H). A top surface of the molding material 124 contacts the conductive bump 120 at a height of the conductive bump 120 comprising a diameter or width comprising dimension C, wherein dimension C is less than the maximum diameter or width Cmax of the conductive bump 120. In some embodiments, a width B of the contact pad 128 on the second substrate 126 can be selected to achieve a ratio of C:B of greater than or equal to 1.0, based on the thickness h of the molding material 124 that creates the confined bump diameter or width C of the conductive bump 120. The molding material 124 may comprise a thickness h of greater than about (½*H) to about (⅔*H) in some embodiments. Alternatively, the molding material 124 may comprise a thickness h of greater than about (⅔*H), in other embodiments.

FIG. 4 is a cross-sectional view of a packaging device including the portions 130 of the packaging devices shown in FIGS. 1, 2, and 3 in accordance with some embodiments. FIG. 4 illustrates the implementation of the portions 130 of the packaging devices shown in FIGS. 1, 2, and 3 in a completed packaged semiconductor device 160. The portions of the packaging devices shown in FIGS. 1, 2, and 3 are inverted with respect to the view shown in FIG. 4.

The PPI structure 110 (not shown in FIG. 4; see FIG. 1, 2, or 3) disposed over the first substrate 102 comprises a PPI structure comprising a plurality of the PPI pads, and the second substrate 126 includes a plurality of the contact pads 128 (also not shown in FIG. 4; see FIG. 1, 2, or 3). A plurality of the conductive bumps 120 is coupled between the first substrate 102 and the second substrate 126, as shown in FIG. 4. Only seven conductive bumps 120 are shown in FIG. 4; however, in some embodiments, dozens or hundreds of conductive bumps 120 may be coupled between the substrates 102 and 126, depending on the application. Each of the plurality of conductive bumps 120 is coupled between one of the plurality of PPI pads 114 and one of the plurality of contact pads 128.

In some embodiments, the PPI structure 110 is formed on a first side 143 of the first substrate 102, and the second substrate 126 is coupled to the PPI structure 110 on the first side 143 of the first substrate 102. A third substrate 140 is coupled to a second side 145 of the first substrate 102, the second side 145 of the first substrate 102 being opposite the first side 143 of the first substrate 102, as shown in FIG. 4. At least one integrated circuit die 150 is coupled to the third substrate 140. In some embodiments, a plurality of the integrated circuit dies 150 to the third substrate. The integrated circuit dies 150 may be coupled horizontally across the surface of the third substrate 140. Alternatively, a plurality of the integrated circuit dies 150 may be coupled vertically over one another, as shown in phantom (e.g., in dashed lines) at 150′.

The third substrate 140 comprises an interposer in some embodiments. The third substrate 140 comprising the interposer includes one or more RDLs and through-substrate vias formed thereon, for example. The third substrate 140 is coupled to the first substrate 102 by a plurality of controlled collapse chip connection (C4) bumps 142, and the integrated circuit die or dies 150 are coupled to the third substrate 140 by a plurality of microbumps 152 in some embodiments. Alternatively, the first substrate 102, the second substrate 126, and the third substrate 140 may comprise other types of substrates, and other types of connections 142 and 152 may be used to couple together the dies 150 and third substrate 140 or the first substrate 102 and the third substrate 140, for example. In some embodiments, the packaged semiconductor device 160 comprises a chip-on-wafer-on-substrate (CoWoS) package that is coupled to a second substrate 126 comprising a PCB, for example.

Some embodiments of the present disclosure comprise methods of designing packaging devices for semiconductor devices. Referring again to FIG. 1, 2, or 3, the design methods include providing a first substrate 102 having a PPI structure 110 disposed thereon, the PPI structure 110 including a PPI pad 114. A width B of a contact pad 128 on a second substrate 126 is determined, the contact pad 128 being coupleable to the PPI pad 114 on the first substrate 102 by a conductive bump 120. A thickness h of a molding material 124 to be disposed over the PPI structure 110 proximate the conductive bump 120 is determined. When the molding material 124 is disposed over the PPI structure 110, a top surface of the molding material 124 is determined to contact the conductive bump 120 at a height of the conductive bump 120 having a diameter or width C. The height of the conductive bump 120 having the diameter or width C is slightly greater than thickness h of the molding material 124 in some embodiments. The height of the conductive bump 120 having the diameter or width C is slightly greater than thickness h of the molding material 124 by a few μm in some embodiments, for example. In other embodiments, the height of the conductive bump 120 having the diameter or width C is substantially equal to dimension h, for example.

The design method includes selecting the width B of the contact pad 128, adjusting the thickness h of the molding material 124, or selecting both the width B of the contact pad 128 and adjusting the thickness h of the molding material 124 to achieve a ratio R of the diameter or width C of the conductive bump to the width B of the contact pad (C:B) of about 1.0 or greater. Advantageously, selecting the width B of the contact pad and/or adjusting the thickness of the molding material to achieve the ratio R of about 1.0 or greater reduces an amount of stress on the conductive bump 120, improving the reliability of the packaged semiconductor device 160.

In some embodiments, ratio R comprises about 1.3 or greater. In other embodiments, ratio R comprises about 1.0 to about 1.3. In yet other embodiments, ratio R comprises about 1.1 to about 1.2, as another example.

FIG. 5 is a flow chart 170 illustrating a method of manufacturing a packaging device in accordance with some embodiments of the present disclosure. Referring also to FIG. 1, in step 172, a PPI structure 110 including a PPI pad 114 is formed over a first substrate 102. In step 176, a molding material 124 is formed over portions of the PPI structure. In step 178, a conductive bump 120 is coupled between the PPI pad 114 and a contact pad 128 on a second substrate 126. The contact pad comprises a width B. A top surface of the molding material 124 contacts the conductive bump 120 at a height of the conductive bump 120 comprising a width C. A ratio R of C:B comprises about 1.0 or greater.

Some embodiments of the present disclosure include methods of manufacturing packaging devices, and also include packaging devices manufactured using the methods described herein. Other embodiments include design methods for packaging devices, and methods of packaging semiconductor devices.

Advantages of some embodiments of the disclosure include providing novel packaging devices that have improved reliability, due to the optimized dimensions of various elements of the packaging devices. Methodologies for improving low cost wafer level packaging reliability are disclosed by embodiments of the present disclosure.

An under-ball metallization (UBM) structure is not included in the first substrates 102, which provides a cost savings. A ratio between the contact pad 128 size and a conductive bump 120 diameter or width C that is in contact with the molding material 124 is optimized, which minimizes strain on the conductive bump 120 and furthermore, reduces stress on insulating material layers of the first substrate 102, which may comprise extra low dielectric constant (ELK) materials having a dielectric constant less than a dielectric constant of silicon dioxide in some embodiments, for example. The reduced amount of accumulated strain on the conductive bumps 120 results in a significant increase in bump fatigue life in some embodiments, for example. The accumulated strain on the conductive bumps 120 can be reduced by about 34% in some embodiments by tuning the molding material 124 thickness and controlling ratio R to a value of about 1.0 or greater. Alternatively, the accumulated strain may be reduced by other amounts.

The packaging devices comprise ultra-low cost wafer level chip scale package (WLCSP) schemes and manufacturing processes in some embodiments that provide a reliability improvement. The novel packaging device structures and designs are easily implementable in manufacturing process flows. The manufacturing methods for the packaging devices can be implemented with no additional cost, and ensure a robust wafer level packaging scheme.

In accordance with some embodiments of the present disclosure, a packaging device includes a first substrate including a PPI structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump comprising a width C, and the contact pad comprises a width B. A ratio R of C:B comprises about 1.0 or greater.

In accordance with other embodiments, a method of manufacturing a packaging device includes forming a PPI structure including a PPI pad over a first substrate. A molding material is formed over portions of the PPI structure, and a conductive bump is coupled between the PPI pad and a contact pad on a second substrate. A top surface of the molding material contacts the conductive bump at a height of the conductive bump comprising a width C. The contact pad comprises a width B. A ratio R of C:B comprises about 1.0 or greater.

In accordance with other embodiments, a method of manufacturing a packaging device includes forming a first contact pad over a first substrate, and forming a polymer layer over the first contact pad and the first substrate. An opening is formed in the polymer layer over a portion of the first contact pad, and a PPI structure including a PPI pad and a PPI line is formed over the polymer layer, a portion of the PPI line being coupled to the first contact pad. A molding material is formed over portions of the PPI structure, and a conductive bump is coupled between the PPI pad and a second contact pad on a second substrate. A top surface of the molding material contacts the conductive bump at a height of the conductive bump comprising a width C, and the second contact pad comprises a width B. A ratio R of C:B comprises about 1.0 or greater.

Although some embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (20)

What is claimed is:
1. A method comprising:
forming a post passivation interconnect (PPI) structure including a PPI pad over a first substrate, the PPI structure being on a first side of the first substrate;
forming a molding material over and in physical contact with a first conductive portion of the PPI structure;
coupling a conductive bump between the PPI pad and a contact pad on a second substrate, wherein a top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, wherein the contact pad has a width B, and wherein a ratio R of C:B is about 1.0 or greater, wherein the conductive bump is laterally separated from the first conductive portion of the PPI structure, wherein coupling the conductive bump comprises coupling a solder bump;
coupling a third substrate to a second side of the first substrate using a plurality of controlled collapse chip connection (C4) bumps with a different size than the solder bump, the second side of the first substrate being opposite the first side of the first substrate; and
coupling an integrated circuit die to the third substrate using a plurality of microbumps with a different size than the C4 bumps and the solder bump.
2. The method according to claim 1, wherein forming the PPI structure over the first substrate comprises forming a PPI structure comprising a plurality of the PPI pads, wherein the second substrate comprises a plurality of the contact pads disposed thereon, wherein coupling the conductive bump comprises coupling a plurality of the conductive bumps, and wherein each of the plurality of the conductive bumps is coupled between one of the plurality of the PPI pads and one of the plurality of the contact pads.
3. The method according to claim 1, wherein the second substrate comprises a printed circuit board (PCB).
4. The method according to claim 1, further comprising coupling a plurality of the integrated circuit dies to the third substrate.
5. The method according to claim 1, wherein coupling the third substrate comprises coupling an interposer to the first substrate.
6. The method according to claim 1, wherein a top surface of the molding material distal the conductive bump has a thickness h, wherein the conductive bump has a stand-off height H between the contact pad and the PPI pad, and wherein the thickness h of the molding material is greater than about (½*H).
7. The method of claim 6, wherein the thickness h of the molding material is greater than (⅔*H).
8. The method of claim 1, wherein the microbumps have a smaller size than the C4 bumps and the solder bump.
9. The method of claim 1, wherein the ratio R of C:B is about 1.1 to about 1.2.
10. The method of claim 1, wherein the ratio R of C:B is about 1.3 or greater.
11. The method of claim 1, wherein the width C of the conductive bump is a maximum diameter of the conductive bump.
12. A method of manufacturing a packaging device, the method comprising:
forming a first contact pad over a first substrate;
forming a polymer layer over the first contact pad and the first substrate;
forming an opening in the polymer layer over a portion of the first contact pad;
forming a post passivation interconnect (PPI) structure including a PPI pad and a PPI line over the polymer layer, a portion of the PPI line being coupled to the first contact pad;
forming a molding material over portions of the PPI structure;
coupling a conductive bump between the PPI pad and a second contact pad on a second substrate, wherein a top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, wherein the second contact pad has a width B, and wherein a ratio R of C:B is about 1.0 or greater;
coupling a third substrate to a first side of the first substrate, the PPI being on a second side of the first substrate, the second side of the first substrate being opposite the first side of the first substrate; and
coupling a plurality of integrated circuit dies to the third substrate, wherein coupling the conductive bump comprises coupling a solder bump, wherein coupling the third substrate comprises coupling the third substrate to the first substrate using a plurality of controlled collapse chip connection (C4) bumps with a different size than the solder bump and wherein coupling the plurality of the integrated circuit dies comprises coupling the plurality of the integrated circuit dies to the third substrate using a plurality of microbumps, wherein the microbumps have a smaller size than the C4 bumps and the solder bump.
13. The method according to claim 12, further comprising forming a passivation layer over the first contact pad and the first substrate, before forming the polymer layer, and forming an opening in the passivation layer over a portion of the first contact pad.
14. The method according to claim 12, wherein the ratio R of C:B is about 1.1 to about 1.2.
15. The method of claim 12, wherein the second substrate comprises a printed circuit board (PCB).
16. A method comprising:
forming a first contact pad on a first side of a first substrate;
forming a post passivation interconnect (PPI) structure including a PPI pad over the first contact pad and the first substrate, a portion of the PPI structure being coupled to the first contact pad;
forming a conductive bump on the PPI pad;
encapsulating the first substrate with a molding material over portions of the PPI structure and surrounding at least a lower portion of the conductive bump, wherein a top surface of the molding material contacts the conductive bump at a first height of the conductive bump having a width C, wherein the top surface of the molding material distal the conductive bump has a thickness h, the thickness h being less than the first height;
coupling the first substrate to a second substrate using the conductive bump, the conductive bump being coupled between the PPI pad and a second contact pad disposed on the second substrate, wherein the second contact pad has a width B, and wherein a ratio R of C:B is about 1.0 or greater, wherein the conductive bump has a stand-off height H between the second contact pad and the PPI pad, and wherein the thickness h of the molding material is greater than (⅓*H);
coupling a third substrate to a second side of the first substrate using a plurality of controlled collapse chip connection (C4) bumps with a different size than the conductive bump, the second side of the first substrate being opposite the first side of the first substrate; and
coupling an integrated circuit die to the third substrate using a plurality of microbumps with a different size than the C4 bumps and the conductive bump.
17. The method according to claim 16, wherein the width C of the conductive bump is a maximum diameter of the conductive bump.
18. The method according to claim 17, wherein the ratio R of C:B is about 1.3 or greater.
19. The method according to claim 16, wherein the thickness h of the molding material is measured from a top surface of the PPI structure and wherein the molding material comprises a single material throughout the molding material.
20. The method of claim 16, wherein the microbumps have a smaller size than the C4 bumps and the conductive bump.
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DE201310109531 DE102013109531A1 (en) 2012-12-28 2013-09-02 Apparatus useful as reinforced package comprises a package component, electrical connections, a device electrically coupled to electrical connections, a molding compound, and a molding underfill between the molding compound and the device
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US14/198,262 US9368398B2 (en) 2012-01-12 2014-03-05 Interconnect structure and method of fabricating same
US15/180,929 US9768136B2 (en) 2012-01-12 2016-06-13 Interconnect structure and method of fabricating same
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9368398B2 (en) 2012-01-12 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9082776B2 (en) 2012-08-24 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having protective layer with curved surface and method of manufacturing same
US9355978B2 (en) 2013-03-11 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
US9401308B2 (en) 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US8884427B2 (en) * 2013-03-14 2014-11-11 Invensas Corporation Low CTE interposer without TSV structure
US9196529B2 (en) 2013-09-27 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor devices
US9343434B2 (en) * 2014-02-27 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Laser marking in packages
US9589900B2 (en) 2014-02-27 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad for laser marking
US9666522B2 (en) 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US20170170101A1 (en) * 2015-12-09 2017-06-15 Texas Instruments Incorporated Flip-chip on leadframe having partially etched landing sites

Citations (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072520A (en) 1990-10-23 1991-12-17 Rogers Corporation Method of manufacturing an interconnect device having coplanar contact bumps
US5869904A (en) * 1997-04-28 1999-02-09 Nec Corporation Semiconductor device having a projecting electrode
US6037065A (en) 1995-12-19 2000-03-14 The Westaim Corporation Spheres useful in a detachable connective medium for ball grid array assemblies
US6158644A (en) 1998-04-30 2000-12-12 International Business Machines Corporation Method for enhancing fatigue life of ball grid arrays
US6187615B1 (en) 1998-08-28 2001-02-13 Samsung Electronics Co., Ltd. Chip scale packages and methods for manufacturing the chip scale packages at wafer level
US20010050434A1 (en) 1999-01-20 2001-12-13 Sony Chemicals Corp. Flexible printed wiring boards
US20020001937A1 (en) 2000-06-30 2002-01-03 Nec Corporation Semiconductor package board using a metal base
US6369451B2 (en) 1998-01-13 2002-04-09 Paul T. Lin Solder balls and columns with stratified underfills on substrate for flip chip joining
US6425516B1 (en) * 1999-04-27 2002-07-30 Sony Corporation Semiconductor device and method of production of the same
US20030068847A1 (en) * 2001-09-25 2003-04-10 Masako Watanabe Semiconductor device and manufacturing method
US20030096453A1 (en) 2001-11-16 2003-05-22 Shanger Wang Integrated void-free process for assembling a solder bumped chip
US6586322B1 (en) 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
US20030153172A1 (en) 2002-02-08 2003-08-14 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device
US6643923B1 (en) 1998-07-29 2003-11-11 Sony Chemicals Corp. Processes for manufacturing flexible wiring boards
US6664637B2 (en) * 1999-05-10 2003-12-16 International Business Machines Corporation Flip chip C4 extension structure and process
US20040012930A1 (en) 2002-02-12 2004-01-22 Grigg Ford B. Microelectronic devices and methods for mounting microelectronic packages to circuit boards
US20040027788A1 (en) * 2002-08-08 2004-02-12 Tz-Cheng Chiu Polymer-embedded solder bumps for reliable plastic package attachment
US20040072387A1 (en) 2002-10-12 2004-04-15 Samsung Electronics Co., Ltd. Method of fabricating and mounting flip chips
US20040266162A1 (en) 2003-06-30 2004-12-30 Advanced Semiconductor Engineering, Inc. Semiconductor wafer package and manufacturing method thereof
US20050080956A1 (en) 2000-05-31 2005-04-14 Zaudtke Stephen M. Communication with a handheld device during power up initialization of a system
US6933613B2 (en) * 2003-01-07 2005-08-23 Kabushiki Kaisha Toshiba Flip chip ball grid array package
US6940169B2 (en) 2002-05-21 2005-09-06 Stats Chippac Ltd. Torch bump
US20060038291A1 (en) 2004-08-17 2006-02-23 Hyun-Soo Chung Electrode structure of a semiconductor device and method of manufacturing the same
DE102005040213A1 (en) 2004-08-17 2006-03-09 Samsung Electronics Co., Ltd., Suwon Manufacturing semiconductor device involves depositing photosensitive layer to cover exposed portion of electrode, and subjecting photosensitive layer to photolithography to partially remove photosensitive layer
US20060063378A1 (en) 2004-09-23 2006-03-23 Megie Corporation Top layers of metal for integrated circuits
US20060189114A1 (en) 2005-02-23 2006-08-24 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device and semiconductor device
US20070045840A1 (en) 2005-09-01 2007-03-01 Delphi Technologies, Inc. Method of solder bumping a circuit component and circuit component formed thereby
US7187068B2 (en) 2004-08-11 2007-03-06 Intel Corporation Methods and apparatuses for providing stacked-die devices
US20070102815A1 (en) 2005-11-08 2007-05-10 Kaufmann Matthew V Bumping process with self-aligned A1-cap and the elimination of 2nd passivation layer
US20070108573A1 (en) 2005-11-17 2007-05-17 Samsung Electronics Co., Ltd. Wafer level package having redistribution interconnection layer and method of forming the same
KR20070076846A (en) 2006-01-20 2007-07-25 삼성전자주식회사 Wafer level package having resin molding portion and manufacturing method thereof
US20070176290A1 (en) 2005-03-22 2007-08-02 Myeong-Soon Park Wafer level chip scale package having a gap and method for manufacturing the same
US20070184577A1 (en) 2006-02-07 2007-08-09 Samsung Electronics Co. Ltd. Method of fabricating wafer level package
US20070187825A1 (en) 1997-01-17 2007-08-16 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US20070267745A1 (en) 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including electrically conductive bump and method of manufacturing the same
US20080001290A1 (en) 2006-06-28 2008-01-03 Megica Corporation Integrated circuit (IC) chip and method for fabricating the same
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US20080150134A1 (en) 2006-12-25 2008-06-26 Rohm Co., Ltd. Semiconductor device
US20080308935A1 (en) 2007-06-18 2008-12-18 Samsung Electronics Co., Ltd. Semiconductor chip package, semiconductor package including semiconductor chip package, and method of fabricating semiconductor package
US20090020864A1 (en) 2007-07-17 2009-01-22 Han-Ping Pu Wafer Level package Structure and Fabrication Methods
US20090045513A1 (en) 2007-08-17 2009-02-19 Samsung Electronics Co., Ltd. Semiconductor chip package, electronic device including the semiconductor chip package and methods of fabricating the electronic device
US20090052218A1 (en) * 2007-08-20 2009-02-26 Samsung Electronics Co., Ltd. Semiconductor package having memory devices stacked on logic device
US20090130840A1 (en) 2007-11-16 2009-05-21 Chung Yu Wang Protected Solder Ball Joints in Wafer Level Chip-Scale Packaging
US20090140942A1 (en) 2005-10-10 2009-06-04 Jyrki Mikkola Internal antenna and methods
US20090140442A1 (en) 2007-12-03 2009-06-04 Stats Chippac, Ltd. Wafer Level Package Integration and Method
US20090146317A1 (en) 2007-12-05 2009-06-11 Phoenix Precision Technology Corporation Package substrate having electrically connecting structure
US20090206479A1 (en) 2008-02-15 2009-08-20 Timothy Harrison Daubenspeck Solder interconnect pads with current spreading layers
KR20090120215A (en) 2008-05-19 2009-11-24 삼성전기주식회사 Wafer level chip scale package and fabricating method of the same
US20090314519A1 (en) 2008-06-24 2009-12-24 Javier Soto Direct layer laser lamination for electrical bump substrates, and processes of making same
US20100065966A1 (en) * 2006-12-14 2010-03-18 Stats Chippac, Ltd. Solder Joint Flip Chip Interconnection
US20100078772A1 (en) 2008-09-30 2010-04-01 Cambridge Silicon Radio Ltd. Packaging technology
US20100096754A1 (en) * 2008-10-17 2010-04-22 Samsung Electronics Co., Ltd. Semiconductor package, semiconductor module, and method for fabricating the semiconductor package
US20100140760A1 (en) 2008-12-09 2010-06-10 Nelson Tam Alpha shielding techniques and configurations
US7749882B2 (en) 2006-08-23 2010-07-06 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
KR20100131180A (en) 2009-06-05 2010-12-15 삼성전자주식회사 Semicondoctor package, semiconductor module and method for fabricationg the semiconductor package
US20110037158A1 (en) 2008-05-21 2011-02-17 Sunpil Youn Ball-grid-array package, electronic system and method of manufacture
US20110101520A1 (en) 2009-10-29 2011-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Die Contact Structure and Method
US20110108983A1 (en) 2009-11-12 2011-05-12 Mao Bang Electronic Co., Ltd. Integrated Circuit
US7977783B1 (en) 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
US20110278739A1 (en) * 2010-05-11 2011-11-17 Yi-Shao Lai Semiconductor Package
US20120006592A1 (en) * 2010-07-09 2012-01-12 Ibiden Co., Ltd Wiring board and method for manufacturing the same
US20120199991A1 (en) 2011-02-09 2012-08-09 Fujitsu Limited Semiconductor device and method for producing the same, and power supply
US20120199959A1 (en) 2009-11-23 2012-08-09 Xilinx, Inc. Extended under-bump metal layer for blocking alpha particles in a semiconductor device
US8264089B2 (en) 2010-03-17 2012-09-11 Maxim Integrated Products, Inc. Enhanced WLP for superior temp cycling, drop test and high current applications
US20120261817A1 (en) 2007-07-30 2012-10-18 Stats Chippac, Ltd. Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution
US20130009307A1 (en) 2011-07-08 2013-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers
US8362612B1 (en) 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US20130147031A1 (en) 2011-12-07 2013-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with bump structure on post-passivation interconncet
US20130168850A1 (en) 2012-01-03 2013-07-04 Maxim Integrated Products, Inc. Semiconductor device having a through-substrate via
US20130181338A1 (en) 2012-01-12 2013-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package on Package Interconnect Structure
US8624392B2 (en) 2011-06-03 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US20140054764A1 (en) 2012-08-24 2014-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US20140077361A1 (en) 2012-09-14 2014-03-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over Carrier for Testing at Interim Stages
US20140159223A1 (en) 2012-01-12 2014-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and Method for Package Reinforcement
US20140187103A1 (en) 2012-12-28 2014-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for an Improved Fine Pitch Joint
US20140232017A1 (en) 2012-08-30 2014-08-21 Freescale Semiconductor, Inc. Identification mechanism for semiconductor device die
US20150123269A1 (en) 2013-03-11 2015-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Devices and Methods of Manufacture Thereof
US20150137352A1 (en) 2013-11-18 2015-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming post-passivation interconnect structure
US20150235977A1 (en) 2014-02-17 2015-08-20 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US20150262948A1 (en) 2013-03-13 2015-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus of Packaging Semiconductor Devices

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH045844A (en) 1990-04-23 1992-01-09 Nippon Mektron Ltd Multilayer circuit board for mounting ic and manufacture thereof
US6399426B1 (en) 1998-07-21 2002-06-04 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6365978B1 (en) * 1999-04-02 2002-04-02 Texas Instruments Incorporated Electrical redundancy for improved mechanical reliability in ball grid array packages
US8345435B2 (en) 2009-08-07 2013-01-01 Semiconductor Energy Laboratory Co., Ltd. Terminal structure and manufacturing method thereof, and electronic device and manufacturing method thereof
JP5330184B2 (en) * 2009-10-06 2013-10-30 新光電気工業株式会社 Electronic component equipment
US8492896B2 (en) 2010-05-21 2013-07-23 Panasonic Corporation Semiconductor apparatus and semiconductor apparatus unit
US10015888B2 (en) 2013-02-15 2018-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect joint protective layer apparatus and method
US9589862B2 (en) 2013-03-11 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9401308B2 (en) 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US9437564B2 (en) 2013-07-09 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same

Patent Citations (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072520A (en) 1990-10-23 1991-12-17 Rogers Corporation Method of manufacturing an interconnect device having coplanar contact bumps
US6037065A (en) 1995-12-19 2000-03-14 The Westaim Corporation Spheres useful in a detachable connective medium for ball grid array assemblies
US20070187825A1 (en) 1997-01-17 2007-08-16 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US5869904A (en) * 1997-04-28 1999-02-09 Nec Corporation Semiconductor device having a projecting electrode
US6369451B2 (en) 1998-01-13 2002-04-09 Paul T. Lin Solder balls and columns with stratified underfills on substrate for flip chip joining
US6158644A (en) 1998-04-30 2000-12-12 International Business Machines Corporation Method for enhancing fatigue life of ball grid arrays
US6643923B1 (en) 1998-07-29 2003-11-11 Sony Chemicals Corp. Processes for manufacturing flexible wiring boards
US6187615B1 (en) 1998-08-28 2001-02-13 Samsung Electronics Co., Ltd. Chip scale packages and methods for manufacturing the chip scale packages at wafer level
US20010050434A1 (en) 1999-01-20 2001-12-13 Sony Chemicals Corp. Flexible printed wiring boards
US6425516B1 (en) * 1999-04-27 2002-07-30 Sony Corporation Semiconductor device and method of production of the same
US6664637B2 (en) * 1999-05-10 2003-12-16 International Business Machines Corporation Flip chip C4 extension structure and process
US20050080956A1 (en) 2000-05-31 2005-04-14 Zaudtke Stephen M. Communication with a handheld device during power up initialization of a system
US20020001937A1 (en) 2000-06-30 2002-01-03 Nec Corporation Semiconductor package board using a metal base
US20030068847A1 (en) * 2001-09-25 2003-04-10 Masako Watanabe Semiconductor device and manufacturing method
US20030096453A1 (en) 2001-11-16 2003-05-22 Shanger Wang Integrated void-free process for assembling a solder bumped chip
US6586322B1 (en) 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
US20030153172A1 (en) 2002-02-08 2003-08-14 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device
US20040012930A1 (en) 2002-02-12 2004-01-22 Grigg Ford B. Microelectronic devices and methods for mounting microelectronic packages to circuit boards
US6940169B2 (en) 2002-05-21 2005-09-06 Stats Chippac Ltd. Torch bump
US20040027788A1 (en) * 2002-08-08 2004-02-12 Tz-Cheng Chiu Polymer-embedded solder bumps for reliable plastic package attachment
US20040072387A1 (en) 2002-10-12 2004-04-15 Samsung Electronics Co., Ltd. Method of fabricating and mounting flip chips
US6933613B2 (en) * 2003-01-07 2005-08-23 Kabushiki Kaisha Toshiba Flip chip ball grid array package
US20040266162A1 (en) 2003-06-30 2004-12-30 Advanced Semiconductor Engineering, Inc. Semiconductor wafer package and manufacturing method thereof
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7187068B2 (en) 2004-08-11 2007-03-06 Intel Corporation Methods and apparatuses for providing stacked-die devices
DE112005001949T5 (en) 2004-08-11 2007-05-31 Intel Corporation, Santa Clara Method and apparatus for providing stacked chip elements
US20060038291A1 (en) 2004-08-17 2006-02-23 Hyun-Soo Chung Electrode structure of a semiconductor device and method of manufacturing the same
DE102005040213A1 (en) 2004-08-17 2006-03-09 Samsung Electronics Co., Ltd., Suwon Manufacturing semiconductor device involves depositing photosensitive layer to cover exposed portion of electrode, and subjecting photosensitive layer to photolithography to partially remove photosensitive layer
US20060063378A1 (en) 2004-09-23 2006-03-23 Megie Corporation Top layers of metal for integrated circuits
US20060189114A1 (en) 2005-02-23 2006-08-24 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device and semiconductor device
US20070176290A1 (en) 2005-03-22 2007-08-02 Myeong-Soon Park Wafer level chip scale package having a gap and method for manufacturing the same
US20070045840A1 (en) 2005-09-01 2007-03-01 Delphi Technologies, Inc. Method of solder bumping a circuit component and circuit component formed thereby
US20090140942A1 (en) 2005-10-10 2009-06-04 Jyrki Mikkola Internal antenna and methods
US20070102815A1 (en) 2005-11-08 2007-05-10 Kaufmann Matthew V Bumping process with self-aligned A1-cap and the elimination of 2nd passivation layer
US20070108573A1 (en) 2005-11-17 2007-05-17 Samsung Electronics Co., Ltd. Wafer level package having redistribution interconnection layer and method of forming the same
KR20070076846A (en) 2006-01-20 2007-07-25 삼성전자주식회사 Wafer level package having resin molding portion and manufacturing method thereof
US20070184577A1 (en) 2006-02-07 2007-08-09 Samsung Electronics Co. Ltd. Method of fabricating wafer level package
US20070267745A1 (en) 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including electrically conductive bump and method of manufacturing the same
US20080001290A1 (en) 2006-06-28 2008-01-03 Megica Corporation Integrated circuit (IC) chip and method for fabricating the same
US7749882B2 (en) 2006-08-23 2010-07-06 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US20100065966A1 (en) * 2006-12-14 2010-03-18 Stats Chippac, Ltd. Solder Joint Flip Chip Interconnection
US20080150134A1 (en) 2006-12-25 2008-06-26 Rohm Co., Ltd. Semiconductor device
US20080308935A1 (en) 2007-06-18 2008-12-18 Samsung Electronics Co., Ltd. Semiconductor chip package, semiconductor package including semiconductor chip package, and method of fabricating semiconductor package
US20090020864A1 (en) 2007-07-17 2009-01-22 Han-Ping Pu Wafer Level package Structure and Fabrication Methods
US20120261817A1 (en) 2007-07-30 2012-10-18 Stats Chippac, Ltd. Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution
US20090045513A1 (en) 2007-08-17 2009-02-19 Samsung Electronics Co., Ltd. Semiconductor chip package, electronic device including the semiconductor chip package and methods of fabricating the electronic device
KR20090018442A (en) 2007-08-17 2009-02-20 삼성전자주식회사 Semiconductor package, method of fabricating the same and electronic device including the same
US20090052218A1 (en) * 2007-08-20 2009-02-26 Samsung Electronics Co., Ltd. Semiconductor package having memory devices stacked on logic device
US20090130840A1 (en) 2007-11-16 2009-05-21 Chung Yu Wang Protected Solder Ball Joints in Wafer Level Chip-Scale Packaging
US20090140442A1 (en) 2007-12-03 2009-06-04 Stats Chippac, Ltd. Wafer Level Package Integration and Method
US20090146317A1 (en) 2007-12-05 2009-06-11 Phoenix Precision Technology Corporation Package substrate having electrically connecting structure
US20130105971A1 (en) 2008-02-15 2013-05-02 Ultratech, Inc. Solder Interconnect Pads with Current Spreading Layers
US20090206479A1 (en) 2008-02-15 2009-08-20 Timothy Harrison Daubenspeck Solder interconnect pads with current spreading layers
KR20090120215A (en) 2008-05-19 2009-11-24 삼성전기주식회사 Wafer level chip scale package and fabricating method of the same
US20110037158A1 (en) 2008-05-21 2011-02-17 Sunpil Youn Ball-grid-array package, electronic system and method of manufacture
US20090314519A1 (en) 2008-06-24 2009-12-24 Javier Soto Direct layer laser lamination for electrical bump substrates, and processes of making same
US20100078772A1 (en) 2008-09-30 2010-04-01 Cambridge Silicon Radio Ltd. Packaging technology
US20100096754A1 (en) * 2008-10-17 2010-04-22 Samsung Electronics Co., Ltd. Semiconductor package, semiconductor module, and method for fabricating the semiconductor package
US20100140760A1 (en) 2008-12-09 2010-06-10 Nelson Tam Alpha shielding techniques and configurations
KR20100131180A (en) 2009-06-05 2010-12-15 삼성전자주식회사 Semicondoctor package, semiconductor module and method for fabricationg the semiconductor package
US7977783B1 (en) 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
US20110101520A1 (en) 2009-10-29 2011-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Die Contact Structure and Method
US20110108983A1 (en) 2009-11-12 2011-05-12 Mao Bang Electronic Co., Ltd. Integrated Circuit
US20120199959A1 (en) 2009-11-23 2012-08-09 Xilinx, Inc. Extended under-bump metal layer for blocking alpha particles in a semiconductor device
US8264089B2 (en) 2010-03-17 2012-09-11 Maxim Integrated Products, Inc. Enhanced WLP for superior temp cycling, drop test and high current applications
US8362612B1 (en) 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US20110278739A1 (en) * 2010-05-11 2011-11-17 Yi-Shao Lai Semiconductor Package
US20120006592A1 (en) * 2010-07-09 2012-01-12 Ibiden Co., Ltd Wiring board and method for manufacturing the same
US20120199991A1 (en) 2011-02-09 2012-08-09 Fujitsu Limited Semiconductor device and method for producing the same, and power supply
US8624392B2 (en) 2011-06-03 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US8735273B2 (en) 2011-07-08 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Forming wafer-level chip scale package structures with reduced number of seed layers
US20130009307A1 (en) 2011-07-08 2013-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers
US20130147031A1 (en) 2011-12-07 2013-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with bump structure on post-passivation interconncet
US20130168850A1 (en) 2012-01-03 2013-07-04 Maxim Integrated Products, Inc. Semiconductor device having a through-substrate via
US20130181338A1 (en) 2012-01-12 2013-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package on Package Interconnect Structure
US20140159223A1 (en) 2012-01-12 2014-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and Method for Package Reinforcement
US20140054764A1 (en) 2012-08-24 2014-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US20140232017A1 (en) 2012-08-30 2014-08-21 Freescale Semiconductor, Inc. Identification mechanism for semiconductor device die
US20140077361A1 (en) 2012-09-14 2014-03-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over Carrier for Testing at Interim Stages
US20140187103A1 (en) 2012-12-28 2014-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for an Improved Fine Pitch Joint
US20150123269A1 (en) 2013-03-11 2015-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Devices and Methods of Manufacture Thereof
US20150243613A1 (en) 2013-03-11 2015-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Devices and Methods of Manufacture Thereof
US20150262948A1 (en) 2013-03-13 2015-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus of Packaging Semiconductor Devices
US20150137352A1 (en) 2013-11-18 2015-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming post-passivation interconnect structure
US20150235977A1 (en) 2014-02-17 2015-08-20 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof

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