CN103187388A - Packaged semiconductor device and method of packaging the semiconductor device - Google Patents

Packaged semiconductor device and method of packaging the semiconductor device Download PDF

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Publication number
CN103187388A
CN103187388A CN2012101919442A CN201210191944A CN103187388A CN 103187388 A CN103187388 A CN 103187388A CN 2012101919442 A CN2012101919442 A CN 2012101919442A CN 201210191944 A CN201210191944 A CN 201210191944A CN 103187388 A CN103187388 A CN 103187388A
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China
Prior art keywords
semiconductor device
contact pad
insulating barrier
moulding compound
encapsulation
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CN2012101919442A
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CN103187388B (en
Inventor
林俊成
洪瑞斌
刘乃玮
茅一超
施婉婷
董簪华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN103187388A publication Critical patent/CN103187388A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.

Description

The semiconductor device of encapsulation and the method for encapsulated semiconductor device
The cross reference of related application
The application relates to the patent application of following common co-pending and common transfer: the name of submitting on September 8th, 2011 is called the sequence number 13/228 of " Packaging Methods and Structures Using a Die Attach Film (method for packing and the structure of employing tube core junction film) ", 244, incorporate its full content into the application.
Technical field
The present invention relates to semiconductor packages, in particular to the semiconductor device of encapsulation and the method for encapsulated semiconductor device.
Background technology
Semiconductor device is used for various electronic application, such as PC, mobile phone, digital camera and other electronic equipments.Usually by above Semiconductor substrate, depositing the material of insulation or dielectric layer, conductive layer and semi-conductive layer in order, and adopt the various material layers of lithographic patterning to form circuit element thereon and element is made semiconductor device.
Semiconductor industry improves constantly various electronic components () integration density for example, transistor, diode, resistor, capacitor etc., this allows more element is integrated in the given zone by constantly reducing the minimal parts size.In some applications, these littler electronic components need utilize the still less littler packaging part of area than the packaging part in past equally.
Therefore, begin to develop new encapsulation technology such as wafer-level packaging (WLP), wherein integrated circuit (IC) has been arranged on the carrier that has for the wiring that connects with IC and other electric components.These are used for semi-conductive novel relatively encapsulation technology and face the manufacturing challenge.
Summary of the invention
On the one hand, the present invention relates to a kind of semiconductor device of encapsulation, comprising: contact pad is positioned on the semiconductor element; Insulating barrier surrounds described contact pad; And moulding compound, surround described insulating barrier, wherein, two vicinities of described moulding compound and described insulating barrier and nonlinear surface contact.
In the semiconductor device of described encapsulation, wiring layer is arranged on the described contact pad and is physically connected to described contact pad, and wherein, described wiring layer extends to outside the border of described semiconductor element.
In the semiconductor device of described encapsulation, the described insulating barrier that surrounds described contact pad has thin and thick portion, and wherein, the thickness of described thin portion is in about 1 μ m to the scope of about 30 μ m.
In the semiconductor device of described encapsulation, protective layer is between described contact pad and described insulating barrier.
In the semiconductor device of described encapsulation, described protective layer is copper diffusion barrier spare.
In the semiconductor device of described encapsulation, the thickness of described protective layer is in about 50nm to the scope of about 2 μ m.
In the semiconductor device of described encapsulation, described protective layer also described insulating barrier and below another insulating barrier between.
In the semiconductor device of described encapsulation, described protective layer is that dielectric material and comprising is selected from by SiN, SiC, SiCN, SiCO, TEOS, SiO 2Or the material of the group of low-k dielectric composition.
In the semiconductor device of described encapsulation, described dielectric material has also improved the adherence between described contact pad and the described insulating barrier.
In the semiconductor device of described encapsulation, described protective layer is electric conducting material and is made by the material that is selected from the group of being made up of Ta, TaN, Ti, TiN, Co and Mn.
In the semiconductor device of described encapsulation, described contact pad is the copper post and has underbump metallization layer below.
In the semiconductor device of described encapsulation, the thickness of described contact pad is greater than the thickness of described insulating barrier.
On the other hand, the present invention also provides a kind of semiconductor device of encapsulation, comprising: contact pad is positioned on the semiconductor element; Insulating barrier surrounds described contact pad; Protective layer, wherein, described protective layer is between described contact pad and described insulating barrier; And moulding compound, surround described insulating barrier, wherein, two vicinities of described moulding compound and described insulating barrier and nonlinear surface contact.
Another aspect the invention provides a kind of method of encapsulated semiconductor device, and described method comprises: semiconductor device is provided, and wherein, described semiconductor device has contact pad; Form insulating barrier above described semiconductor device, wherein, the thickness of described contact pad is greater than the thickness of described insulating barrier; Form moulding compound to cover described semiconductor device and the interval between described semiconductor device and adjacent semiconductor device, wherein, these two semiconductor device all are positioned on the carrier wafer; And be positioned at the described moulding compound of described bond pad top and the surface that described insulating barrier comes the described semiconductor device of planarization by removal.
Described method also comprises: form redistributing layer (RDL) above described semiconductor device, wherein, described RDL is connected to described contact pad, and wherein, described RDL extends to outside the border of described semiconductor device.
Described method also comprises: form protective layer between described contact pad and described insulating barrier.
In described method, the thickness of described protective layer is in about 50nm to the scope of about 2 μ m.
In described method, implement the described surface of planarization by grinding.
In described method, described contact pad is that copper post and having is in the thickness of about 1 μ m to about 35 mu m ranges.
In described method, remove the described protective layer that does not surround described contact pad by etching.
Description of drawings
In order to understand the present invention and advantage thereof more fully, the following description that will carry out by reference to the accompanying drawings now as a reference, wherein:
Figure 1A to Fig. 1 H is the cutaway view according to the semiconductor device in the fan-out wafer-level packaging part (FO-WLP) of each encapsulated phase of some embodiment.
Fig. 1 I is the amplification view according to the semiconductor device of the encapsulation of Fig. 1 H of some embodiment.
Fig. 2 A to Fig. 2 C is the amplification view according to the part of the semiconductor device in the fan-out wafer-level packaging part of describing in Figure 1B, Fig. 1 C and Fig. 1 D respectively (FO-WLP) of some embodiment.
Fig. 3 A to Fig. 3 B is the cutaway view according to the order processing of the semiconductor device in the fan-out wafer-level packaging part (FO-WLP) of each encapsulated phase of some embodiment.
Fig. 3 C is the amplification view according to the semiconductor device of the encapsulation of some embodiment.
Fig. 4 A to Fig. 4 B is the cutaway view according to the semiconductor device in the fan-out wafer-level packaging part (FO-WLP) of each encapsulated phase of some embodiment.
Fig. 4 C is the amplification view according to the semiconductor device of the encapsulation of some embodiment.
Fig. 5 A to Fig. 5 B is the cutaway view according to the semiconductor device in the fan-out wafer-level packaging part (FO-WLP) of each encapsulated phase of some embodiment.
Except as otherwise noted, corresponding label and symbol is often referred to corresponding components in the different accompanying drawings.Draw accompanying drawing and be used for being clearly shown that the related fields of embodiment, and must not draw in proportion.
Embodiment
Manufacturing and the use of the embodiment of the invention have been discussed below in detail.Yet, should be appreciated that, the invention provides many applicable inventive concepts that can in various concrete environment, realize.The specific embodiment of discussing only is manufacturing and uses illustrative of specific ways of the present invention, limits the scope of the invention and be not used in.
Figure 1A to Fig. 1 I is the cutaway view at the semiconductor device of each encapsulated phase according to the embodiment of the invention.At first with reference to Figure 1A, provide carrier wafer 100.As an example, carrier wafer 100 can comprise glass, silica, aluminium oxide etc.The thickness of carrier wafer 100 can be between approximately a few mil to tens mils, and can comprise the diameter of about 300mm in certain embodiments.Carrier wafer 100 works as the carrier wafer that is used for fan-out of processing during encapsulated semiconductor device or tube core 104 (referring to Figure 1B), and fan-out means the electrical connection that exceeds outside the semiconductor element border.
In certain embodiments, above carrier wafer 100, form tube core junction film (DAF) 102, as shown in Figure 1A.DAF 102 can comprise polymer, and comprises thermoplastic in certain embodiments.DAF 102 can be liquid, and thick liquid for example, this liquid be liquid when using but at room temperature form solid, and can become semiliquid when heating, thereby and can become working as sticker of viscosity at elevated temperatures.
Next, as shown in Figure 1B, a plurality of tube cores 104 are engaged to DAF 102.As an example, according to size and the concrete purposes of the size of tube core 104, carrier wafer 100, can with tens tube cores 104 or a hundreds of tube core 104 or more tube core be engaged to DAF 102.In this article, for the purpose of discussing, tube core 104 has positive 103a and back side 103b.The positive 103a of tube core 104 is also referred to as first in this article, and back side 103b is also referred to as second in this article.Tube core 104 comprises semiconductor device or the integrated circuit of before having made in Semiconductor substrate.Tube core 104 can comprise one or more layers circuit and/or the electric function element that forms thereon, and can comprise for example (not shown) lead, through hole, capacitor, diode, transistor, resistor, inductor and/or other electric components.After making, that tube core 104 is separated from each other and prepare to encapsulate.For example, can use to pick up with placement machine tube core 104 is placed in the precalculated position on the carrier wafer 100.As shown in Figure 1B, the back side 103b of tube core 104 is engaged to DAF 102.
Next, implement packaging technology to encapsulate each in a plurality of tube cores 104.In more described embodiment as Figure 1A to Fig. 1 I, for package die 104, at first, forming moulding compound 106 above a plurality of tube cores 104 and above the expose portion of DAF 102, as shown in Fig. 1 C.As shown, can above the carrier wafer 100 moulding compound 106 be molded on tube core 104 and the DAF 102.The end face of moulding compound 106 can be higher than (as shown in Fig. 1 C), flush in (as shown in Fig. 1 D) or be lower than the end face 104a of tube core 104 slightly.As shown, moulding compound 106 is filled in the gap between a plurality of tube cores 104.To discuss the more details that molding forms technology below.
Next, can implement the end face 104a of a plurality of tube cores 104 of flatening process (such as grinding technics) planarization, thereby can reduce at least and may eliminate any inhomogeneous among the end face 104a of tube core 104 basically.If moulding compound 106 comprises the part on the end face 104a that is positioned at tube core 104, these parts of moulding compound 106 have also been removed by grinding technics, as shown in Fig. 1 D.Therefore, the end face 106a of the remainder of moulding compound 106 flushes with the end face 104a of a plurality of tube cores 104.In addition, can also height or the thickness of a plurality of tube cores 104 be decreased to predetermined height by grinding technics.
For example on the positive 103a of tube core 104, above the end face 104a of a plurality of tube cores 104, form wiring layer 108, as shown in Fig. 1 E.Wiring layer 108 can comprise one or more redistributing layers (RDL), will do further to discuss to it in this article with reference to figure 1I.The RDL layer is surrounded by one or more dielectric layers.Part RDL can extend to outside the border of tube core 104.As a result, can realize better connectivity and design flexibility.The fan-out that RDL is used in wafer-level packaging (WLP) is designed to possibility.
Structure shown in Fig. 1 E comprises the reconstruction wafer that for example is positioned at carrier wafer 100 tops that comprise a plurality of tube cores 104.Above part wiring layer 108, form a plurality of soldered balls 110, as shown in Fig. 1 F.Making and this stage of packaging technology, can be for example electricly alternatively packaged die 104 be being tested with functional test by implementing.
In certain embodiments, packaged die 104 comprises moulding compound 106, wiring layer 108, soldered ball 110 and DAF 102.In other embodiments, removed DAF 102, thereby packaged die comprises moulding compound 106, wiring layer 108 and soldered ball 110.
Next, according to some embodiment, as shown in Fig. 1 G, remove carrier wafer 100 at least from packaged die 104.For example, during the technology of peeling off (debonding) carrier wafer 100 from packaged die 104, moulding compound 106 and wiring layer 108 support tube core 104.In the embodiment shown in Figure 1A to Fig. 1 I, as shown, DAF 102 is retained on the back side 103b of tube core 104.Alternatively, can for example adopt light (laser) or thermal process and when removing carrier wafer 100 or with the procedure of processing of separating, remove DAF 102.
At the tube core 104 of the separation of defiber (singulation line) 114 places or separate packages, form independently packaged die 104 then, be also referred to as the semiconductor device 120 of encapsulation hereinafter, as shown in Fig. 1 H.The edge of adjacent die 104 arranges moulding compound 106 between wiring layer 108 and DAF 102 in the semiconductor device 120 of encapsulation, the edge of its protection tube core 104.For packaged die 104 and contiguous packaged die 104 are separated, also as shown in Fig. 1 G, can apply the soldered ball 110 on the positive 103a of tube core 104 and be with 112.Be included in the cutting belt that supports packaged die 104 during the separating technology with 112.Then from the semiconductor device 120 with 112 removal encapsulation, as shown in Fig. 1 H.
Fig. 1 I is the amplification view according to the semiconductor device 120 of the encapsulation shown in Fig. 1 H of some embodiment.Fig. 1 I also shows can apply optional and is with 122 above DAF 102 after removing carrier wafer 100.In certain embodiments, optionally can comprise the indicia band that is suitable for the laser marking mark with 122.In other embodiments, DAF 102 can comprise the material that is suitable for for example using laser labelling, and is with 122 can not be included in the structure.After forming soldered ball 110, can implement test to tube core 104, and for example, can to 122 or DAF 102 carry out mark to show the result of test.Also can be for other a variety of causes before separating or afterwards packaged die 104 is carried out mark.
According to some embodiment, Fig. 1 I also shows the more detailed view of tube core 104 and wiring layer 108.The view of tube core 104 and wiring layer 108 is exemplary; Alternatively, tube core 104 and wiring layer 108 can comprise other structures, layout and/or design.In the illustrated embodiment, tube core 104 comprises the substrate 124 that comprises silicon or other semi-conducting materials. Insulating barrier 126a and 126b can be included in the passivation layer that arranges on the substrate 124.Can be at the conductive component (such as metal pad 127, connector, through hole or lead) of substrate thus the electric component (not shown) of the contact pad 128 that the top forms tube core 104 and substrate 124 forms and electrically contacts.Contact pad 128 can be in forming insulating barrier 126c, and this insulating barrier 126c can comprise polymeric layer or other insulating material.
Wiring layer 108 can comprise insulating barrier 132a and the 132b that includes polymer or other insulating material.As shown, can form RDL 130 in insulating barrier 132a and 132b, wherein the contact pad on part RDL130 and the tube core 104 128 forms and electrically contacts.As shown, can form optional under-bump metallization (UBM) structure (or layer) 134 at part RDL 130 and insulating barrier 132b.UBM structure 134 is conducive to for example connect and form soldered ball 110.Be that the name of submitting on September 8th, 2011 is called the more details of having described the method for encapsulated semiconductor device in No. the 13/228th, 244, the U.S. Patent application of " Packaging Methods and Structures Using a Die Attach Film (adopting method for packing and the structure of tube core junction film) ".
Fig. 2 A is the enlarged drawing according to the zone 150 of Figure 1B of some embodiment.Zone 150 is parts of tube core 104 and comprises substrate 124 as describing among Fig. 1 I.As mentioned above, have device in substrate 124, this substrate 124 comprises silicon and/or other semi-conducting materials.Have insulating barrier 126a above substrate 124, this insulating barrier 126a isolates and separates the conductive structure (not shown).Insulating barrier 126a can comprise that undoped silicon oxide, low-k are (low-k) dielectric, doping dielectric film or its combination.In certain embodiments, the dielectric dielectric constant of low-k can be less than 3.5.In some other embodiment, the dielectric dielectric constant of low-k can be less than 2.5.
Fig. 2 A shows zone 150 and also comprises metal pad 127, and this metal pad 127 can be made by aluminium or other suitable material.By the interconnection structure (not shown) metal pad 127 is connected to device on the substrate 124.Form contact pad 128 ' at metal pad 127.In certain embodiments, metal pad 128 ' is made of copper and forms in the top of metal pad 127 and UBM layer 129 (not shown in Fig. 1 I for the sake of simplicity).UBM layer 129 can comprise copper diffusion barrier spare, and it can be titanium layer, titanium nitride layer, tantalum layer or tantalum nitride layer.UBM layer 129 can also comprise Seed Layer, and it can comprise copper or copper alloy.Yet, also can comprise other metals, such as silver, gold, aluminium and combination thereof.
In certain embodiments, contact pad 128 ' is the copper post and passes through to electroplate formation.Insulating barrier 126b is used for a part and the metal pad 127 of contact pad 128 ' and UBM layer 129 are kept apart.Insulating barrier 126b can be made by one or more dielectric layers, and these one or more dielectric layers can comprise oxide, nitride, polyimides, insulating polymer or other suitable material.Insulating barrier 126c ' covers insulating barrier 126b and contact pad 128 '.As mentioned above, insulating barrier 126c ' can comprise polymeric layer or other insulating material.The exemplary polymer that can be used for insulating barrier 126c can comprise epoxy resin, polyimides, benzocyclobutene (BCB), polybenzoxazoles (PBO) etc., yet also can use other softer (being generally organic) dielectric materials relatively.
The height D ' of the contact pad of measuring above insulating barrier 126b in certain embodiments, 128 is in about 1 μ m to the scope of about 25 μ m.The height H of the insulating barrier 126c ' that above insulating barrier 126b, measures ' be in about 1 μ m to the scope of about 30 μ m.
Fig. 2 B is the enlarged drawing according to the zone 150 ' of Fig. 1 C of some embodiment.Fig. 2 B shows moulding compound 106 and covers tube core 104.As describing and illustrate among Fig. 1 I, part fan-out structure will be made up, such as RDL 130 in the above above moulding compound 106.According to some embodiment, moulding compound 106 is liquid form and dry after carrier wafer 100 disperses at first.For example, moulding compound 106 can comprise epoxy resin, resin, silica-filled thing or other additives.
Fig. 2 C is the zone 150 according to Fig. 1 D of some embodiment " enlarged drawing.Fig. 2 C illustrates by flatening process (such as grinding) and has removed the moulding compound 106, insulating barrier 126c of part and metal pad 128 that may a part, thereby from the unnecessary material of the surface removal of contact pad 128 ' and the substrate surface of planarization Fig. 2 B.Afterwards, according to some embodiment, as shown in Fig. 1 I, then uncompleted packaging part (having the structure of Fig. 2 C at carrier wafer 100) is delivered to other packaging technologies of describing among Fig. 1 E to Fig. 1 H above carrying out with the substrate of manufacturing and encapsulation.Interface 142 ' is positioned between contact pad 128 ' and the dielectric layer 126c '.
The following technological operation that ball 110 is installed that comprises that uncompleted packaging part (structure that has Fig. 2 C at carrier wafer 100) is implemented may apply big stress to packaged die 120.As shown in Fig. 2 C, the interface 141 ' between insulating barrier 126c ' and the moulding compound 106 is linear or vertical.In certain embodiments, linear interface 141 ' is more weak relatively and may cause layering (delamination) under the stress effect.In addition, when the substrate of Fig. 2 B is implemented moulding compound 106 and the insulating barrier 126c ' that planarization operates to remove part, and during contact pad 128 ' that may a part, determining of flatening process terminal point may be challenging.When removed material when moulding compound 106 changes to insulating barrier 126c ' and change to contact pad 128 ' then, can determine the terminal point of flatening process by detecting the different torsional forcess that born by planarization instrument (such as grinder).In certain embodiments, by determining terminal point by planarization tool detection contact pad 128 '.When the planarization instrument need be identified the joint on two kinds of dissimilar surfaces (insulating barrier 126c ' and contact pad 128 '), the terminal point of determining flatening process was challenging.
Except the problem of discussing above, the exposed surface 333 ' of insulating barrier 126c ' can discharge chemical substance during forming insulating barrier 132a and RDL 130 in following process.As mentioned above, insulating barrier 126c ' can be made by polymer, and this polymer can decompose under plasma process, sputtering technology or photoresist ashing effect.The chemical substance that insulating barrier 126c ' discharges can redeposited interface 334 ' between contact pad 128 ' and RDL 130 goes up and causes interface resistance to increase.Because these problems at least, according to some embodiment, need to improve the follow-up structure of semiconductor device that causes forming encapsulation of the mechanism of the formation molded structure shown in Fig. 2 A to Fig. 2 C and they.
According to some embodiment, Fig. 3 A illustrates the more detailed cutaway view in the zone 150 ' of Fig. 1 C.The contact pad 128 of Fig. 3 A " height D " be higher than the height D ' among Fig. 2 A.In certain embodiments, height D " be in about 1 μ m to the scope of about 35 μ m.Insulating barrier 126 " height H ' be in about 1 μ m to the scope of about 30 μ m.Insulating barrier 126c " surface 145 be lower than contact pad 128 " surface 434.If form insulating barrier 126c by the liquid that distributes (such as passing through spin coating process) to contain the precursor of polymer or polymer ", at contact pad 128 " top forms insulating barrier 126c " and thin layer 126c*.In certain embodiments, the thickness of thin layer 126c* is in about 0.01 μ m to the scope of about 3 μ m.Described above be suitable for forming insulating barrier 126c " exemplary polymer.In certain embodiments, implement curing process then to drive away moisture or the solvent in the membrane.Fig. 3 A illustrate moulding compound 106 cover have insulating barrier 126c " tube core 104.
Fig. 3 B is the zone 150 according to Fig. 1 D of some embodiment " enlarged drawing.Fig. 3 B illustrate such as by grind removed and planarization the moulding compound 106 of part, be positioned at contact pad 128 " the dielectric layer 126c of top " and contact pad 128 ".According to some embodiment, uncompleted substrate package is delivered to carried out such as the semiconductor device of the other packaging technology described in Fig. 1 E to 1H with manufacturing and encapsulation then.Fig. 3 C illustrates the more detailed cutaway view according to the semiconductor device 120 ' of the encapsulation of some embodiment.
For the structure shown in Fig. 3 B, moulding compound 106 and dielectric layer 126c " between interface 141 " be not single linear interface.On the contrary, according to some embodiment, as shown in Fig. 3 C, interface 141 " have three sections connected to one another, i.e. linear surface 141A ", 141B " and 141C ".Interface 141 " stronger than above-described single linear interface 141 ' on mechanical strength, and can bear more stress and not stratified.In addition, at the moulding compound 106 of removing part and dielectric layer 126c* and contact pad 128 that may a part " flatening process during, at contact pad 128 " only there is skim dielectric layer 126c* the top.With processing at contact pad 128 " the top structure that do not have this thin layer dielectric layer 126c* compares, this makes the terminal point of determining planarization be more prone to and is more accurate.Because, in case torsional forces owing to planarization instrument contact dielectric layer 126c* changes, the planarization instrument will be very fast and contact pad 128 " contact.The definite of terminal point will be more accurate.For example, the set time of torsional forces after changing can be set stops flatening process.In addition, also greatly reduce contact pad 128 " interface 334 " on the higher risk of interface resistance.This is because dielectric layer 126c " exposed surface 333 " (than the surface 333 ' described in Fig. 2 C) significantly reduced.Therefore, dielectric layer 126c " amount of the chemical substance that discharges also significantly reduced.Therefore, make dielectric layer 126c " chemical substance that discharges is deposited on interface 334 again " on risk minimization.
For some packaging parts, as shown in Fig. 2 C, relate to the layering that the interface 142 ' (referring to Fig. 2 C) between contact pad 128 ' and dielectric layer 126c ' is located.In addition, if contact pad 128 ', 128 " comprise copper, for some packaging parts, also may relate to contact pad 128 ', 128 " the metal diffusion.As a result, according to some embodiment, as shown in Fig. 4 A, can deposit protective layer 135 to surround contact pad 128 ".Protective layer 135 can be made by dielectric material, and this dielectric material comprises SiN, SiC, SiCN, SiCO, TEOS, SiO 2, low-k dielectric etc.For example, low-k dielectric can have the dielectric constant less than about 3.5.Protective layer 135 has also improved dielectric layer 126c " and contact pad 128 " between adherence.In certain embodiments, the thickness of protective layer 135 is in about 50nm to the scope of about 2 μ m.According to some embodiment, form dielectric layer 126c " and the technology of moulding compound 106 and top at the resemble process described in Fig. 3 A and Fig. 3 B.Then, remove moulding compound 106, dielectric layer 126c " and protective layer 135 be positioned at contact pad 128 " above part.
Fig. 4 B shows and is positioned at contact pad 128 according to some embodiment with removal in planarization " cutaway view of structure after the material of top.Protective layer 135 covers contact pads 128 " sidewall and reduce contact pad 128 " in the outdiffusion of copper.In addition, protective layer 135 has also improved contact pad 128 " and dielectric layer 126c " between adherence.Fig. 4 C shows the semiconductor device 120 according to the encapsulation of some embodiment " cutaway view.
In certain embodiments, protective layer 135 ' can be by being enough to stop the electric conducting material (such as Ta, TaN, Ti, TiN, Co, Mn or its combination) of copper diffusion to be made.Fig. 5 A shows according to some embodiment and covers the contact pad 128 that is positioned on the substrate 124 " the protective layer 135 ' of sidewall.Protective layer 135 ' does not cover the surface of dielectric layer 126b.Forming dielectric layer 126c " before, remove the protective layer 135 ' that is positioned at dielectric layer 126b surface by etching.In certain embodiments, etch process is the dry plasma body technology.Then, at substrate deposition moulding compound 106.Remove moulding compound 106, dielectric layer 126c*, protective layer 135 ' by planarization then and be positioned at contact pad 128 " part of top.Fig. 5 B shows the cutaway view according to Fig. 5 A after the planarization operation of some embodiment.
Provide in semiconductor device substrates and formed moulding compound so that the fan-out structure in the wafer-level packaging (WLP) becomes possible mechanism.This mechanism comprises the part surface that covers the insulating barrier that surrounds contact pad.This mechanism has been improved the reliability of packaging part and the technology controlling and process of packaging technology.This mechanism also reduces the risk of interface debonding and the too much degasification of insulating barrier during following process.This mechanism has also been improved determining of planarization endpoint.By utilizing the protective layer between contact pad and the insulating barrier, can reduce the outdiffusion of copper and also can improve adherence between contact pad and the insulating barrier.
A kind of semiconductor device of encapsulation is provided in certain embodiments.The semiconductor device of this encapsulation comprises the contact pad that is positioned on the semiconductor element; And the insulating barrier that surrounds contact pad.The semiconductor device of this encapsulation also comprises the moulding compound that surrounds insulating barrier, and two vicinities of this moulding compound and insulating barrier and nonlinear surface contact.
In some other embodiment, provide a kind of semiconductor device of encapsulation.The semiconductor device of this encapsulation comprises the contact pad that is positioned on the semiconductor element; And the insulating barrier that surrounds contact pad.The semiconductor device of this encapsulation also comprises protective layer; And this protective layer is between contact pad and insulating barrier.The semiconductor device of this encapsulation also comprises the moulding compound that surrounds insulating barrier, and two vicinities of this moulding compound and insulating barrier and nonlinear surface contact.
In other other embodiment, provide a kind of method of encapsulated semiconductor device.This method comprises provides semiconductor device, and this semiconductor device has contact pad.This method also is included in the semiconductor device top and forms insulating barrier, and the thickness of contact pad is greater than the thickness of insulating barrier.This method also comprises and forms moulding compound to cover the interval between semiconductor device and semiconductor device and the adjacent semiconductor device.These two semiconductor device all are positioned on the carrier wafer.In addition, this method comprises by removal and is positioned at the moulding compound of contact pad top and the surface that insulating barrier comes the planarization semiconductor device.
Although described embodiments of the invention and advantage thereof in detail, should be appreciated that, can under the situation of the spirit and scope of the present invention that do not deviate from the claims restriction, carry out various changes, replacement and change therein.For example, those skilled in the art will be readily appreciated that, parts described herein, function, technology and material can change and still within the scope of the invention.And the application's scope is not limited in the specific embodiment of technology, machine, manufacturing, material component, device, method and the step described in the specification.To be readily appreciated that according to the present invention as those of ordinary skills, can utilize be used for carrying out the function substantially the same with corresponding embodiment described herein or obtaining substantially the same result's technology, machine, manufacturing, material component, device, method or step of existing or exploitation from now on according to the present invention.Therefore, claims are expected at and comprise such technology, machine, manufacturing, material component, device, method or step in its scope.

Claims (10)

1. the semiconductor device of an encapsulation comprises:
Contact pad is positioned on the semiconductor element;
Insulating barrier surrounds described contact pad; And
Moulding compound surrounds described insulating barrier, wherein, two vicinities of described moulding compound and described insulating barrier and nonlinear surface contact.
2. the semiconductor device of encapsulation according to claim 1, wherein, wiring layer is arranged on the described contact pad and is physically connected to described contact pad, and wherein, described wiring layer extends to outside the border of described semiconductor element.
3. the semiconductor device of encapsulation according to claim 1, wherein, the described insulating barrier that surrounds described contact pad has thin and thick portion, and wherein, the thickness of described thin portion is in about 1 μ m to the scope of about 30 μ m.
4. the semiconductor device of encapsulation according to claim 1, wherein, protective layer is between described contact pad and described insulating barrier.
5. the semiconductor device of encapsulation according to claim 1, wherein, described contact pad is the copper post and has underbump metallization layer below.
6. the semiconductor device of encapsulation according to claim 1, wherein, the thickness of described contact pad is greater than the thickness of described insulating barrier.
7. the semiconductor device of an encapsulation comprises:
Contact pad is positioned on the semiconductor element;
Insulating barrier surrounds described contact pad;
Protective layer, wherein, described protective layer is between described contact pad and described insulating barrier; And
Moulding compound surrounds described insulating barrier, wherein, two vicinities of described moulding compound and described insulating barrier and nonlinear surface contact.
8. the method for an encapsulated semiconductor device, described method comprises:
Semiconductor device is provided, and wherein, described semiconductor device has contact pad;
Form insulating barrier above described semiconductor device, wherein, the thickness of described contact pad is greater than the thickness of described insulating barrier;
Form moulding compound to cover described semiconductor device and the interval between described semiconductor device and adjacent semiconductor device, wherein, these two semiconductor device all are positioned on the carrier wafer; And
Be positioned at the described moulding compound of described bond pad top and the surface that described insulating barrier comes the described semiconductor device of planarization by removal.
9. method according to claim 8 also comprises:
Above described semiconductor device, form redistributing layer (RDL), wherein, described RDL is connected to described contact pad, and wherein, described RDL extends to outside the border of described semiconductor device.
10. method according to claim 8 also comprises:
Between described contact pad and described insulating barrier, form protective layer.
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