CN102637608A - 半导体器件和形成用于3d fo-wlcsp的垂直互连结构的方法 - Google Patents

半导体器件和形成用于3d fo-wlcsp的垂直互连结构的方法 Download PDF

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CN102637608A
CN102637608A CN2012100297574A CN201210029757A CN102637608A CN 102637608 A CN102637608 A CN 102637608A CN 2012100297574 A CN2012100297574 A CN 2012100297574A CN 201210029757 A CN201210029757 A CN 201210029757A CN 102637608 A CN102637608 A CN 102637608A
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sealant
semiconductor element
conductive layer
layer
projection
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CN102637608B (zh
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林耀剑
陈康
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Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件和形成用于3D FO-WLCSP的垂直互连结构的方法。一种半导体器件具有临时载体。半导体管芯以有源表面面向临时载体并被安装到临时载体。沉积具有在临时载体上的第一表面和与第一表面相对的第二表面的密封剂，并且所述密封剂被沉积在半导体管芯的背面上。临时载体被除去。在半导体管芯的外围中的密封剂的一部分被除去以在密封剂的第一表面中形成开口。互连结构形成在半导体管芯的有源表面上并且延伸到密封剂层中的开口中。形成通路，并且该通路从密封剂的第二表面延伸到开口。第一凸块形成在通路中并且电连接到互连结构。

Description

半导体器件和形成用于3D FO-WLCSP的垂直互连结构的方法
要求国内优先权
本申请是2009年10月2日提交的美国专利申请No. 12/572,590的部分继续申请。本申请进一步要求2011年2月10日提交的临时申请No. 61/441,561和2011年2月21日提交的临时申请No. 61/444,914的优先权。本申请根据35 U.S.C. § 120要求上述申请的优先权。
技术领域
本发明总体上涉及半导体器件，并且更具体地说涉及具有用于三维（3D）扇出型晶片级芯片规模封装（FO－WLCSP）的垂直互连结构的半导体器件。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（base current）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个半导体管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个半导体管芯并且封装管芯以提供结构支撑和环境隔离。在此使用的术语“半导体管芯”不仅指词的单数形式而且指词的复数形式，并且因此不仅可以指单个半导体器件而且可以指多个半导体器件。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占位空间（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的半导体管芯的前端工艺可以实现更小的半导体管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占位空间的半导体器件封装。
半导体制造的另一个目标是制造具有充分热耗散的半导体器件。高频半导体器件通常产生更多热。在没有有效热耗散的情况下，产生的热可能降低性能、降低可靠性、并且减小半导体器件的使用年限。
可以利用导电直通硅通路（TSV）或直通孔通路（THV）实现包括多级半导体器件（3D器件集成）的FO-WLCSP和外部器件之间的电互连。在大部分TSV和THV中，通路的侧壁和底侧被共形地电镀有导电材料以增强粘附。然后例如通过电镀工艺通过铜沉积，TSV和THV被填充另一种导电材料。TSV和THV形成通常包括通路填充的相当长的一段时间，这减少了每单位小时（UPH）生产计划。电镀所需要的设备，例如电镀槽，和侧壁钝化增加了制造成本。另外，可能在通路内形成空隙，这引起缺陷并且降低器件的可靠性。TSV和THV可能是制造半导体封装中的垂直电互连的慢并且昂贵的方法。这些互连方案也具有半导体管芯放置精确度、载体除去之前和之后的翘曲控制、以及工艺成本管理的问题。
3D FO-WLCSP和外部器件之间的电互连除了包括TSV和THV之外，进一步包括再分配层（RDL）。RDL用作用于封装内的电互连（包括与封装I/O焊盘的电互连）的中间层，所述封装I/O焊盘提供从3D FO-WLCSP内的半导体管芯到3D FO-WLCSP外部的点的电连接。RDL可以形成在3D FO-WLCSP内的半导体管芯的正面和背面上。然而，包括在半导体管芯的正面和背面上的多个RDL的形成对于制造用于3D FO-WLCSP的电互连而言可能是慢并且昂贵的方法，并且可能导致较高的制造成本。
发明内容
存在为3D半导体器件提供互连结构的需要。因此，在一个实施例中，本发明是一种制造半导体器件的方法，所述方法包括以下步骤：提供临时载体，以有源表面面向临时载体安装半导体管芯，以及沉积具有在临时载体上的第一表面和与第一表面相对的第二表面的密封剂。第二表面在半导体管芯的背面上。所述方法进一步包括以下步骤：除去临时载体，除去在半导体管芯的外围中的密封剂的一部分以在密封剂的第一表面中形成开口，在半导体管芯的有源表面上形成互连结构并且延伸进入开口中，形成从密封剂的第二表面到开口的通路，以及在通路中形成电连接到互连结构的第一凸块。
在另一个实施例中，本发明是一种制造半导体器件的方法，所述方法包括以下步骤：提供具有有源表面的半导体管芯，在半导体管芯的外围中和半导体管芯的背面上沉积密封剂，所述密封剂具有第一表面和与第一表面相对的第二表面，从第一表面除去密封剂的一部分以形成开口，在半导体管芯的有源表面上形成互连结构并且延伸进入开口中，形成从密封剂的第二表面到开口的通路，以及在通路中沉积电连接到互连结构的导电材料。
在另一个实施例中，本发明是一种制造半导体器件的方法，所述方法包括以下步骤：提供具有有源表面的半导体管芯，在半导体管芯的外围中沉积密封剂，所述密封剂具有第一表面和与第一表面相对的第二表面，在半导体管芯的外围中沉积从密封剂的第一表面延伸到第二表面的导电材料，以及在半导体管芯的有源表面上形成互连结构并且电连接到导电材料。
在另一个实施例中，本发明是一种半导体器件，所述半导体器件包括具有有源表面的半导体管芯。密封剂被沉积在半导体管芯的外围中，所述密封剂具有第一表面和与第一表面相对的第二表面。互连结构形成在半导体管芯的有源表面上。导电通路从密封剂的第二表面延伸到互连结构。
附图说明
图1示出具有安装到其表面的不同类型封装的印刷电路板（PCB）；
图2a-2c示出安装到PCB的典型半导体封装的更多细节；
图3a-3c示出具有被划片街区（saw street）分开的多个半导体管芯的半导体晶片；
图4a-4k示出形成用于FO-WLCSP的垂直互连结构的过程；
图5a-5b示出具有带有导电柱的垂直互连结构的FO-WLCSP；
图6示出具有垂直互连结构的FO-WLCSP的替换实施例；
图7示出用于FO-WLCSP的垂直互连结构的多层UBM；
图8示出具有带有导电柱和凸块的垂直互连结构的FO-WLCSP的替换实施例；
图9a-9b示出具有垂直互连结构的FO-WLCSP，所述垂直互连结构在导电柱下具有RDL；
图10a-10b示出形成用于3D FO-WLCSP的垂直互连结构的另一个过程；
图11示出在半导体管芯上具有密封剂的具有垂直互连结构的FO-WLCSP；
图12示出在半导体管芯上具有密封剂的具有另一个垂直互连结构的FO-WLCSP；
图13a-13x示出形成用于3D FO-WLCSP的垂直互连结构的另一个过程；
图14a-14d示出在具有垂直互连结构的3D FO-WLCSP上安装凸起的半导体器件的过程；
图15a-15d示出形成用于3D FO-WLCSP的垂直互连结构的另一个过程；
图16a-16d示出形成用于3D FO-WLCSP的垂直互连结构的另一个过程；
图17示出具有垂直互连结构的FO-WLCSP的另一个实施例；
图18a-18b示出具有垂直互连结构的FO-WLCSP的替换实施例，所述垂直互连结构具有导电柱；
图19a-19b示出具有导电通路的3D FO-WLCSP的另一个实施例；
图20a-20b示出在半导体管芯上具有密封剂的3D FO-WLCSP；
图21a-21c示出具有阶梯形密封剂的3D FO-WLCSP；
图22a-22c示出包括热沉或屏蔽层的3D FO-WLCSP的另一个实施例；
图23示出具有破裂停止层的3D FO-WLCSP；
图24a-24b示出包括水平扩展的互连结构的3D FO-WLCSP；以及
图25a-25b示出包括水平扩展的互连结构的3D FO-WLCSP的另一个实施例。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electroless plating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。在一个实施例中，利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。在另一个实施例中，利用溶剂将未经受光的光致抗蚀剂（负性光致抗蚀剂）图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个半导体管芯，并且然后封装半导体管芯用于结构支撑和环境隔离。为单体化半导体管芯，沿被叫做划片街区或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个半导体管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（stud bump）、导电胶、或接合线（bond wire）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或PCB 12的电子器件10，所述芯片载体衬底或PCB 12具有多个安装在它的表面上的半导体封装。电子器件10可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件10可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件10可以是更大系统的子部件。例如，电子器件10可以是蜂窝式电话、个人数字助理（PDA）、数码摄像机（DVC）或其它电子通信装置的一部分。可替换地，电子器件10可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、射频（RF）电路、分立器件、或其它半导体管芯或电部件。对于将被市场接受的这些产品而言，小型化和减轻重量是必需的。半导体器件之间的距离必须被减小以实现更高的密度。
在图1中，PCB 12提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）14形成在PCB 12的表面上或各层内。信号迹线14提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线14也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中半导体管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括接合线封装16和倒装芯片18，被示出在PCB 12上。另外，几种第二级封装，包括球栅阵列（BGA）20、凸块芯片载体（BCC）22、双列直插式封装（DIP）24、岸面栅格阵列（land grid array，LGA）26、多芯片模块（MCM）28、四侧无引脚扁平封装（quad flat non-leaded package，QFN）30、以及四侧扁平封装32被示出安装在PCB 12上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 12。在一些实施例中，电子器件10包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用不太昂贵的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来不是很贵，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 12上的DIP 24的更多细节。半导体管芯34包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯34的有源区内的其它电路元件。接触焊盘36是一层或多层的导电材料，例如铝（AL）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag），并且电连接到形成在半导体管芯34内的电路元件。在DIP 24的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯34安装到中间载体38。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线40和接合线42在半导体管芯34和PCB 12之间提供电互连。密封剂44被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染半导体管芯34或接合线42来进行环境保护。
图2b示出安装在PCB 12上的BCC 22的更多细节。半导体管芯46利用底层填充材料或环氧树脂粘附材料50被安装到载体48上。接合线52在接触焊盘54和56之间提供第一级封装互连。模塑料或密封剂60被沉积在半导体管芯46和接合线52上以为所述器件提供物理支撑和电隔离。接触焊盘64利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB 12的表面上以防止氧化。接触焊盘64电连接到PCB 12中的一个或多个导电信号迹线14。凸块66被形成在BCC 22的接触焊盘56与PCB 12的接触焊盘64之间。
在图2c中，利用倒装芯片型第一级封装将半导体管芯18面朝下地安装到中间载体76。半导体管芯18的有源区78包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区78内的其它电路元件。半导体管芯18通过凸块80被电连接和机械连接到载体76。
BGA 20 利用凸块82电连接和机械连接到具有BGA型第二级封装的PCB 12。半导体管芯18通过凸块80、信号线84、以及凸块82电连接到PCB 12中的导电信号迹线14。模塑料或密封剂86被沉积在半导体管芯18和载体76上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯18上的有源器件到PCB 12上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯18可以在没有中间载体76的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 12。
图3a示出具有用于结构支撑的基底衬底材料92（例如硅、锗、砷化镓、磷化铟、或碳化硅）的半导体晶片90。多个半导体管芯或部件112形成在晶片90上，被稳定的、管芯间的晶片区域或划片街区94分开，如上所述。划片街区94提供切割区域以将半导体晶片90单体化成单个半导体管芯112。
图3b示出半导体晶片90的一部分的截面图。每个半导体管芯112具有背表面96和有源表面97，所述有源表面97包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面97内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯112也可以包括集成无源器件（IPD），例如电感器、电容器、和电阻器，用于RF信号处理。在一个实施例中，半导体管芯112是倒装芯片型器件。
利用PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在有源表面97上形成导电层98。导电层98可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层98用作电连接到有源表面97上的电路的接触焊盘。可以离半导体管芯112的边缘第一距离并排设置接触焊盘98，如图3b中所示。可替换地，接触焊盘98可以多行偏移使得第一行接触焊盘被设置得离管芯的边缘为第一距离，并且与第一行交替的第二行接触焊盘被设置得离管芯的边缘为第二距离。
使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在接触焊盘98上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到接触焊盘98。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块114。在一些应用中，凸块114被二次回流以改善到接触焊盘98的电接触。凸块114也可以被压缩结合到接触焊盘98。凸块114表示一种可以形成在接触焊盘98上的互连结构。所述互连结构也可以使用柱形凸块、微凸块、或其它电互连。
在图3c中，利用锯条或激光切割工具99，通过划片街区94，半导体晶片90被单体化成单个半导体管芯112。
相对于图1和图2a-2c，图4a-4k示出形成用于3D FO-WLCSP的垂直互连结构的过程。在图4a中，衬底或晶片100包括伪或牺牲基底材料，例如硅（Si）、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃环氧树脂、氧化铍、或其它合适的低成本、刚性材料或体半导体材料，用于结构支撑。
界面层102可以是临时接合膜或刻蚀停止层。临时接合膜可以是热或光可释放材料。刻蚀停止层可以是具有湿法腐蚀选择性的金属膜、二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、或有机膜。利用层压、PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化沉积界面层102。在后面的步骤中通过光或热可释放界面层102。可替换地，可以在除去载体100之后通过刻蚀工艺除去界面层102。在一个实施例中，界面层102是SiO2/Si3N4薄膜并且用作刻蚀停止层。
利用沉积和图案化工艺在界面层102上形成导电层104以形成单独的部分或部104a-104d。图4b示出导电层104a-104d的顶视图或平面图，其中导电层104a通过暴露界面层102的间隙106与导电层104b-104d电隔离或部分隔离。导电层104可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层104的沉积使用PVD、CVD、溅射、电解电镀、无电极电镀、金属蒸发、金属溅射、或其它合适的金属沉积工艺。在一个实施例中，导电层104a是用于为后来形成的导电柱传导电流的固态膜。导电层104b-104d包括电镀种子层和凸块下金属化（UBM）焊盘，所述凸块下金属化（UBM）焊盘包括多层选择性电镀的Ni/Au、钛（Ti）/Cu、钛钨（TiW）/Cu、Ti/Cu/镍钒（NiV）/Cu、或它们的组合。UBM焊盘104b-104d提供可接合的焊盘用于与凸块114接合，并且可以进一步提供扩散屏障和可湿性的种子层。
在图4c中，光致抗蚀剂层108沉积在界面层102和导电层104上。通过刻蚀显影工艺，光致抗蚀剂层108的一部分被暴露并且被除去。利用选择性电镀或其它合适的工艺在导电层104a上的光致抗蚀剂108的被除去的部分中形成导电柱或杆110。导电柱110是Cu、Al、钨（W）、Au、焊料、或其它合适的导电材料。在一个实施例中，通过在光致抗蚀剂108的被图案化的区域中电镀Cu来形成导电柱110。在一个实施例中，导电柱110具有范围为2－120微米（μm）的高度。光致抗蚀剂108被剥离，留下单独的导电柱110。在另一个实施例中，可以利用焊料球或柱形凸块替代导电柱110。
在图4d中，来自图3a-3c的半导体管芯112以倒装芯片布置利用凸块114被安装到UBM焊盘104b-104d，使得半导体管芯112的有源表面面向载体100。可替换地，凸块或互连114形成在UBM焊盘104b-104d上，而不是在接触焊盘98上，使得当半导体管芯被安装在UBM焊盘上时半导体管芯112被安装到凸块或互连114。在另一个实施例中，无源部件被安装到UBM焊盘104b-104d。因此，相同的导电层104工作用于倒装芯片接合放置和导电柱电镀。
图4e示出利用浆料印刷（paste printing）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器（applicator）在半导体管芯112、导电层104、界面层102上以及导电柱110周围沉积的密封剂或模塑料116。密封剂116可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂116不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。密封剂116具有被调整到与基底半导体材料（例如Si，在100℃到300摄氏度（℃）的范围内具有高的玻璃软化温度（Tg））的热膨胀系数匹配的热膨胀系数（CTE）以减小翘曲。可以利用填充物，例如粉末、纤维、或布料添加物，来调整密封剂116的CTE。合适的密封剂材料通常特性在于类似于Si的良好热导率、低收缩率、大于1.0 kohm-cm的高电阻率、小于3.5的低介电常数、以及小于0.02的低介电损耗。
密封剂116经受研磨或等离子体刻蚀以暴露导电柱110和半导体管芯112的顶表面。可替换地，利用部分暴露的成型工艺沉积密封剂116使得密封剂116不覆盖导电柱110和半导体管芯112的顶表面。在两种情况中，导电柱110都表示直通模塑互连（TMI）结构。导电柱110的暴露的表面的高度小于半导体管芯112的背面表面的高度。结果，邻近半导体管芯112的背面表面的密封剂116的高度大于形成在载体100上以及形成在半导体管芯112的占位空间外部的导电柱110的外围中的密封剂116的高度。密封剂116的顶表面的一部分包括锥形或倾斜轮廓，所述锥形或倾斜轮廓从形成在导电柱110的外围中的密封剂116的第一高度延伸到在第二高度处的半导体管芯112的背面表面。第二高度大于第一高度。在一个实施例中，第一高度和第二高度之间的差在10-200 μm的范围内。可以通过利用背面研磨或其它合适的工艺除去半导体管芯112的背面表面的一部分以及在半导体管芯的背面的外围中的密封剂116的一部分来改变第一高度和第二高度之间的差。
在图4f中，利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在导电柱110、密封剂116、和半导体管芯112上形成绝缘或钝化层118。绝缘层118包括一层或多层的SiO2、Si3N4、SiON、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、聚酰亚胺、苯并环丁烯（benzocyclobutene，BCB）、聚苯并恶唑（polybenzoxazoles，PBO）、或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层118是在低于200℃低固化的光敏介电聚合物。绝缘层118被共形地施加到导电柱110、密封剂116、和半导体管芯112，遵循导电柱110、密封剂116、和半导体管芯112的轮廓，并且均匀地覆盖导电柱110、密封剂116、和半导体管芯112。在一个实施例中，通过刻蚀或其它合适的工艺除去绝缘层118的一部分以暴露导电柱110的顶表面。绝缘层118被用来平面化晶片表面形貌并且是可选的。
利用图案化和金属沉积工艺，例如印刷、PVD、CVD、溅射、电解电镀、无电极电镀、金属蒸发、金属溅射、或其它合适的金属沉积工艺，在导电柱110和绝缘层118上形成导电层120。导电层120是一层或多层的Al、Cu、Sn、Ni、Au、Ag、Ti、或其它合适的导电材料。在一个实施例中，导电层120是包含Ti/Cu或Ti/Al合金的多层RDL结构。导电层120遵循绝缘层118、在导电柱110上的绝缘层118中的开口、以及被绝缘层118中的开口暴露的导电柱110的部分的轮廓。导电层120用作RDL以相对于导电柱110延伸电连接。
利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在绝缘层118和导电层120上形成绝缘或钝化层122。绝缘层122包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层122是在低于200℃低固化的光敏介电聚合物。绝缘层122形成在绝缘层118和导电层120上以平面化晶片表面形貌并且保护导电层。通过刻蚀或其它合适的工艺除去绝缘层122的一部分以暴露导电层120用于封装级互连。根据互连功能所需要的，可以将附加的绝缘层和导电层添加到器件结构。
在图4g中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘焙、激光扫描、或湿法脱模来除去载体100和界面层102。在载体和界面层除去之前或之后在导电层120和绝缘层122上形成可选的保护层124。在载体和界面层除去期间导电层104a-104d保持如图4b中所示。然后通过选择性图案化和湿法腐蚀或其它合适的工艺除去导电层104a的一部分以形成如图4h中的截面图和图4i中的平面图中所示的包括互连线126和焊盘128的设计图案。导电层104被图案化使得UBM焊盘104b-104d、互连线126、和焊盘128与后面形成的凸块一起提供半导体器件内的电连接并且提供到半导体器件外部的点的下一级电连接。在一个实施例中，除去导电层104a的一部分进一步形成附加的电路部件，例如电感器。
在图4h中，利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在半导体管芯112的有源表面、导电层104、和密封剂116上形成绝缘或钝化层130。绝缘层130包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层130是在低于200℃低固化的光敏介电聚合物。绝缘层130形成在导电层104上并且保护导电层104。通过刻蚀或其它合适的工艺除去绝缘层130的一部分以暴露导电层104的一部分。
图4i示出半导体器件的平面图，所述半导体器件包括导电层104、UBM焊盘104b-104d、互连线126、焊盘128、和绝缘层130，其被配置成使得稍后形成的凸块将提供半导体器件内的电连接并且提供到半导体器件外部的点的下一级电连接。
图4j示出来自图4h的包括导电层104a、导电层104d、和绝缘层130的区域132的进一步的细节。导电层104a-104d均包括层叠的顶部浸润层134、阻挡层136、和底部浸润层138，例如Cu/NiV/Cu、Cu/TiW/Cu、或Cu/Ti/Cu。在层叠的浸润和阻挡层、以及绝缘层130之间形成粘附层140。在一个实施例中，粘附层140是Ti膜层。可替换地，粘附层140是TiW、Al、或铬（Cr）。绝缘层130形成在导电层104a-104d上。通过干法刻蚀、湿法腐蚀、或其它合适的工艺除去被形成在绝缘层130中的开口暴露的粘附层140的一部分以暴露绝缘层130的占位空间外部的底部浸润层138。
类似于图4j，图4k示出来自图4h的包括导电层104a、导电层104d、和绝缘层130的区域132的替换实施例。导电层104a-104d包括具有顶部浸润层142、阻挡层144、可选的底部浸润层146、和粘附层148的多层金属叠层。粘附层148包括Ti、TiW膜、或其它合适的材料。利用图案化和金属沉积工艺，例如印刷、PVD、CVD、溅射、电解电镀、无电极电镀、金属蒸发、金属溅射、或其它合适的金属沉积工艺，在粘附层148上形成导电层150。导电层150可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。在一个实施例中，导电层150是电镀的Cu并且通过使用导电层104作为用于选择性电镀的种子层而形成。通过刻蚀或其它合适的工艺除去导电层150的一部分以形成电感器。可以通过干法刻蚀、湿法腐蚀、或其它合适的工艺除去粘附层148的一部分以在形成导电层150之前或之后暴露底部浸润层146。在两种情况下，都在导电层150上形成绝缘层130之前除去粘附层148的所述部分。
图5a示出来自图4a-4k的3D FO-WLCSP，其中导电凸块材料利用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺被沉积在导电层104a-104d上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层104a-104d。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块152和154。在一些应用中，凸块152和154被二次回流以改善到导电层104a-104d的电接触。凸块也可以被压缩结合到导电层104a-104d。凸块152用作互连线126和UBM焊盘104b-104d之间的桥，参见例如图4i和5b。凸块154被制作得比凸块152高，在没有电短路凸块152的情况下用于下一级互连。凸块152和154表示一种可以形成在导电层104a-104d上的互连结构。所述互连结构也可以使用接合线、3D互连、导电胶、柱形凸块、微凸块、或其它电互连。3D FO-WLCSP通过包括导电层104、TMI导电柱110、导电层120、以及凸块152和154的垂直互连结构为半导体管芯112提供到外部器件的电连接。
图6示出类似于来自4a-4k的3D FO-WLCSP的3D FO-WLCSP的替换实施例，其中类似的元件具有相同的数字。在图6中，利用图案化和金属沉积工艺，例如印刷、PVD、CVD、溅射、电解电镀、无电极电镀、金属蒸发、金属溅射、或其它合适的金属沉积工艺，在导电层104和密封剂116上形成导电层156。导电层156可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。在类似于来自图4a-4f的载体100和界面层102的载体和界面层被除去之后在导电层104和密封剂116上形成导电层156。导电层156在半导体管芯112的凸块114、导电柱110、和稍后形成的用于下一级互连的凸块之间提供电路径。导电层104和156在相同的工艺步骤中被形成或沉积在一起。然后在两个分开的步骤中通过图案化和刻蚀或其它合适的工艺除去导电层104和156的部分。在形成导电柱110之前除去导电层104的一部分。在载体和界面层被除去之后除去导电层156的一部分，使得导电层156的剩余部分是用于稍后形成的凸块的UBM。所述剩余部分也是在稍后形成的凸块、导电柱110、和半导体管芯112之间提供电互连的RDL。
利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在导电层156和密封剂116上形成绝缘或钝化层158。绝缘层158包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层158是在低于200℃低固化的光敏介电聚合物。绝缘层158被共形地施加到导电层156和密封剂116，遵循导电层156和密封剂116的轮廓，并且保护导电层156和密封剂116。通过刻蚀或其它合适的工艺除去绝缘层158的一部分以暴露导电层156的一部分用于随后的电互连。
利用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺在导电层156上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层156。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块160。在一些应用中，凸块160被二次回流以改善到导电层156的电接触。凸块也可以被压缩结合到导电层156。凸块160表示一种可以形成在导电层156上的互连结构。所述互连结构也可以使用接合线、3D互连、导电胶、柱形凸块、微凸块、或其它电互连。3D-WLCSP的凸块160通过包括导电层104和156、TMI导电柱110、和导电层120的垂直互连结构为半导体管芯112提供到外部器件的电连接。
图7示出来自图6的包括导电层104和156的区域162的进一步的细节。导电层104a-104d均包括具有顶部浸润层163和阻挡层164的多层金属叠层。在一个实施例中，浸润层163是Cu并且阻挡层164是NiV或Ni。类似地，导电层156也包括具有可选的中间粘附层165、可选的阻挡层166、底部浸润层167、和底部粘附层168的多层金属叠层。在一个实施例中，粘附层165是Ti或TiW，阻挡层166是NiV或Ni，浸润层167是Cu，并且粘附层168是Ti。导电层104和156被形成为分开的层，或者可替换地，所述导电层在相同的工艺步骤中被形成或沉积在一起。当导电层104和156被形成为分开的层时，在形成导电柱110之前形成并且图案化导电层104，并且在除去类似于图4a-4f中所示的载体100和界面层102的临时载体和界面层之后形成导电层156。当在相同的工艺步骤中形成导电层104和156时，通过图案化和刻蚀或其它合适的工艺在两个分开的步骤中除去各个导电层的一部分。在形成导电柱110之前从浸润层163和阻挡层164除去导电层104的一部分。从粘附层168除去导电层156的一部分使得导电层156的剩余部分是用于稍后形成的凸块的UBM。导电层156的剩余部分也是在稍后形成的凸块、导电柱110、和半导体管芯112之间提供电互连的RDL。在载体和界面层被除去之后，导电层156被配置为UBM和RDL。
图8示出类似于来自4a-4k的3D FO-WLCSP的3D FO-WLCSP的互连结构的替换实施例。在载体和界面层上形成类似于4a-4k中所示的导电层104的导电层170以形成单独的部分或部170a-170d。导电层170a与导电层170b-170d电隔离。在一个实施例中，导电层170b-170d包括电镀的种子层和UBM焊盘，所述UBM焊盘包括多层选择性电镀的Ni/Au、Ti/Cu、或Ti/Cu/NiV/Cu。
类似于图4c中的导电杆110的导电柱或杆176形成在导电层170a上。以倒装芯片布置利用凸块174将半导体管芯172（类似于图4d中的半导体管芯112）安装到UBM焊盘170b-170d。在另一个实施例中，无源部件可以被安装到UBM焊盘170b-170d。
在半导体管芯172上、在导电层170上、在类似于载体100和界面层102的载体和界面层上、以及在导电柱176周围沉积第一密封剂或模塑料178（类似于图4e中的密封剂116）。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器沉积密封剂178。密封剂178可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂178不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。密封剂178具有被调整到与基底半导体材料（例如Si，在100℃到300℃的范围内具有高Tg）的CTE匹配的CTE以减小翘曲。可以利用填充物例如粉末、纤维、或布料添加物来调整密封剂178的CTE。合适的密封剂材料通常特性在于类似于Si的良好热导率、低收缩率、大于1.0 kohm-cm的高电阻率、小于3.5的低介电常数、以及小于0.02的低介电损耗。
密封剂178经受研磨或等离子体刻蚀以暴露导电柱176和半导体管芯172的顶表面。可替换地，利用部分暴露的成型工艺沉积密封剂178使得密封剂178不覆盖导电柱176和半导体管芯172的顶表面。在两种情况中，导电柱176都表示TMI结构。导电柱176的暴露的表面的高度小于半导体管芯172的背面表面的高度。结果，邻近半导体管芯172的背面表面的密封剂178的高度大于形成在载体上以及形成在半导体管芯172的占位空间外部的导电柱176的外围中的密封剂178的高度。密封剂178的顶表面179的一部分包括锥形或倾斜轮廓，所述锥形或倾斜轮廓从形成在导电柱176的外围中的密封剂178的第一高度延伸到在第二高度处的半导体管芯172的背面表面。第二高度大于第一高度。在一个实施例中，第一高度和第二高度之间的差在10-200 μm的范围内。可以通过利用背面研磨或其它合适的工艺除去半导体管芯172的背面表面的一部分以及在半导体管芯的背面的外围中的密封剂178的一部分来改变第一高度和第二高度之间的差。
利用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺在导电柱176上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电柱176。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块180。在一些应用中，凸块180被二次回流以改善到导电柱176的电接触。凸块也可以被压缩结合到导电柱176。凸块180表示一种可以形成在导电柱176上的互连结构。所述互连结构也可以使用导电胶、柱形凸块、微凸块、或其它电互连。因此，凸块180被形成在导电柱176上并且被电连接到导电柱176以形成具有增加的高度或支座（standoff）的TMI结构。
在第一密封剂178上、在半导体管芯172上、以及在凸块180周围利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器沉积第二密封剂或模塑料181。密封剂181可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂181不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。密封剂181具有被调整到与基底半导体材料（例如Si，在100℃到300℃的范围内具有高Tg）的CTE匹配的CTE以减小翘曲。可以利用填充物例如粉末、纤维、或布料添加物来调整密封剂181的CTE。合适的密封剂材料通常特性在于类似于Si的良好热导率、低收缩率、大于1.0 kohm-cm的高电阻率、小于3.5的低介电常数、以及小于0.02的低介电损耗。
密封剂181包括第一或底表面182，所述第一或底表面182被共形地施加到密封剂178的顶表面179并且遵循密封剂178的顶表面179的轮廓，所述密封剂178的顶表面179包括从导电柱176的外围的第一高度延伸到在第二高度处的半导体管芯172的背面表面的锥形或倾斜轮廓。密封剂181也包括与第一或底表面182相对形成的第二或顶表面183。第二或顶表面183是平面并且不与第一或底表面182的轮廓平行。在一个实施例中，利用部分暴露的成型工艺沉积密封剂181使得密封剂181的第二或顶表面183不覆盖凸块180的顶表面或一部分。可替换地，密封剂181的第二或顶表面183覆盖凸块180的顶表面或一部分，并且密封剂181经受研磨或等离子体刻蚀来除去密封剂181的一部分以暴露凸块180的顶表面或一部分。在两种情况下，凸块180都被暴露为TMI结构的一部分，所述TMI结构相对于仅包括导电柱176的TMI结构具有增加的高度或支座。
利用图案化和金属沉积工艺，例如印刷、PVD、CVD、溅射、电解电镀、无电极电镀、金属蒸发、金属溅射、或其它合适的金属沉积工艺，在凸块180和密封剂181上形成导电层184。导电层184是一层或多层的Al、Cu、Sn、Ni、Au、Ag、Ti、或其它合适的导电材料。在一个实施例中，导电层184是包含Ti/Cu或Ti/Al合金的多层RDL结构。导电层184被共形地施加到凸块180的顶表面或一部分和密封剂181的第二或顶表面183并且遵循凸块180的顶表面或一部分和密封剂181的第二或顶表面183的轮廓。导电层184用作RDL以相对于凸块180和导电柱176延伸电连接。
利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在第二密封剂181和导电层184上形成绝缘或钝化层186。绝缘层186包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层186是在低于200℃低固化的光敏介电聚合物。绝缘层186形成在密封剂181和导电层184上以平面化晶片表面形貌并且保护导电层。通过刻蚀或其它合适的工艺除去绝缘层186的一部分以暴露导电层184用于封装级互连。根据互连功能所需要的，可以将附加的绝缘层和导电层添加到器件结构。
通过化学腐蚀、机械剥离、CMP、机械研磨、热烘焙、激光扫描、或湿法脱模来除去载体和界面层（类似于图4g中的载体100和界面层102）。然后通过选择性图案化和湿法腐蚀或其它合适的工艺除去导电层170a的一部分以形成包括类似于图4h和图4i中所示的互连线126和焊盘128的互连线和焊盘的设计图案。导电层170a也可以被图案化以形成附加的电路部件，例如电感器。
在半导体管芯172的有源表面、导电层170、以及密封剂178上形成绝缘或钝化层188（类似于图4h中的绝缘层130）。绝缘层188被形成在导电层170上并且保护导电层170。通过刻蚀或其它合适的工艺除去绝缘层188的一部分以暴露导电层170的一部分。
导电凸块材料被沉积在导电层170a-170d上以形成球形球或凸块190和192，类似于图5a中所示的形成凸块152和154的工艺。凸块190用作互连线和UBM焊盘之间的桥，类似于图4i和5b中的互连线126和UBM焊盘128。凸块192被制作得比凸块190大，在没有电短路凸块190的情况下用于下一级互连。凸块190和192表示一种可以形成在导电层170a-170d上的互连结构。所述互连结构也可以使用接合线、3D互连、导电胶、柱形凸块、微凸块、或其它电互连。3D FO-WLCSP通过包括导电层170、TMI导电柱176、导电层184、以及凸块180、190、和192的垂直互连结构为半导体管芯172提供到外部器件的电连接。
图9a-9C示出类似于图6的3D FO-WLCSP的3D FO-WLCSP的互连结构的替换实施例。图9a与图6的不同之处在于包括导电层218，这在下面进行更详细讨论。在图9a中，在载体和界面层上形成导电层200（类似于图6中所示的导电层104）以形成单独的部分或部200a-200d。单独的部分或部200a-200d在图9b中以平面图示出。导电层200a通过间隙203与导电层200b-200d电隔离。在一个实施例中，导电层200b-200d包括电镀的种子层和UBM焊盘，所述UBM焊盘包括多层选择性电镀的Ni/Au、Ti/Cu、或Ti/Cu/NiV/Cu。
在导电层200a上形成导电柱或杆206（类似于图6中的导电杆110）。以倒装芯片布置利用凸块204将半导体管芯202（类似于图6中的半导体管芯112）安装到UBM焊盘200b-200d。在另一个实施例中，无源部件可以被安装到UBM焊盘200b-200d。图9a中所示的密封剂208、绝缘层210、导电层212、和绝缘层214分别类似于如图4a-4k和图6中所示的密封剂116、绝缘层118、导电层120、和绝缘层122。
在载体和界面层上形成或沉积材料（例如提供密封剂208、绝缘层210、导电层212、和绝缘层214）之后，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘焙、激光扫描、或湿法脱模来除去载体和界面层（类似于图4g中的载体100和界面层102）。在载体和界面层除去期间导电层200a-200d保持如图9b中所示。然后通过选择性图案化和湿法腐蚀或其它合适的工艺除去导电层200a的一部分以形成包括图9a中的截面图和图9c中的平面图中所示的互连线和焊盘的设计图案。导电层200a也可以被图案化以形成附加的电路部件，例如电感器。
利用图案化和金属沉积工艺，例如印刷、PVD、CVD、溅射、电解电镀、无电极电镀、金属蒸发、金属溅射、或其它合适的金属沉积工艺，在导电层200和密封剂208上形成导电层218。导电层218可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。在导电层200a的一部分被除去之后在导电层200和密封剂208上形成导电层218以形成图9c中所示的互连线216和焊盘。导电层218在半导体管芯202的凸块204、导电柱206、和稍后形成的用于下一级互连的凸块之间提供电路径。因此，导电层218在半导体管芯202和半导体管芯外部的点之间提供互连，而不是使用凸块，例如图5a中所示的凸块152，来提供电互连。因此，图9a中所示的导电层200和218在不同的工艺步骤中形成。导电层200形成在载体和界面层上。导电层218在载体和界面层被除去之后形成在导电层200上。因此，图9中的导电层218的形成不同于来自图6的导电层156的形成，因为导电层156与导电层104一起并且在相同的工艺步骤中形成在载体和界面层上。
图9a进一步示出利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在导电层218和密封剂208上形成的绝缘或钝化层220。绝缘层220包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层220是在低于200℃低固化的光敏介电聚合物。绝缘层220被共形地施加到导电层218和密封剂208，遵循导电层218和密封剂208的轮廓，并且保护导电层218和密封剂208。通过刻蚀或其它合适的工艺除去绝缘层220的一部分以暴露导电层218的一部分用于随后的电互连。
利用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺在导电层218上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层218。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块222。在一些应用中，凸块222被二次回流以改善到导电层218的电接触。凸块也可以被压缩结合到导电层218。凸块222表示一种可以形成在导电层218上的互连结构。所述互连结构也可以使用接合线、3D互连、导电胶、柱形凸块、微凸块、或其它电互连。3D FO-WLCSP的凸块222通过包括导电层200和218、TMI导电柱206、和导电层212的垂直互连结构为半导体管芯202提供到外部器件的电连接。
图10a-10b示出形成用于3D FO-WLCSP的互连结构的另一个过程。在图10a中，衬底或晶片230包括伪或牺牲基底材料，例如Si、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃环氧树脂、氧化铍、或其它合适的低成本、刚性材料或体半导体材料，用于结构支撑。
界面层232被沉积在载体230上。界面层232可以是临时接合膜或刻蚀停止层。临时接合膜可以是热或光可释放材料。刻蚀停止层可以是SiO2、Si3N4、SiON、有机膜、或金属膜。利用层压、PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化沉积界面层232。在一个实施例中，界面层232是SiO2/Si3N4薄膜并且用作刻蚀停止层。
光致抗蚀剂层被沉积在界面层232上。通过刻蚀工艺暴露并且除去光致抗蚀剂的一部分。利用光刻工艺在光致抗蚀剂的被除去的部分中形成导电柱或杆234。利用选择性电镀或其它合适的工艺在界面层232上的光致抗蚀剂的被除去的部分中形成导电柱或杆234。导电柱234可以是Cu、Al、W、Au、焊料、或其它合适的导电材料。在一个实施例中，通过在光致抗蚀剂的被图案化的区域中电镀Cu来形成导电柱234。导电柱234具有范围为2－120 μm的高度。光致抗蚀剂被剥离，留下单独的导电柱234。在另一个实施例中，可以利用焊料球或柱形凸块替代TMI导电柱234。
利用预先施加并且可剥离的粘附剂238将多个具有接触焊盘237的半导体管芯236安装到界面层232。半导体管芯236均包括具有有源区的衬底，所述有源区包含模拟或数字电路，所述模拟或数字电路被实现为根据半导体管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、和形成在半导体管芯236的有源区内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。
利用PVD、CVD、电解电镀、无电极电镀、或其它合适的金属沉积工艺在半导体管芯236的有源表面上形成接触焊盘237。接触焊盘237可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。接触焊盘237电连接到有源表面上的电路。接触焊盘237可以被并排设置得离半导体管芯236的边缘为第一距离。可替换地，接触焊盘237可以多行偏移使得第一行接触焊盘被设置得离管芯的边缘为第一距离，并且与第一行交替的第二行接触焊盘被设置得离管芯的边缘为第二距离。
在半导体管芯236上、在载体230和界面层232上、以及在导电柱234周围沉积密封剂或模塑料240（类似于图4e中的密封剂116）。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器沉积密封剂240。密封剂240可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂240不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。密封剂240具有被调整到与基底半导体材料（例如Si，在100℃到300℃的范围内具有高Tg）的CTE匹配的CTE以减小翘曲。可以利用填充物例如粉末、纤维、或布料添加物来调整密封剂240的CTE。合适的密封剂材料通常特性在于类似于Si的良好热导率、低收缩率、大于1.0 kohm-cm的高电阻率、小于3.5的低介电常数、以及小于0.02的低介电损耗。
密封剂240经受研磨或等离子体刻蚀以暴露导电柱234的顶表面和半导体管芯236的背面表面。可替换地，利用部分暴露的成型工艺沉积密封剂240，使得密封剂240不覆盖导电柱234和半导体管芯236的顶表面。在两种情况中，导电柱234都表示TMI结构。导电柱234的暴露的表面的高度小于半导体管芯236的背面表面的高度。结果，邻近半导体管芯236的背面表面的密封剂240的高度大于形成在载体230上以及形成在半导体管芯236的占位空间外部的导电柱234的外围中的密封剂240的高度。密封剂240的顶表面的一部分包括锥形或倾斜轮廓，所述锥形或倾斜轮廓从形成在导电柱234的外围中的密封剂240的第一高度延伸到在第二高度处的半导体管芯236的背面表面。第二高度大于第一高度。在一个实施例中，第一高度和第二高度之间的差在10-200 μm的范围内。可以通过利用背面研磨或其它合适的工艺除去半导体管芯236的背面表面的一部分以及在半导体管芯236的背面的外围中的密封剂240的一部分来改变第一高度和第二高度之间的差。
利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在导电柱234、密封剂240、和半导体管芯236上形成绝缘或钝化层242。绝缘层242包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层242是在低于200℃低固化的光敏介电聚合物。绝缘层242被共形地施加到导电柱234、密封剂240、和半导体管芯236，遵循导电柱234、密封剂240、和半导体管芯236的轮廓，并且均匀地覆盖导电柱234、密封剂240、和半导体管芯236。在一个实施例中，通过刻蚀或其它合适的工艺除去绝缘层242的一部分以暴露电柱234的顶表面。绝缘层242被用来平面化晶片表面形貌并且是可选的。
利用图案化和金属沉积工艺，例如印刷、PVD、CVD、溅射、电解电镀、无电极电镀、金属蒸发、金属溅射、或其它合适的金属沉积工艺，在导电柱234和绝缘层242上形成导电层244。导电层244是一层或多层的Al、Cu、Sn、Ni、Au、Ag、Ti、或其它合适的导电材料。在一个实施例中，导电层244是包含Ti/Cu或Ti/Al合金的多层RDL结构。导电层244遵循绝缘层242、在导电柱234上的绝缘层242中的开口、以及被绝缘层242中的开口暴露的导电柱234的部分的轮廓。导电层244用作RDL以相对于导电柱234延伸电连接。
利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在绝缘层242和导电层244上形成绝缘或钝化层246。绝缘层246包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层246是在低于200℃低固化的光敏介电聚合物。绝缘层246形成在绝缘层242和导电层244上以平面化晶片表面形貌并且保护导电层。通过刻蚀或其它合适的工艺除去绝缘层246的一部分以暴露导电层244用于封装级互连。根据互连功能所需要的，可以将附加的绝缘层和导电层添加到器件结构。
在图10b中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘焙、激光扫描、或湿法脱模来除去载体230、界面层232和粘附剂238。在除去载体和界面层232之前或之后在导电层244和绝缘层246上形成与载体230相对的可选的保护层。
利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在半导体管芯236的有源表面、导电柱234和密封剂240上形成绝缘或钝化层248。绝缘层248包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层248是在低于200℃低固化的光敏介电聚合物。绝缘层248形成在导电柱234和半导体管芯236上并且保护导电柱234和半导体管芯236。通过刻蚀或其它合适的工艺除去绝缘层248的一部分以暴露导电柱234和接触焊盘237的底部部分。
利用图案化和金属沉积工艺，例如印刷、PVD、CVD、溅射、电解电镀、无电极电镀、金属蒸发、金属溅射、或其它合适的金属沉积工艺在导电柱234、接触焊盘237和绝缘层242上形成导电层250。导电层250是一层或多层的Al、Cu、Sn、Ni、Au、Ag、Ti、或其它合适的导电材料。在一个实施例中，导电层250是包含Ti/Cu或Ti/Al合金的多层RDL结构。导电层250遵循绝缘层248、在导电柱234上的绝缘层248中的开口、以及被绝缘层248中的开口暴露的导电柱234的部分的轮廓。导电层250用作RDL以相对于导电柱234和半导体管芯236延伸电连接。
利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在导电层250和绝缘层248上形成绝缘或钝化层252。绝缘层252包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层252是在低于200℃低固化的光敏介电聚合物。绝缘层252形成在导电层250上并且保护导电层250。通过刻蚀或其它合适的工艺除去绝缘层252的一部分以暴露导电层250的一部分。
使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在导电层250上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层250。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块254。在一些应用中，凸块254被二次回流以改善到导电层250的电接触。凸块也可以被压缩结合到导电层250。凸块254表示一种可以形成在导电层250上的互连结构。所述互连结构也可以使用接合线、3D互连、导电胶、柱形凸块、微凸块、或其它电互连。3D FO-WLCSP的凸块254通过包括导电层244、导电层250、以及TMI导电柱234的垂直互连结构为半导体管芯236提供到外部器件的电连接。
图11示出类似于来自4a-4k的3D FO-WLCSP的3D FO-WLCSP的替换实施例，其中类似的元件具有相同的数字。图11与图4a-4k的不同之处在于密封剂260保持设置在半导体管芯112上而不是如例如在图4e中所示地暴露半导体管芯相对于密封剂的背面表面。
在图11中，类似于图4e中的密封剂116的密封剂或模塑料260沉积在半导体管芯112上、载体和界面层上以及导电柱110周围。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器来沉积密封剂260。密封剂260可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂260不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。密封剂260具有被调整以便与基底半导体材料（例如Si，在100oC到300oC的范围内具有高Tg）的CTE匹配的CTE以减小翘曲。可以利用填充物例如粉末、纤维、或布料添加物来调整密封剂260的CTE。合适的密封剂材料通常特性在于类似于Si的良好热导率、低收缩率、大于1.0 kohm-cm的高电阻率、小于3.5的低介电常数、以及小于0.02的低介电损耗。
密封剂260经受研磨或等离子体刻蚀以暴露导电柱110的顶表面。该研磨和刻蚀没有暴露半导体管芯112的背面表面以便密封剂层260保留在半导体管芯112的整个背面表面上并且钝化半导体管芯112。可替换地，利用部分暴露的成型工艺沉积密封剂260使得密封剂260不覆盖导电柱110的顶表面，而是覆盖半导体管芯112的背面表面。在两种情况中，导电柱110都表示TMI结构，其中导电柱110的一部分从密封剂260被暴露。导电柱110的暴露的表面的高度小于半导体管芯112的背面表面的高度。结果，在半导体管芯112的背面表面上的密封剂260的高度大于形成在半导体管芯112的占位空间外部的导电柱110的外围中的密封剂260的高度。密封剂260的顶表面的一部分包括锥形或倾斜轮廓，所述锥形或倾斜轮廓从形成在导电柱110的外围中的密封剂260的第一高度延伸到在第二高度处的半导体管芯112的背面表面上。第二高度大于第一高度。在一个实施例中，第一高度和第二高度之间的差在10-200 μm的范围内。可以通过除去半导体管芯112的背面表面上的密封剂260的一部分来改变第一高度和第二高度之间的差。
图12示出类似于来自10a-10b的3D FO-WLCSP的3D FO-WLCSP的替换实施例，其中类似的元件具有相同的数字。图12与图10a-10b的不同之处在于密封剂262保持设置在半导体管芯236上而不是在图10a-10b中所示地暴露半导体管芯相对于密封剂240的背面表面。
在图12中，类似于图10a-10b中的密封剂240的密封剂或模塑料262沉积在半导体管芯236上、载体和界面层上以及导电柱234周围。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器来沉积密封剂262。密封剂262可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂262不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。密封剂262具有被调整以便与基底半导体材料（例如Si，在100oC到300oC的范围内具有高Tg）的CTE匹配的CTE以减小翘曲。可以利用填充物例如粉末、纤维、或布料添加物来调整密封剂262的CTE。合适的密封剂材料通常特性在于类似于Si的良好热导率、低收缩率、大于1.0 kohm-cm的高电阻率、小于3.5的低介电常数、以及小于0.02的低介电损耗。
密封剂262经受研磨或等离子体刻蚀以暴露导电柱234的顶表面。该研磨和刻蚀没有暴露半导体管芯236的表面以便密封剂层262保留在半导体管芯236的整个背面表面上并且钝化半导体管芯236。可替换地，利用部分暴露的成型工艺沉积密封剂262使得密封剂262不覆盖导电柱234的顶表面，而是覆盖半导体管芯236的背面表面。在两种情况中，导电柱234都表示TMI结构，其中导电柱234的一部分从密封剂262被暴露。导电柱234的暴露的表面的高度小于半导体管芯236的背面表面的高度。结果，在半导体管芯236的背面表面上的密封剂262的高度大于形成在半导体管芯236的占位空间外部的导电柱234的外围中的密封剂262的高度。密封剂262的顶表面的一部分包括锥形或倾斜轮廓，所述锥形或倾斜轮廓从形成在导电柱234的外围中的密封剂262的第一高度延伸到在第二高度处的半导体管芯236的背面表面上。第二高度大于第一高度。在一个实施例中，第一高度和第二高度之间的差在10-200 μm的范围内。可以通过除去半导体管芯236的背面表面上的密封剂260的一部分和在半导体的背面的外围中的密封剂262的一部分来改变第一高度和第二高度之间的差。
相对于图1和图2a-2c，图13a-13x示出形成用于3D FO-WLCSP的垂直互连结构的另一过程。在图13a中，衬底或临时载体270包括伪或牺牲基底材料，例如Si、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃环氧树脂、氧化铍、或其它合适的低成本、刚性材料或体半导体材料，用于结构支撑。
界面层或双面载体胶带272形成在载体270上作为临时粘性接合膜或刻蚀停止层。作为载体胶带，界面层272可以是热或光可释放材料。在替换实施例中，界面层272可以是具有湿法腐蚀选择性的金属膜、SiO2、Si3N4、SiON、或有机膜的刻蚀停止层。利用层压、PVD、CVD、印刷、旋涂、喷涂、烧结、热氧化或其它合适的工艺来沉积界面层272。
在图13b中，半导体管芯276，类似于来自图3a-3c的半导体管芯112，被安装到载体270上，其中半导体管芯的有源表面面向衬底270和界面层272。半导体管芯276包括形成在半导体管芯276的有源表面上的接触焊盘277。接触焊盘277由导电材料制成（所述导电材料例如是Al、Cu、Sn、Ni、Au或Ag）并且电连接到形成在半导体管芯276内的电路元件。通过PVD、CVD、电解电镀、无电极电镀、或其它合适的工艺形成接触焊盘277。在半导体管芯276的有源表面上形成绝缘或钝化层278。利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化将绝缘层278共形地施加到半导体管芯276上。绝缘层278包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层278覆盖并保护形成在半导体管芯276的有源表面内的一个或多个晶体管、二极管或其它电路元件，包括IPD，例如电感器、电容器和电阻器。绝缘层278的一部分从接触焊盘277的一部分上被除去。接触焊盘277上的绝缘层278中的开口便于将来与半导体管芯276的电互连。
以半导体管芯276的有源表面在前，半导体管芯被安装到载体270和界面层272上。绝缘层278接触界面层272，包括绝缘层278的在绝缘层278中的开口的外围中和在所述开口周围的部分，以便防止随后形成的密封剂接触接触焊盘277。
在图13c中，利用丝网印刷、喷射或其它合适的工艺将印刷点或结280形成在界面层272上以及形成在半导体管芯276的外围中。印刷点280是溶剂可去除材料，例如光致抗蚀剂层、干膜、或膏剂，其在暴露于150oC热处理达一小时之后通过刻蚀工艺被除去。可替换地，印刷点280是在暴露于150oC热处理达一小时之后的水可去除材料。在将半导体276安装到载体270和界面层272上之前形成印刷点280。可替换地，在将半导体276安装到载体270和界面层272上之后形成印刷点280。根据应用的配置和设计，印刷点280包括圆或圆形形状、环形形状、坝状结构、直线形状或任何其它合适的形状。印刷点280在稍后形成的密封剂中提供空腔或空隙，如在下面进一步详细讨论的。
类似于图13b-13c，图13d-13e示出替换实施例，其包括形成在绝缘层278上的临时平面化和保护层282。尽管13d-13w示出用于包括临时平面化层282的使用的半导体器件的工艺流程，但是该临时平面化层是可选的，并且类似于图13d-13w中所示的那些步骤的步骤用于形成3-D FO-WLCSP器件，而没有使用临时平面化层282。因此，在图中呈现的任何实施例可以利用或者可以不利用临时平面化层282制造。利用旋涂、层压、丝网印刷、切涂（slit coating）、喷涂或其它合适的工艺将临时平面化层282共形地施加到绝缘层278上并且遵循绝缘层278的轮廓。临时平面化层282是溶剂可去除材料，例如光致抗蚀剂层或干膜，其在暴露于150oC热处理达一小时之后通过刻蚀工艺被除去。可替换地，临时平面化层282是在暴露于150oC热处理达一小时之后的水可去除材料。临时平面化层282的第一表面遵循绝缘层278的顶表面的轮廓，遵循绝缘层278中的开口的侧壁的轮廓，并且形成在半导体管芯276的接触焊盘277上。临时平面化层282的与第一表面相对的第二表面基本上是平面并且便于半导体管芯276随后安装到载体270上的界面层272。临时平面化层282在半导体管芯276的有源表面和界面层272的顶表面之间提供增加的偏移。
在图13e中，如之前在图13c中所描述的，将印刷点或结280形成在界面层272上以及形成在半导体管芯276的外围中。图13e还示出半导体管芯276安装到载体270和界面层272上，其中半导体管芯的有源表面面向载体和界面层。临时平面化层282接触界面层272，提供在半导体管芯276的有源表面和界面层272的顶表面之间的增加的偏移，防止随后形成的密封剂形成在接触焊盘277上。
在图13f中，可选的背面对准单元284形成在载体270和界面层272的表面上。背面对准单元284包含用于随后激光钻孔和作记号或者用于下一级表面安装技术(SMT)对准的对准标记。当背面对准单元的与界面层272相对的部分被暴露时，背面对准单元284提供对准。多个背面对准单元284位于载体270的便于多个半导体管芯276在重构晶片级的对准的部分上。背面对准单元284例如位于在载体270附近交替间隔的四个对准位置处，用于全局或晶片级对准。载体270和半导体管芯276的对准便于在重构晶片级执行的随后的工艺步骤，包括激光钻孔、作记号和光刻曝光工艺。
在图13g中，利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器在半导体管芯276、印刷点280、对准单元284之上和周围以及在界面层272上沉积密封剂或模塑料286。密封剂286可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂286不导电，提供物理支撑，并且在环境上保护半导体器件免受外部元件和污染物的影响。在一个实施例中，密封剂286具有被调整以与基底半导体材料（例如Si，在100℃到300℃的范围内具有高Tg）的CTE匹配的CTE以减小翘曲。可以利用填充物例如粉末、纤维、或布料添加物来调整密封剂286的CTE。合适的密封剂材料通常特性在于类似于Si的良好热导率、低收缩率、大于1.0 kohm-cm的高电阻率、小于3.5的低介电常数、以及小于0.02的低介电损耗。
在于载体270上安装和密封半导体管芯276之前，半导体管芯276经历背面研磨工艺以将半导体管芯276减薄到期望的厚度。可替换地，半导体管芯276在被安装到载体270且被密封剂286密封之后在重构晶片级经历背面研磨。
在图13h中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘焙、紫外（UV）光、激光扫描或湿法脱模来除去载体270和界面层272以暴露密封剂286的底表面和临时平面化层282或绝缘层278的底表面。图13h还示出除去印刷点280以在位于半导体管芯276、绝缘层278和临时平面化层282的外围中的密封剂286中形成开口或空隙288。可替换地，在没有形成印刷点280的情况下，在除去载体270之后，除去密封剂286的一部分以形成开口288。被除去来形成开口的密封剂286的所述部分是通过激光钻孔或其它合适的方法来除去的。开口288是形成在半导体管芯276、绝缘层278和临时平面化层282的外围中的密封剂286的底表面中的浅通路或空腔。开口288从密封剂286的底表面部分地延伸，但是不完全通过密封剂286。开口288被配置成接收随后形成的绝缘和导电层，其形成互连层的一部分，其提供相对于半导体管芯276的电连接。
图13i示出具有侧壁290和底部部分292的开口288。侧壁290是锥形的而不是如图13h所示是垂直的。底部部分292是平面的，并且具有小于与密封剂286的底表面共面的开口288的一部分的占位空间的面积的面积。在形成开口288时通过激光钻孔或其它合适的方法形成锥形侧壁290。可替换地，在最初形成开口288之后，例如在除去印刷点280的情况下形成开口288之后，形成锥形侧壁290。作为另一个替换，当除去印刷点280时形成具有锥形侧壁的开口288。图13i还示出在半导体管芯276的外围周围形成开口294。通过激光钻孔或其它合适的工艺通过除去密封剂286来形成开口294，并且开口294在半导体管芯276和密封剂286之间的界面处提供光滑的轮廓。
在图13j中，除去临时平面化层282。利用包括溶剂的湿法清洁工艺、利用二氧化碳（CO2）配料或其它合适的工艺除去临时平面化层282。临时平面化层282的去除暴露了绝缘层278和接触焊盘277的未被绝缘层278覆盖的部分。临时平面化层282的去除在半导体管芯276的有源表面和界面层272的顶表面之间提供增加的偏移，还提供开口或空腔296。开口296形成在半导体管芯276的有源表面上并且从密封剂286的底部或背面表面的水平延伸到半导体管芯276的绝缘层278和接触焊盘277。开口296的表面遵循密封剂286的侧壁的轮廓，沿绝缘层278、沿接触焊盘277上绝缘层278中的开口的侧壁以及沿接触焊盘277的表面延伸。
在替换实施例中，临时平面化层282没有被完全除去，而是保留在半导体管芯276的有源表面和绝缘层278上作为附加绝缘或介电层。在实施例中，其中临时平面化层282没有被完全除去，临时平面化层包含一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、氧化铪（HfO2）、光敏聚酰亚胺、非光敏聚酰亚胺、BCB、PBO、介电膜材料、或具有类似绝缘和结构特性的具有小于或等于380°C的固化温度的其它材料。通过激光钻孔、UV曝光或其它合适的工艺将临时平面化层282的一部分从接触焊盘277上除去以形成开口或通路，其暴露接触焊盘277的一部分。从接触焊盘277上除去的临时平面化层282的所述部分是在固化临时平面化层之后被除去的，或者可替换地，是在半导体管芯276被单体化且被安装到载体270上之前被除去的。而且，绝缘层278的一部分还可以在与除去临时平面化层282的所述部分的相同工艺步骤中被除去以便暴露接触焊盘277的所述部分。
在图13k中，通过沉积和图案化绝缘或钝化层298并且沉积和图案化导电层302来形成FO-WLCSP互连或RDL的第一部分。绝缘层298被共形地施加到密封剂286、包括侧壁290和底表面292的开口288、以及开口296，并且具有遵循密封剂286、包括侧壁290和底表面292的开口288、以及开口296的轮廓的第一表面。绝缘层298具有与第一表面相对的第二平面表面。绝缘层298包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合物抗蚀剂、液晶聚合物（LCP）、层压化合物膜、具有填充物的绝缘膏剂、焊料掩模抗蚀剂膜、液体模塑化合物、粒状模塑化合物、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。使用印刷、旋涂、喷涂、层压或其它合适的工艺沉积绝缘层298。绝缘层298随后被图案化且使用UV曝光被固化，其后是显影或其它合适的工艺。根据半导体管芯276的配置和设计，通过激光烧蚀、刻蚀或其它合适的工艺来除去绝缘层298的一部分以暴露半导体管芯276的接触焊盘277和开口288的底表面。
导电层302被图案化并且被沉积在密封剂286、半导体管芯276和绝缘层298上。导电层302可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层302的沉积使用PVD、CVD、电解电镀、无电极电镀、或其它合适的工艺。在一个实施例中，导电层302包括TiW/Cu、Ti/Cu的种子层，或偶联剂/Cu。通过溅射、无电极电镀或者通过与无电极电镀相组合地沉积层压的Cu箔来沉积种子层。在一个实施例中，导电层302在绝缘层298中的开口内具有至少8um的厚度。绝缘层298中的开口完全延伸通过开口288上和接触焊盘277上的绝缘层。导电层302用作RDL以将来自半导体管芯276的电连接延伸到半导体管芯276外部的点。形成在开口288内的导电层302的一部分在开口288的底表面292上形成连接盘（land），其用作随后钻孔或从密封剂286的顶侧除去密封剂286的一部分的停止层。在一个实施例中，形成在开口288内的导电层302的所述部分具有大于形成在接触焊盘277上的导电层302的所述部分的宽度的宽度。
在图13l中，绝缘或钝化层306被共形地施加到绝缘层298和导电层302，并且遵循绝缘层298和导电层302的轮廓。绝缘层306包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合物抗蚀剂、LCP、层压化合物膜、具有填充物的绝缘膏剂、焊料掩模抗蚀剂膜、液体模塑化合物、粒状模塑化合物、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。使用印刷、旋涂、喷涂、层压或其它合适的工艺沉积绝缘层306。绝缘层306随后被图案化且使用UV曝光被固化，其后是显影或其它合适的工艺。通过激光烧蚀、刻蚀或其它合适的工艺来除去绝缘层306的一部分以暴露导电层302的多个部分。
导电层310被图案化并且被沉积在导电层302、绝缘层306、半导体管芯276和密封剂286上。导电层310可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层310的沉积使用PVD、CVD、电解电镀、无电极电镀、或其它合适的工艺。在一个实施例中，导电层310包括TiW/Cu、Ti/Cu的种子层，或偶联剂/Cu。通过溅射、无电极电镀或者通过与无电极电镀相组合地沉积层压的Cu箔来沉积种子层。在一个实施例中，导电层310在绝缘层306中的开口内具有至少8um的厚度。绝缘层306中的开口完全延伸通过导电层302上的绝缘层。导电层310用作RDL以将来自半导体管芯276的电连接通过导电层302延伸到半导体管芯276外部的点。
在图13m中，绝缘或钝化层314被共形地施加到绝缘层306和导电层310，并且遵循绝缘层306和导电层310的轮廓。绝缘层314包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合物抗蚀剂、LCP、层压化合物膜、具有填充物的绝缘膏剂、焊料掩模抗蚀剂膜、液体模塑化合物、粒状模塑化合物、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。使用印刷、旋涂、喷涂、层压或其它合适的工艺沉积绝缘层314。绝缘层314随后被图案化且使用UV曝光被固化，其后是显影或其它合适的工艺。通过激光烧蚀、刻蚀或其它合适的工艺来除去绝缘层314的一部分以暴露导电层310的多个部分。
导电层318被图案化并且被沉积在导电层310、绝缘层314、半导体管芯276和密封剂286上。导电层318可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层318的沉积使用PVD、CVD、电解电镀、无电极电镀、或其它合适的工艺。在一个实施例中，导电层318包括TiW/Cu、Ti/Cu的种子层，或偶联剂/Cu。通过溅射、无电极电镀或者通过与无电极电镀相组合地沉积层压的Cu箔来沉积种子层。在一个实施例中，导电层318在绝缘层314中的开口内具有至少8um的厚度，所述开口完全延伸通过导电层310上的绝缘层。根据半导体管芯276的配置和设计，导电层318用作RDL以将来自半导体管芯276的电连接通过导电层302和310延伸到半导体管芯276外部的点。放在一起，绝缘层298、306和314以及导电层302、310和318形成互连结构320。在互连320内包括的绝缘层和导电层的数目取决于电路布线设计的复杂性并且随其变化。因此，互连320可以包括任何数目的绝缘层和导电层来促进相对于半导体管芯276的电互连。而且，将以其它方式被包括在背面互连结构或RDL中的元件可以被集成作为互连320的一部分以相对于包括正面和背面互连或RDL的封装来简化制造和降低制作成本。
在图13n中，绝缘或钝化层322被共形地施加到绝缘层314和导电层318，并且遵循绝缘层314和导电层318的轮廓。绝缘层322包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合物抗蚀剂、LCP、层压化合物膜、具有填充物的绝缘膏剂、焊料掩模抗蚀剂膜、液体模塑化合物、粒状模塑化合物、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。使用印刷、旋涂、喷涂、层压或其它合适的工艺沉积绝缘层322。绝缘层322随后被图案化且使用UV曝光被固化，其后是显影或其它合适的工艺。通过激光烧蚀、刻蚀或其它合适的工艺来除去绝缘层322的一部分以暴露导电层318的多个部分。
使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在导电层318和绝缘层322上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层318。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块326。在一些应用中，凸块326被二次回流以改善到导电层318的电接触。在一个实施例中，凸块326被形成在UBM上，所述UBM具有浸润层、阻挡层和粘附层。凸块也可以被压缩结合到导电层318。凸块326表示一种可以形成在导电层318上的互连结构。所述互连结构也可以使用接合线、导电胶、柱形凸块、微凸块、或其它电互连。
图13o-13q，类似于图13n，示出可以电连接到互连320以将来自半导体管芯276的电连接延伸到半导体管芯276外部的点的替换互连结构。在图13o中，代替凸块326，凸块328形成在导电层318上。凸块328是Ni/Au、Ni/Pt/Au、或Ni/Pd/Au，并且被形成为I/O焊盘，用于将来自半导体管芯276的电连接延伸到半导体管芯276外部的点。
在图13p中，凸块332形成在导电层318上。凸块332包括电镀的铜铝并且被形成为I/O焊盘，用于将来自半导体管芯276的电连接延伸到半导体管芯276外部的点。
在图13q中，凸块336形成在导电层310上。凸块336包括电镀的铜铝并且被形成为I/O焊盘，用于将来自半导体管芯276的电连接延伸到半导体管芯276外部的点。图13q与图13n-13p的不同之处在于最后的绝缘层338，类似于绝缘层322，覆盖导电层310和凸块336两者。由此，最后的绝缘层338在形成凸块336之后形成。换句话说，在形成绝缘层338之前将凸块336形成在导电层310上。
在图13r中，背面研磨胶带342被施加到半导体管芯276、密封剂286、互连320和凸块326、328、332或336上。背面研磨胶带342接触互连320的最后或最底层，例如绝缘层322，并且还接触最后的I/O焊盘，例如凸块326。背面研磨胶带342遵循凸块326的表面的轮廓并且在凸块326周围和之间延伸。背面研磨胶带342包括具有高达270oC的热阻的胶带。背面研磨胶带342还包括具有热释放功能的胶带。背面研磨胶带342的实例包括UV胶带HT 440和非UV胶带MY-595。背面研磨胶带342为随后的背面研磨和从与互连320相对的密封剂286的背面表面或顶表面除去密封剂286的一部分提供结构支撑。
在图13r中，密封剂286的与互连320相对的顶表面经历利用研磨器344的研磨操作以平面化该表面并且减小密封剂的厚度。研磨操作将重构晶片的厚度减小到在50到600um的范围内的厚度。化学腐蚀也可以用于除去和平面化密封剂286。在研磨操作完成之后，密封剂层286覆盖半导体晶片276的背面表面。可替换地，在研磨操作之后半导体管芯276的背面表面从密封剂286暴露，并且半导体管芯276的厚度也被研磨操作减小。在另一个实施例中，背面研磨胶带342仅仅是具有UV或热释放功能的支撑胶带，使得该胶带当被除去时被除去而不用背面研磨工艺。
图13s示出这样的实施例，其中在研磨操作之后半导体管芯276的背面表面从密封剂286暴露。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器在半导体管芯276的背面表面和密封剂286上沉积密封剂或模塑料346，并且密封剂或模塑料346接触所述半导体管芯276的背面表面和密封剂286。密封剂346可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂346不导电，提供物理支撑，并且当存在需要保护半导体管芯276的背面时在环境上保护半导体器件免受外部元件和污染物的影响。
从图13r继续，图13t示出从半导体管芯276的外围以及从导电层302上除去密封剂286的一部分以形成开口350。开口350包括垂直或倾斜侧壁并且从密封剂286的背表面完全经过该密封剂延伸到开口288的底表面292。通过钻孔、激光烧蚀、高能水喷射、刻蚀、或其它合适的工艺形成开口350以暴露部分导电层302。在一个实施例中，开口350用作圆形的直通密封剂盲孔（TEBV），所述直通密封剂盲孔（TEBV）延伸到导电层302并且接触导电层302。可替换地，开口350包括任何形状的的截面轮廓。在背面研磨或支撑胶带342被附着到互连320和凸块326上时开口350被形成并且随后被清洁。通过将开口350形成为穿过半导体管芯276的外围中的密封剂286的TEBV，导电层302的一部分从密封剂286的背面被暴露。开口350被配置成为半导体管芯276提供随后的3D电互连而不使用TSV或THV。
图13u，类似于图13t，示出密封剂286的一部分从半导体管芯276的外围中以及导电层302上被除去以形成开口352。开口352包括具有倾斜的第一部分和垂直的第二部分的侧壁。开口352从密封剂286的背表面完全通过密封剂延伸到开口288的底表面292。通过钻孔、激光烧蚀、高能水喷射、刻蚀、或其它合适的工艺形成开口352以暴露部分导电层302。开口352用作TEBV，所述TEBV延伸到导电层302并且接触导电层302。在背面研磨或支撑胶带342被附着到互连320和凸块326上时开口352被形成并且随后被清洁。通过将开口352形成为穿过半导体管芯276的外围中的密封剂286的TEBV，导电层302的一部分从密封剂286的背面被暴露。开口352被配置成为半导体管芯276提供随后的3D电互连而不使用TSV或THV。
在图13v中，利用蒸发、电解电镀、无电极电镀、球滴、丝网印刷、喷射、或其它合适的工艺在开口350中以及导电层302上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层302。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块356。在一些应用中，凸块356被二次回流以改善到导电层302的电接触。在一个实施例中，凸块356形成在具有浸润层、阻挡层、和粘附层的UBM上。凸块也可以被压缩结合到导电层302。凸块356表示一种可以形成在导电层302上的互连结构。所述互连结构也可以使用接合线、Cu、Ag、或其它导电胶、柱形凸块、微凸块、具有Cu核的焊料球、被浸渍了焊料膏剂或焊料涂层的Cu球或柱、或其它电互连。凸块356形成用于下一级互连的3D互连。在一个实施例中，在重构晶片级利用沉积到开口350中的浆料印刷通过SMT形成凸块356。因此，通过凸块356、导电层302、互连320、凸块326、和半导体管芯276形成3D互连，从而在半导体管芯276的占位空间上没有背面互连或RDL的情况下形成用于3D FO-WLCSP的直通垂直电互连。
在图13w中，在完成密封剂286的研磨后、在形成并且清洁开口350后、并且在形成凸块356后除去背面研磨胶带342。可替换地，在完成密封剂286的研磨后并且在形成和清洁开口350后但在形成凸块356之前除去背面研磨胶带342。此外，利用锯条或激光切割装置360将重构晶片单体化成单个3D FO-WLCSP 362。单体化可以在除去背面研磨胶带342之前或之后发生。
图13x示出类似于来自图13w的3-D FO-WLCSP 362的3-D FO-WLCSP 366。3-D FO-WLCSP 366与FO-WLCSP 362的不同之处在于在不使用如图13b和13c所示的临时平面化层282的情况下形成3-D FO-WLCSP 366。因此，半导体管芯276相对于密封剂286的底表面的偏移，以及随后存在的从除去临时平面化层282得到的开口296在3-D FO-WLCSP 366中并不存在。然而，类似于在图13w中，利用锯条或激光切割装置368将重构晶片单体化成单个3-D FO-WLCSP 366。单体化可以在除去背面研磨胶带之前或之后发生。
3-D FO-WLCSP 362和366提供通过形成在半导体管芯的占位空间外部的垂直互连与互连I/O阵列的3-D电互连，而不使用在半导体管芯的占位空间内延伸的背面RDL。具有对准标记的可选的背面对准单元嵌入在密封剂中以便于下一级SMT对准和POP配置。激光钻孔或其它合适的方法用于在半导体管芯的有源表面的外围在密封剂的正面中形成开口。互连结构形成在半导体管芯的有源表面上并且延伸到密封剂的正面中的开口中。互连结构包括形成FO-WLCSP RDL的绝缘和导电层。将以其它方式被包括在背面互连结构或RDL中的元件可以被集成为形成在半导体管芯的有源表面上的单个互连结构的一部分。可替换地，背面RDL元件可以被包括在另一半导体器件的其它稍后安装的部件中作为POP配置的一部分。凸块或其它I/O互连形成在互连结构上。背面研磨胶带被施加到凸块上，并且密封剂的一部分和半导体管芯的背面的一部分在背面研磨工艺中被除去。激光钻孔或其它合适的工艺除去在半导体管芯的外围的密封剂的一部分以便于随后垂直互连（例如圆形TEBV）的形成，所述垂直互连从密封剂的背表面延伸到互连结构。除去背面研磨胶带。凸块或其它合适的导电材料形成在TEBV中以形成3D垂直互连用于下一级互连和POP配置。重构晶片被单体化。
从图13t继续，图14a-14d示出形成通过开口350与导电层320的电连接的另一个实施例。在图14a中，在重构晶片级通过印刷、喷射或其它合适的工艺将导电凸块材料370沉积在开口350中。导电凸块材料370是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、铟(In)、焊料，及其组合，带有可选的焊剂溶液。例如，导电凸块材料370可以是共晶Sn/Pb、高铅焊料、或无铅焊料。导电凸块材料370接触导电层302并且填充开口350的一部分，其小于开口的整体以便于随后的电互连。
在图14b中，具有凸块376的凸起的半导体器件或封装374在重构晶片级被安装在3-D FO-WLCSP 378上。半导体管芯374包括互连元件，其将以其它方式被包括在形成在半导体276的背面上的背面互连结构或RDL中，其没有被包括作为互连320的一部分。凸块376是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、In、焊料，及其组合，带有可选的焊剂溶液。例如，凸块376可以是共晶Sn/Pb、高铅焊料、或无铅焊料。使用拾取和放置操作或其它合适的操作安装半导体器件374。利用凸块376、面向3-D FO-WLCSP 378地安装半导体器件374，使得凸块376延伸到开口350中并且接触开口350内的导电凸块材料370。凸块376和导电凸块材料370之间的接触导致密封剂286和半导体器件374的表面之间的偏移380。半导体器件374的占位空间具有大于半导体管芯276的占位空间的面积的面积。由此，在半导体器件已经被安装到3-D FO-WLCSP 378之后，半导体管芯276的占位空间位于半导体器件374的占位空间内。
在图14c中，包括半导体器件374和3-D FO-WLCSP 378的重构晶片被加热以回流凸块材料370和凸块376。在一个实施例中，通过将凸块材料370和凸块376加热到它们的熔点以上，所述凸块材料370和凸块376被回流以形成球形球或凸块380。在一些应用中，凸块380被二次回流以改善到导电层302的电接触。凸块也可以被压缩结合到导电层302。凸块380表示一种可以形成在导电层302上的互连结构。所述互连结构也可以使用接合线、导电胶、柱形凸块、微凸块、或其它电互连。
在图14d中，利用锯条或激光切割装置384将包括半导体器件374的重构晶片单体化成单个3-D FO-PoP 386。在除去背面研磨胶带342之前单体化FO-PoP 386。可替换地，在完成密封剂286的研磨之后以及在形成和清洁开口350之后但是在单体化之前除去背面研磨胶带342。当在3-D FO-PoP 386的单体化之前除去背面研磨胶带342时，可选的切割胶带387被施加到凸块326上并且接触互连320的绝缘层322或者最后或最低层，遵循凸块326的表面的轮廓，并且在凸块326周围和之间延伸。
从图13t继续，图15a-15d示出用于形成通过开口350与导电层302的电连接的另一个方法。在从导电层320上除去密封剂286的一部分以形成开口350之后，除去背面研磨胶带342。
在图15b中，包括半导体管芯276的重构晶片388被对准并放置在可再用的载体390上。载体390由载体基底材料（例如金属）制成，其具有适合于最小化在随后的焊料回流循环中载体的翘曲的热导率和刚性特性。载体390包括多个半球形空腔392。空腔392被配置用于接收凸块326。空腔392具有小于凸块326的高度的高度。在一个实施例中，空腔392具有比凸块326的高度小至少5um的高度。可替换地，空腔392具有比凸块326的高度大5-100um的高度。凸块326和空腔392之间的高度差在绝缘层322和载体390的顶表面之间产生间隙或偏移394。空腔392还具有大于凸块326的宽度的宽度。在一个实施例中，空腔392具有比凸块326的宽度大至少10um的宽度。凸块326和空腔392之间的宽度差在凸块326和空腔392的轮廓或表面之间产生间隙或偏移。
空腔392和凸块326之间的偏移或区域包括不可浸润材料396。不可浸润材料396被沉积在载体390的支撑表面（包括载体392的表面）上并涂覆该支撑表面。不可浸润材料396包括高温涂层，例如高温特氟隆（Teflo）、Ti、TiN或其它相对于凸块326为惰性的薄膜材料。不可浸润材料396被配置用于在高温下接触凸块326而不与凸块326或绝缘层322反应或粘贴到凸块326或绝缘层322。例如，不可浸润材料396被配置成在大于或等于280oC的温度下不与凸块326或绝缘层322反应或粘贴到凸块326或绝缘层322。
在一个实施例中，载体390包括具有真空环或真空孔397的真空，其被配置用于保持重构晶片388与载体390和不可浸润材料396接触。
类似于图15b，图15c示出被对准并放置在可再用的载体390上的重构晶片388。图15c与图15b的不同之处在于来自图15b的绝缘层322和载体390的顶表面之间的偏移394被偏移398替换。偏移398在凸块326的表面和空腔392的底表面之间延伸，并且在一个实施例中包括在5-100um的范围内的距离。
在图15d中，在重构晶片388被安装到可再用载体390的情况下，凸块400被沉积或形成在开口350内。使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在开口350内和导电层302上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层302。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块400。在一些应用中，凸块400被二次回流以改善与导电层302的电接触。凸块也可以被压缩结合到导电层302。凸块400表示一种可以形成在导电层302上的互连结构。所述互连结构也可以使用接合线、导电胶、柱形凸块、微凸块、或其它电互连。
在形成凸块400之后，利用锯条或激光切割装置404将重构晶片388单体化成单个3D FO-WLCSP 406。
图16a-16d示出用于形成通过开口412与导电层302的电连接的替换方法。图16a示出在形成类似于来自图13n-13q的凸块或I/O连接326、328、332和336的导电凸块之前，背面研磨胶带410，类似于图13r的背面研磨胶带342，被施加到绝缘层322上。背面研磨胶带410包括具有高达270oC的热阻的胶带和具有热释放功能的胶带。背面研磨胶带410的实例包括UV胶带HT 440和非UV胶带MY-595。背面研磨胶带410为在密封剂286的背面表面或顶表面的密封剂286的可选的背面研磨提供结构支撑，如之前在图13r中所描述的。
在施加背面研磨胶带410之后，从导电层302上除去密封剂286的一部分以形成开口412。开口412包括垂直或倾斜侧壁并且从密封剂286的背表面完全经过该密封剂延伸到开口288的底表面292。通过钻孔、激光烧蚀、高能水喷射、刻蚀、或其它合适的工艺形成开口412以暴露部分导电层302。在一个实施例中，开口412用作圆形的TEBV，所述TEBV延伸到导电层302并且接触导电层302。可替换地，开口412包括任何形状的截面轮廓。在背面研磨或支撑胶带410被附着时，开口350被形成并且随后被清洁。通过将开口412形成为穿过半导体管芯276的外围的密封剂286的TEBV，导电层302的一部分从密封剂286的背面被暴露。
在图16b中，在可选的密封剂286的研磨之后以及在开口412的形成和清洁之后除去背面研磨胶带410。
在图16c中，在重构晶片414上形成临时支撑层416。临时支撑层416接触绝缘层322并包括高温胶带和热可释放的胶带。临时支撑层416在凸块418的形成和放置期间支撑重构晶片414，并且在凸块418的形成之后被除去。
使用蒸发、电解电镀、无电极电镀、球滴、丝网印刷压缩结合、或其它合适的工艺，通过在导电层302上和开口412内沉积导电凸块材料来形成凸块418。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层302。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块418。在一些应用中，凸块418被二次回流以改善到导电层302的电接触。凸块418表示一种可以形成在导电层302上的互连结构。所述互连结构也可以使用接合线、导电胶、柱形凸块、微凸块、或其它电互连。凸块418被形成为高度小于开口412的高度，使得凸块418凹在密封剂286的背面或顶表面以下。在一个实施例中，凸块418具有比开口412的高度小至少1um的高度。
在另一个实施例中，临时支撑层416是可选的并且在除去背面研磨胶带410之后不被施加。在没有临时支撑层416来提供对重构晶片414的结构支撑的情况下，如上所述地形成凸块418。当通过球滴工艺形成凸块418时，球滴机器的卡盘用于在放置凸块418期间提供临时支撑。球滴机器的卡盘被涂覆有顺应保护材料，例如特氟隆，以促进球滴工艺。
在图16d中，临时支撑层422被形成在重构晶片414上并接触密封剂286的背面表面。临时支撑层422包括高温胶带、热可释放胶带，并在凸块424的形成和放置期间支撑重构晶片414。
凸块424形成在重构晶片414上，与凸块418相对，并且与临时支撑层422相对。使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺通过在导电层318上沉积导电凸块材料来形成凸块424。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层318。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块424。在一些应用中，凸块424被二次回流以改善到导电层318的电接触。凸块也可以被压缩结合到导电层318。凸块424表示一种可以形成在导电层318上的互连结构。所述互连结构也可以使用接合线、导电胶、柱形凸块、微凸块、或其它电互连。
在另一个实施例中，临时支撑层422是可选的并且对于凸块424的形成没有被施加到重构晶片414。如上所述地形成凸块424，但是没有临时支撑层422来提供对重构晶片414的结构支撑。当通过球滴工艺形成凸块424时，球滴机器的卡盘用于在放置凸块424期间提供临时支撑。当用于支撑时，球滴机器的卡盘被涂覆有顺应保护材料，例如特氟隆。
在形成凸块424之后，临时支撑层422（如果使用了的话）被除去。利用锯条或激光切割装置426将重构晶片414单体化成单个3D FO-WLCSP 428。
图17示出类似于来自图13x的3-D FO-WLCSP 366的3-D FO-WLCSP 430。3-D FO-WLCSP 430与FO-WLCSP 366的不同之处在于在没有在密封剂286中形成开口288的情况下形成3-D FO-WLCSP 430。因此，导电层434的顶表面432与在表面432的外围的绝缘或钝化层438的顶表面436是平面，而不是包括如图13x所示在导电层的外围具有阶梯形配置的密封剂286。
图18a，类似于图13x，示出类似于来自图13x的3-D FO-WLCSP 366的3-D FO-WLCSP 442。3-D FO-WLCSP 442与FO-WLCSP 366的不同之处在于3-D FO-WLCSP 442与导电柱444和绝缘或钝化层446一起形成。导电柱444形成在密封剂450的正面448上、半导体管芯452的接触焊盘451上以及开口453内。使用图案化和金属沉积工艺，例如溅射、电解电镀和无电极电镀形成导电柱444。在一个实施例中，导电柱444是Cu。可替换地，导电柱444是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。在一个实施例中，导电柱444包括Cu电镀种子层，利用PVD将其沉积在密封剂450的正面448上、半导体管芯452的接触焊盘451上以及开口453内。导电柱444电连接到接触焊盘451、凸块454和互连结构456。
利用真空层压、浆料印刷、压缩模塑、旋涂或其它合适的工艺将绝缘层446形成在密封剂450上、半导体管芯452上和导电柱444周围。绝缘层446是LCP、层压化合物膜、具有填充物的绝缘膏剂、焊料掩模抗蚀剂膜、液体或粒状模塑化合物、光敏复合物抗蚀剂、以及光敏低固化温度介电抗蚀剂。在一个实施例中，绝缘层446包括可选的介电层，在密封剂450中形成开口453之后将所述可选的介电层施加到密封剂450的正面448上并在其上被图案化。在形成绝缘层446之后，绝缘层经历固化或UV曝光、显影和固化。在固化之后，通过研磨、激光钻孔或其它合适的工艺去除绝缘层446的一部分以暴露被绝缘层446覆盖的导电柱444的一部分。
图18b示出类似于来自图18a的3-D FO-WLCSP 442的3-D FO-WLCSP 462。3-D FO-WLCSP 462与FO-WLCSP 442的不同之处在于在没有在密封剂450中形成开口453的情况下形成3-D FO-WLCSP 462。因此，导电层466的顶表面464与在表面464的外围的密封剂450的正面468是平面，而不是包括如图18a所示在导电层的外围具有阶梯形配置的密封剂。
图19a，类似于图13x，包括通路或TSV 474和接触焊盘476的附加特征。通过深反应离子刻蚀(DRIE)、激光钻孔或其它合适的工艺形成通过半导体管芯478的通路474。使用PVD、CVD、电解电镀、无电极电镀或其它合适的金属沉积工艺利用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅、或其它合适的导电材料填充通路474。可替换地，多个柱形凸块或焊料球可以形成在通路内。通路474在半导体管芯478的有源表面从接触焊盘480延伸到半导体管芯478的背面以便为3-D FO-WLCSP 482提供直通垂直电互连。
接触焊盘或后TSV RDL 476形成在通路474上或形成在半导体管芯478的背面上。接触焊盘476利用导电材料制成，所述导电材料例如是Al、Cu、Sn、Ni、Au或Ag，并且电连接到通路474和接触焊盘480。通过PVD、CVD、电解电镀、无电极电镀或其它合适的工艺形成接触焊盘476。当在接触焊盘476上的密封剂484的背面或顶表面经历研磨操作以平面化该表面并减小密封剂的厚度时暴露接触焊盘476。在一个实施例中，在形成开口486之前通过背面研磨工艺暴露接触焊盘476。可替换地，可以在形成开口486之前或之后利用浅激光钻孔或其它合适的工艺暴露接触焊盘476。
图19b示出类似于来自图19a的3-D FO-WLCSP 482的3-D FO-WLCSP 490。3-D FO-WLCSP 490与FO-WLCSP 482的不同之处在于包括利用微凸块494安装在半导体管芯496的背面上的半导体管芯492。在面板级、在重构晶片级或者可替换地在SMT工艺之后安装半导体管芯492。
图20a示出类似于来自图13x的3-D FO-WLCSP 366的3-D FO-WLCSP 500。在图20a中，半导体管芯502的背面表面从密封剂504被暴露。密封剂或模塑料506被沉积在半导体管芯502的整个背面表面或顶表面以及密封剂504上并接触所述半导体管芯502的整个背面表面或顶表面以及密封剂504。利用真空层压、浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、旋涂、喷涂、或其它合适的工艺来沉积密封剂506，之后进行固化。密封剂506是具有或不具有Cu箔的LCP、层压化合物膜、具有填充物的绝缘膏剂、焊料掩模抗蚀剂膜、液体或粒状模塑化合物、光敏复合物抗蚀剂、以及光敏低固化温度介电抗蚀剂、或其它合适的材料。密封剂506不导电，提供物理支撑，并且在环境上保护半导体器件免受外部元件和污染物的影响。在一个实施例中，密封剂506具有等于或大于15ppm的CTE并且颜色为黑色。选择密封剂506的厚度和密封剂506的其它材料特性来获得3-D FO-WLCSP 500所期望的翘曲和可靠性性能。
图20b示出类似于来自图20a的3-D FO-WLCSP 500的3-D FO-WLCSP 510。不是在半导体管芯502的整个背面表面或顶表面以及密封剂504上沉积密封剂或模塑料506，密封剂512沉积在半导体管芯514的背面表面和密封剂516的一部分上。然而，密封剂512没有形成在开口518的外围。密封剂512提供物理支撑并且在环境上保护半导体器件514免受外部元件和污染物的影响。在一个实施例中，密封剂512具有等于或大于15ppm的CTE并且颜色为黑色。选择密封剂512的厚度和密封剂的其它材料特性来获得3-D FO-WLCSP 510所期望的翘曲和可靠性性能。
图21a示出类似于来自图13x的3-D FO-WLCSP 366的3-D FO-WLCSP 522。FO-WLCSP 522与FO-WLCSP 366的不同之处在于密封剂524与密封剂524的阶梯形部分526一起形成，所述阶梯形部分526具有从半导体管芯530的占位空间外部密封剂524的背表面的垂直偏移528。由此，阶梯形部分526形成阶梯模盖（mold cap），其从半导体管芯530的背面上突出。在形成密封剂524期间形成阶梯形部分526。可替换地，在选择性背面研磨工艺中形成阶梯形部分526。阶梯形部分526在半导体管芯530的背面上具有厚度532，并且在一个实施例中，厚度532小于半导体管芯530的厚度。在另一个实施例中，厚度532大于或等于半导体管芯530的厚度。厚度532、垂直偏移528和阶梯形部分526的长度和宽度被调整以便优化3-D FO-WLCSP 522的封装纵横比和在热性能方面的性能、以及翘曲。根据3-D FO-WLCSP 522的设计来调整阶梯形部分526的长度和宽度以形成大于半导体管芯530的占位空间的区域。可替换地，阶梯形部分526的长度和宽度被调整以形成小于或等于半导体管芯530的占位空间的区域。在一个实施例中，阶梯形部分526的外边缘与半导体管芯530的外边缘垂直对准。
图21b示出类似于来自图21a的3-D FO-WLCSP 522的3-D FO-WLCSP 538。密封剂540具有相对于半导体管芯544的占位空间外部的密封剂540的背表面的垂直偏移542。由此，垂直偏移542形成从半导体管芯544的背面上突出的阶梯模盖。垂直偏移542是在形成密封剂540期间形成的。可替换地，在选择性背面研磨工艺中形成垂直偏移542。半导体器件或封装546安装在半导体管芯544上并且利用凸块550电连接到导电层548。半导体器件546的底表面具有相对于半导体管芯544的占位空间外部的密封剂540的背表面的垂直偏移552。垂直偏移552的距离大于垂直偏移542的距离，使得半导体器件546的底表面不接触密封剂540的背表面，包括阶梯模盖的背表面。
图21c示出类似于来自图21b的3-D FO-WLCSP 538的3-D FO-WLCSP 556。密封剂558具有相对于密封剂558的顶表面或背面表面的垂直偏移560，其在半导体管芯562的背面上的密封剂中形成空腔561。垂直偏移560形成空腔561，该空腔561相对于该空腔的占位空间外部的密封剂558的顶表面或背面表面凹进并且低于所述外部密封剂558的顶表面或背面表面。空腔561是在密封剂558的形成期间形成的。可替换地，通过浅激光刻槽、湿法腐蚀或其它合适的方法在选择性背面研磨工艺中形成空腔561。空腔561被配置成为稍后安装的半导体器件提供空间，所述半导体器件例如是倒装芯片半导体器件、接合线BGA、接合线LGA、分立部件或其它半导体器件。
半导体器件或封装564安装在半导体管芯562上并且利用凸块568电连接到导电层566。半导体器件564的底表面具有相对于密封剂558的顶表面或背面表面的垂直偏移570。半导体器件或封装572安装到半导体器件564并且在凸块568之间。垂直偏移560和570的组合距离大于被半导体器件572占据的垂直距离。因此，半导体器件572适合在空腔561内并且位于密封剂558上且不接触密封剂558。
图22a示出类似于来自图13x的3-D FO-WLCSP 366的3-D FO-WLCSP 576。然而，FO-WLCSP 576不包括类似于在FO-WLCSP 366中用于顶侧电互连的凸块536的电互连或凸块的形成。在完成3-D FO-WLCSP 576之前不形成在开口578内的电互连。代替地，在完成3-D FO-WLCSP 576之后，在用于下一级互连或作为PoP组装工艺的一部分的SMT工艺期间在开口578中形成电互连。
图22b，类似于图22a，示出另一个实施例，其中类似于FO-WLCSP 366中的凸块356的电互连或凸块直到完成3-D FO-WLCSP 580之后才被形成。在用于下一级互连或作为PoP组装工艺的一部分的SMT工艺期间在开口582中形成电互连。与图22a形成对照，图22b示出半导体管芯584的背面从密封剂586暴露作为被单体化的3-D FO-WLCSP 580的一部分。
图22c，类似于图22b，示出FO-WLCSP 590，其中导电层592形成在密封剂594的顶表面或背面表面上或上面以及形成在半导体管芯596的背面上。导电层或膜592是Cu、Al、铁氧体或羰基铁、不锈钢、镍银、低碳钢、硅-铁钢、箔、导电树脂、和其它具有高热导率或能够阻挡或吸收电磁干扰（EMI）、射频干扰（RFI）、谐波失真和其它器件间干扰的材料。导电层592被图案化并且使用层压、印刷、电解电镀、无电极电镀、溅射、PVD、CVD或其它合适的金属沉积工艺被共形地沉积。导电层592可以与可选的绝缘或保护层596一起形成。
可选的绝缘层596形成在半导体管芯596的背面上。绝缘层596包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合物抗蚀剂、LCP、层压化合物膜、具有填充物的绝缘膏剂、焊料掩模抗蚀剂膜、液体模塑化合物、粒状模塑化合物、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。使用印刷、旋涂、喷涂、层压或其它合适的工艺沉积绝缘层596。
在形成开口598之前或之后，导电层592和可选的绝缘层596可以形成在密封剂594的背面和半导体管芯596上。在一个实施例中，导电层592用作热沉来改善3-D FO-WLCSP 590的热性能。在另一个实施例中，导电层592用作屏蔽层来阻挡或吸收EMI、RFI、谐波失真和其它干扰。
图23示出类似于来自图13w的3-D FO-WLCSP 362的3-D FO-WLCSP 600。3-D FO-WLCSP 600与FO-WLCSP 362的不同之处在于包括破裂停止层602。利用旋涂、真空层压、丝网印刷或其它合适的工艺，破裂停止层602被共形地施加到半导体管芯606上的绝缘层604上并且遵循该绝缘层604的轮廓。破裂停止层602包含一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、光敏聚酰亚胺、非光敏聚酰亚胺、BCB、PBO、介电膜材料、或具有类似绝缘和结构特性的具有小于或等于380°C的固化温度的其它材料。破裂停止层602具有高拉伸强度和高伸长率，其有助于防止3-D FO-WLCSP 600内的破裂。在一个实施例中，破裂停止层602具有大于或等于100兆帕(MPa)的拉伸强度以及在30-150%的范围内的伸长率。通过激光钻孔、反应离子刻蚀(RIE)、UV曝光或其它合适的工艺将破裂停止层602的一部分从接触焊盘277上除去以形成暴露接触焊盘277的一部分的开口或通路。从接触焊盘277上被除去的破裂停止层602的部分是在破裂停止层的固化之后被除去的，或者可替换地，是在将半导体管芯606单体化并且随后安装在3-D FO-WLCSP 600的一部分内之前被除去的。在一个实施例中，绝缘层604的一部分也在与除去破裂停止层602的所述部分相同的工艺步骤中被除去以便暴露接触焊盘277的所述部分。
图24a示出类似于来自图13w的3-D FO-WLCSP 362的3-D FO-WLCSP 610。3-D FO-WLCSP 610与FO-WLCSP 362的不同之处在于包括互连结构612，其相对于互连320水平地扩张。互连结构612包括导电层614，类似于导电层302，其延伸到密封剂620中的开口或空隙616和618中。开口616和618类似于图13h中的开口288，并且形成在密封剂620的正面中。开口624类似于来自图13t的开口350，并且形成在密封剂620的背面中和开口616上。开口624不形成在开口618上。因此，并不是形成在密封剂620的正面中的每个开口616和618都具有形成在密封剂620的背面中的对应开口624。不具有形成在密封剂620的背面中的对应开口624的开口618位于3-D FO-WLCSP 610内，使得凸块或正面I/O互连628形成在开口618上并且与开口618垂直地对准。被包括在互连结构612内的导电层和绝缘或钝化层的数目和配置随根据3-D FO-WLCSP 610的设计和功能的电路布线设计的复杂性变化，并且提供附加互连能力。
图24b，类似于图24a，示出具有延伸到开口636、638和640中的水平扩张互连结构634的FO-WLCSP 632。导电层642被共形地施加到绝缘或钝化层644并且遵循该绝缘或钝化层644的轮廓。导电层642延伸到开口636中，但是没有延伸到开口638和640中。开口638不具有形成在密封剂646的背面中的对应开口644，并且位于3-D FO-WLCSP 632内，使得凸块或正面I/O互连648形成在开口638上并且与开口638垂直地对准。导电层642的一部分尽管没有延伸到开口638中，但是确实在开口638和互连648之间延伸。类似地，开口640不具有形成在密封剂646的背面中的对应开口644，但是位于3-D FO-WLCSP 632内，使得凸块或正面I/O互连648形成在开口640上并且与开口640垂直地对准。导电层642的一部分没有在开口640和互连648之间延伸。被包括在互连结构634内的导电层和绝缘或钝化层的数目和配置随根据3-D FO-WLCSP 632的设计和功能的电路布线设计的复杂性变化。
图25a，类似于图24a，示出具有水平扩张互连结构654的3-D FO-WLCSP 652。3-D FO-WLCSP 652包括密封剂层656，该密封剂层656具有以多行形成在密封剂层的正面上的开口或空隙658。互连结构654形成在密封剂654的正面上并且互连结构的一部分延伸到开口658中。导电层660被形成为互连结构654的一部分以及被共形地施加到绝缘或钝化层662，并且遵循绝缘或钝化层662的轮廓。导电层660延伸到开口658中，并且每个开口658具有形成在密封剂656的背面中的对应开口664。因此，开口664以多行形成并且安置成用于穿过FO-WLCSP 652的背面的垂直电互连的阵列。如前所述，通过将导电材料沉积在开口内和互连结构654上来完成穿过开口664的电互连。开口658位于3-D FO-WLCSP 652内，使得凸块或正面I/O互连668形成在每个开口658上并且与开口658垂直地对准。在互连654内的导电层和绝缘或钝化层的数目和配置随根据3-D FO-WLCSP 652的设计和功能的电路布线设计的复杂性变化。因此，3-D FO-WLCSP 652提供穿过形成在半导体管芯670的占位空间外部的垂直互连与互连I/O阵列的3-D电互连，而不使用在半导体管芯的占位空间内延伸的背面RDL。
图25b，类似于图25a，示出具有水平扩张互连结构676的3-D FO-WLCSP 674。3-D FO-WLCSP 674与FO-WLCSP 652的不同之处在于绝缘或钝化薄层678保留在形成在密封剂682的背面中的开口684和导电层686之间的开口680中。在一个实施例中，绝缘层678被显影不足，使得绝缘层678的薄层保留在开口680中。因此，3-D FO-WLCSP 674提供穿过形成在半导体管芯686的占位空间外部的垂直互连与互连I/O阵列的3-D电互连，而不使用在半导体管芯的占位空间内延伸的背面RDL。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行修改和改编。

Claims (12)

1.一种制造半导体器件的方法，包括：
提供临时载体；
以有源表面面向临时载体安装半导体管芯；以及
沉积具有在临时载体上的第一表面和与第一表面相对的第二表面的密封剂，第二表面在半导体管芯的背面上；
除去临时载体；
除去在半导体管芯的外围中的密封剂的一部分以在密封剂的第一表面中形成开口；
在半导体管芯的有源表面上形成互连结构并且延伸进入所述开口中；
形成从密封剂的第二表面到所述开口的通路；以及
在所述通路中形成电连接到互连结构的第一凸块。
2.根据权利要求1所述的方法，还包括在半导体管芯的有源表面上沉积临时平面化和保护层。
3.根据权利要求1所述的方法，其中形成互连结构包括：
在半导体管芯的有源表面上以及在密封剂的第一表面上沉积第一绝缘层；
在第一绝缘层上沉积导电层，所述导电层电连接到第一凸块；
在导电层上沉积第二绝缘层；以及
在第二绝缘层上形成第二凸块并且电连接到导电层。
4.根据权利要求1所述的方法，还包括形成多个通路，所述多个通路被组织为具有多行的阵列，其中所述多个通路从密封剂的第二表面延伸到密封剂的第一表面中的开口。
5.一种制造半导体器件的方法，包括：
提供具有有源表面的半导体管芯；
在半导体管芯的外围中沉积密封剂，所述密封剂具有第一表面和与第一表面相对的第二表面；
在半导体管芯的外围中沉积导电材料，所述导电材料从密封剂的第一表面延伸到第二表面；以及
在半导体管芯的有源表面上形成互连结构并且电连接到导电材料。
6.根据权利要求5所述的方法，其中沉积导电材料包括形成铜柱。
7.根据权利要求5所述的方法，其中密封剂的第二表面包括具有垂直偏移的台阶。
8.根据权利要求5所述的方法，还包括在半导体管芯的外围中沉积导电材料之前在互连结构上沉积背面研磨胶带。
9.一种半导体器件，包括：
具有有源表面的半导体管芯；
沉积在半导体管芯的外围中的密封剂，所述密封剂具有第一表面和与第一表面相对的第二表面；
形成在半导体管芯的有源表面上的互连结构；以及
导电通路，其从密封剂的第二表面延伸到互连结构。
10.根据权利要求9所述的半导体器件，其中从密封剂的第二表面延伸到互连结构的导电通路包括具有垂直或锥形轮廓的侧壁。
11.根据权利要求9所述的半导体器件，还包括沉积在半导体管芯的有源表面上的破裂停止层。
12.根据权利要求9所述的半导体器件，还包括安装在半导体管芯的外围中的背面对准单元。
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Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367139A (zh) * 2013-07-11 2013-10-23 华进半导体封装先导技术研发中心有限公司 一种tsv孔底部介质层刻蚀方法
CN103681468A (zh) * 2012-09-14 2014-03-26 新科金朋有限公司 在Fo-WLCSP中形成双面互连结构的半导体器件和方法
CN103681372A (zh) * 2013-12-26 2014-03-26 华进半导体封装先导技术研发中心有限公司 扇出型圆片级三维半导体芯片的封装方法
CN103681606A (zh) * 2012-08-29 2014-03-26 台湾积体电路制造股份有限公司 三维（3d）扇出封装机制
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CN104617034A (zh) * 2013-11-05 2015-05-13 中芯国际集成电路制造(上海)有限公司 半导体封装结构及其形成方法
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CN106409699A (zh) * 2015-07-30 2017-02-15 商升特公司 形成小z半导体封装的方法和半导体器件
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US9893017B2 (en) 2015-04-09 2018-02-13 STATS ChipPAC Pte. Ltd. Double-sided semiconductor package and dual-mold method of making same
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US10304817B2 (en) 2012-09-14 2019-05-28 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
CN110098147A (zh) * 2012-12-11 2019-08-06 新科金朋有限公司 半导体器件和形成具有垂直互连单元的低轮廓扇出式封装的方法
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CN111863772A (zh) * 2019-04-29 2020-10-30 矽磐微电子(重庆)有限公司 定位方法、封装组件及封装结构
US12009350B2 (en) 2018-09-07 2024-06-11 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

Families Citing this family (126)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9082806B2 (en) 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9293401B2 (en) * 2008-12-12 2016-03-22 Stats Chippac, Ltd. Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)
US8592992B2 (en) 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
JP5419226B2 (ja) 2010-07-29 2014-02-19 日東電工株式会社 フリップチップ型半導体裏面用フィルム及びその用途
US20120037935A1 (en) * 2010-08-13 2012-02-16 Wen-Kun Yang Substrate Structure of LED (light emitting diode) Packaging and Method of the same
FR2964786B1 (fr) * 2010-09-09 2013-03-15 Commissariat Energie Atomique Procédé de réalisation d'éléments a puce munis de rainures d'insertion de fils
US20130037929A1 (en) * 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
US9385009B2 (en) 2011-09-23 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP
US20130075892A1 (en) * 2011-09-27 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Three Dimensional Integrated Circuit Fabrication
US9059109B2 (en) * 2012-01-24 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package assembly and method of forming the same
KR101163574B1 (ko) * 2012-03-13 2012-07-06 주식회사 나노맥 무선인식 및 무선충전 겸용 전자파흡수체와 이를 포함하는 무선인식 및 무선충전 겸용 무선안테나, 그것의 제조방법
US20130249101A1 (en) * 2012-03-23 2013-09-26 Stats Chippac, Ltd. Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US10049964B2 (en) 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US9837303B2 (en) 2012-03-23 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
US8810024B2 (en) 2012-03-23 2014-08-19 Stats Chippac Ltd. Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
US9082780B2 (en) 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US9385006B2 (en) 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
US8809996B2 (en) * 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9030010B2 (en) 2012-09-20 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9385102B2 (en) 2012-09-28 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
KR101835566B1 (ko) * 2012-10-08 2018-03-07 삼성전기주식회사 패키지 구조물 및 그 제조 방법
US9331007B2 (en) 2012-10-16 2016-05-03 Stats Chippac, Ltd. Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor packages
US9391041B2 (en) * 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US20140127857A1 (en) * 2012-11-07 2014-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Carrier Wafers, Methods of Manufacture Thereof, and Packaging Methods
US9236366B2 (en) 2012-12-20 2016-01-12 Intel Corporation High density organic bridge device and method
US9704824B2 (en) 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9721862B2 (en) 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
TW201428901A (zh) * 2013-01-07 2014-07-16 矽品精密工業股份有限公司 半導體封裝件及其製法
US9378982B2 (en) * 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US9553070B2 (en) * 2013-04-30 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9711462B2 (en) 2013-05-08 2017-07-18 Infineon Technologies Ag Package arrangement including external block comprising semiconductor material and electrically conductive plastic material
US9252092B2 (en) 2013-07-24 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming through mold hole with alignment and dimension control
US9455211B2 (en) 2013-09-11 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with openings in buffer layer
US9425121B2 (en) 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
US9620580B2 (en) 2013-10-25 2017-04-11 Mediatek Inc. Semiconductor structure
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9472533B2 (en) 2013-11-20 2016-10-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wire bondable fan-out EWLB package
US9653442B2 (en) 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9589900B2 (en) 2014-02-27 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad for laser marking
US9343434B2 (en) 2014-02-27 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Laser marking in packages
TW201543641A (zh) * 2014-05-12 2015-11-16 Xintex Inc 晶片封裝體及其製造方法
US9666522B2 (en) 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US9978700B2 (en) * 2014-06-16 2018-05-22 STATS ChipPAC Pte. Ltd. Method for building up a fan-out RDL structure with fine pitch line-width and line-spacing
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US10490521B2 (en) * 2014-06-26 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced structure for info wafer warpage reduction
US20160035677A1 (en) * 2014-08-04 2016-02-04 Infineon Technologies Ag Method for forming a package arrangement and package arrangement
TWI584387B (zh) * 2014-08-15 2017-05-21 矽品精密工業股份有限公司 封裝結構之製法
US9842825B2 (en) * 2014-09-05 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Substrateless integrated circuit packages and methods of forming same
TWI549203B (zh) * 2014-11-26 2016-09-11 力成科技股份有限公司 防止中介導體橋接之半導體封裝件立體堆疊方法
US9659863B2 (en) * 2014-12-01 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, multi-die packages, and methods of manufacture thereof
US9812337B2 (en) 2014-12-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package pad and methods of forming
US9859200B2 (en) * 2014-12-29 2018-01-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof
US20160218021A1 (en) * 2015-01-27 2016-07-28 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US9786623B2 (en) 2015-03-17 2017-10-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming PoP semiconductor device with RDL over top package
US9502397B1 (en) * 2015-04-29 2016-11-22 Deca Technologies, Inc. 3D interconnect component for fully molded packages
US20170098589A1 (en) * 2015-10-05 2017-04-06 Mediatek Inc. Fan-out wafer level package structure
KR101674322B1 (ko) * 2015-11-18 2016-11-08 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR20170067426A (ko) * 2015-12-08 2017-06-16 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지
DE112016006322T5 (de) * 2016-01-28 2018-10-18 Intel IP Corporation Integrierte Schaltungspackungen
US10211071B2 (en) * 2016-01-29 2019-02-19 Nxp B.V. IC packaging method and a packaged IC device
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof
CN109075151B (zh) 2016-04-26 2023-06-27 亚德诺半导体国际无限责任公司 用于组件封装电路的机械配合、和电及热传导的引线框架
US20170338128A1 (en) * 2016-05-17 2017-11-23 Powertech Technology Inc. Manufacturing method of package structure
US10600748B2 (en) * 2016-06-20 2020-03-24 Samsung Electronics Co., Ltd. Fan-out semiconductor package
TWI610409B (zh) * 2016-08-30 2018-01-01 南茂科技股份有限公司 半導體封裝及其製造方法
US10141276B2 (en) * 2016-09-09 2018-11-27 Powertech Technology Inc. Semiconductor package structure and manufacturing method thereof
KR101952865B1 (ko) * 2016-10-10 2019-02-27 삼성전기주식회사 팬-아웃 반도체 패키지 및 감광성 수지 조성물
KR101963278B1 (ko) * 2016-10-28 2019-07-31 삼성전자주식회사 팬-아웃 반도체 패키지 및 그 제조방법
TWI622142B (zh) * 2016-11-07 2018-04-21 財團法人工業技術研究院 晶片封裝體以及晶片封裝方法
JP2018098302A (ja) * 2016-12-09 2018-06-21 株式会社デンソー 電子装置
CN108288616B (zh) 2016-12-14 2023-04-07 成真股份有限公司 芯片封装
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
KR102373440B1 (ko) * 2017-03-17 2022-03-14 삼성디스플레이 주식회사 디스플레이 패널 및 이를 구비하는 디스플레이 장치
US10510709B2 (en) * 2017-04-20 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor package and manufacturing method thereof
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10192843B1 (en) * 2017-07-26 2019-01-29 Micron Technology, Inc. Methods of making semiconductor device modules with increased yield
US10957679B2 (en) * 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US11024569B2 (en) * 2017-08-09 2021-06-01 Advanced Semiconducor Engineering, Inc. Semiconductor package device and method of manufacturing the same
KR102440119B1 (ko) 2017-08-10 2022-09-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
US10643863B2 (en) * 2017-08-24 2020-05-05 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
KR101892869B1 (ko) * 2017-10-20 2018-08-28 삼성전기주식회사 팬-아웃 반도체 패키지
US10636775B2 (en) * 2017-10-27 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10672737B2 (en) * 2017-11-05 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional integrated circuit structure and method of manufacturing the same
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US20190164948A1 (en) * 2017-11-27 2019-05-30 Powertech Technology Inc. Package structure and manufacturing method thereof
US20190181116A1 (en) * 2017-12-11 2019-06-13 Semiconductor Components Industries, Llc Fan-out structure for semiconductor packages and related methods
KR20190082604A (ko) * 2018-01-02 2019-07-10 삼성전자주식회사 반도체 패키지
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US20190385962A1 (en) * 2018-06-15 2019-12-19 Texas Instruments Incorporated Semiconductor structure and method for wafer scale chip package
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10672703B2 (en) 2018-09-26 2020-06-02 Nxp Usa, Inc. Transistor with shield structure, packaged device, and method of fabrication
US20200098684A1 (en) * 2018-09-26 2020-03-26 Nxp Usa, Inc. Transistor, packaged device, and method of fabrication
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
KR102530319B1 (ko) * 2018-12-07 2023-05-09 삼성전자주식회사 전도성 필라를 갖는 반도체 패키지 및 그 제조 방법
KR102600963B1 (ko) 2019-01-07 2023-11-13 삼성전자주식회사 디스플레이 장치
TWI694555B (zh) * 2019-02-28 2020-05-21 鴻海精密工業股份有限公司 晶片封裝結構及其製作方法
TWI744649B (zh) * 2019-06-18 2021-11-01 鈺橋半導體股份有限公司 具有跨過界面之橋接件的線路板
US11322381B2 (en) 2019-06-28 2022-05-03 Applied Materials, Inc. Method for substrate registration and anchoring in inkjet printing
US11329003B2 (en) 2019-06-28 2022-05-10 Applied Materials, Inc. Anchoring dies using 3D printing to form reconstructed wafer
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11164817B2 (en) 2019-11-01 2021-11-02 International Business Machines Corporation Multi-chip package structures with discrete redistribution layers
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
KR20220000294A (ko) 2020-06-25 2022-01-03 삼성전자주식회사 반도체 패키지
CN111883437B (zh) * 2020-07-03 2023-04-25 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
US11908831B2 (en) 2020-10-21 2024-02-20 Stmicroelectronics Pte Ltd Method for manufacturing a wafer level chip scale package (WLCSP)
US11854924B2 (en) * 2020-12-04 2023-12-26 Mediatek Inc. Semiconductor package with improved reliability
US11978723B2 (en) * 2021-03-31 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical interconnect structures in three-dimensional integrated circuits
TWI823299B (zh) * 2022-03-18 2023-11-21 邱志威 電晶體下具有電源連接結構之半導體結構的製造方法及電晶體下具有電源連接結構之半導體結構
US20230108000A1 (en) * 2021-09-24 2023-04-06 Intel Corporation Topological crack stop (tcs) passivation layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030116861A1 (en) * 2001-12-26 2003-06-26 Jeung Boon Suan Multi-substrate microelectronic packages and methods for manufacture
CN101075580A (zh) * 2007-06-01 2007-11-21 日月光半导体制造股份有限公司 切割晶圆的方法
US20080111233A1 (en) * 2006-11-10 2008-05-15 Pendse Rajendra D Semiconductor package with embedded die
US20090212420A1 (en) * 2008-02-22 2009-08-27 Harry Hedler integrated circuit device and method for fabricating same

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5872338A (en) 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6833613B1 (en) 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts
US6002169A (en) 1998-06-15 1999-12-14 Lsi Logic Corporation Thermally enhanced tape ball grid array package
US6586323B1 (en) * 2000-09-18 2003-07-01 Taiwan Semiconductor Manufacturing Company Method for dual-layer polyimide processing on bumping technology
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
TW495943B (en) 2001-04-18 2002-07-21 Siliconware Precision Industries Co Ltd Semiconductor package article with heat sink structure and its manufacture method
SG111919A1 (en) 2001-08-29 2005-06-29 Micron Technology Inc Packaged microelectronic devices and methods of forming same
TW200302685A (en) 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US7548430B1 (en) 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US6987031B2 (en) 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
DE102004022884B4 (de) 2004-05-06 2007-07-19 Infineon Technologies Ag Halbleiterbauteil mit einem Umverdrahtungssubstrat und Verfahren zur Herstellung desselben
DE102005026098B3 (de) 2005-06-01 2007-01-04 Infineon Technologies Ag Nutzen und Halbleiterbauteil aus einer Verbundplatte mit Halbleiterchips und Kunststoffgehäusemasse sowie Verfahren zur Herstellung derselben
FR2893764B1 (fr) 2005-11-21 2008-06-13 St Microelectronics Sa Boitier semi-conducteur empilable et procede pour sa fabrication
US8072059B2 (en) 2006-04-19 2011-12-06 Stats Chippac, Ltd. Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die
DE102006019244B4 (de) 2006-04-21 2008-07-03 Infineon Technologies Ag Nutzen und Halbleiterbauteil aus einer Verbundplatte mit Halbleiterchips und Kunststoffgehäusemasse sowie Verfahren zur Herstellung desselben
JP2008166373A (ja) 2006-12-27 2008-07-17 Nec Electronics Corp 半導体装置およびその製造方法
KR100809718B1 (ko) 2007-01-15 2008-03-06 삼성전자주식회사 이종 칩들을 갖는 적층형 반도체 칩 패키지 및 그 제조방법
US8409920B2 (en) 2007-04-23 2013-04-02 Stats Chippac Ltd. Integrated circuit package system for package stacking and method of manufacture therefor
US20080284045A1 (en) 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package
TWI332790B (en) 2007-06-13 2010-11-01 Ind Tech Res Inst Image sensor module with a three-dimensional dies-stacking structure
US7944034B2 (en) 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
US8384199B2 (en) 2007-06-25 2013-02-26 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
KR101329355B1 (ko) 2007-08-31 2013-11-20 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US7834462B2 (en) 2007-09-17 2010-11-16 Qimonda Ag Electric device, stack of electric devices, and method of manufacturing a stack of electric devices
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8101460B2 (en) 2008-06-04 2012-01-24 Stats Chippac, Ltd. Semiconductor device and method of shielding semiconductor die from inter-device interference
US8039303B2 (en) 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
KR20100009941A (ko) 2008-07-21 2010-01-29 삼성전자주식회사 단차를 갖는 몰딩수지에 도전성 비아를 포함하는 반도체패키지, 그 형성방법 및 이를 이용한 적층 반도체 패키지
CA2676881C (en) 2008-09-30 2017-04-25 Wyeth Peripheral opioid receptor antagonists and uses thereof
US7952176B2 (en) 2008-12-09 2011-05-31 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
US9082806B2 (en) 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
TWI499024B (zh) 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
US9299648B2 (en) 2009-03-04 2016-03-29 Stats Chippac Ltd. Integrated circuit packaging system with patterned substrate and method of manufacture thereof
TWI570820B (zh) 2009-06-09 2017-02-11 史達晶片有限公司 半導體元件和在晶粒及互連結構之間形成應力減輕層之方法
US7993976B2 (en) 2009-06-12 2011-08-09 Stats Chippac, Ltd. Semiconductor device and method of forming conductive vias with trench in saw street
US8367470B2 (en) 2009-08-07 2013-02-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die
US8198131B2 (en) 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
US8241952B2 (en) 2010-02-25 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of forming IPD in fan-out level chip scale package
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US9082780B2 (en) 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US9331007B2 (en) 2012-10-16 2016-05-03 Stats Chippac, Ltd. Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor packages

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030116861A1 (en) * 2001-12-26 2003-06-26 Jeung Boon Suan Multi-substrate microelectronic packages and methods for manufacture
US20080111233A1 (en) * 2006-11-10 2008-05-15 Pendse Rajendra D Semiconductor package with embedded die
CN101075580A (zh) * 2007-06-01 2007-11-21 日月光半导体制造股份有限公司 切割晶圆的方法
US20090212420A1 (en) * 2008-02-22 2009-08-27 Harry Hedler integrated circuit device and method for fabricating same

Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681606B (zh) * 2012-08-29 2018-06-08 台湾积体电路制造股份有限公司 三维(3d)扇出封装机制
CN103681606A (zh) * 2012-08-29 2014-03-26 台湾积体电路制造股份有限公司 三维（3d）扇出封装机制
CN103681386A (zh) * 2012-08-31 2014-03-26 南茂科技股份有限公司 半导体结构与其制造方法
US10304817B2 (en) 2012-09-14 2019-05-28 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
CN103681468A (zh) * 2012-09-14 2014-03-26 新科金朋有限公司 在Fo-WLCSP中形成双面互连结构的半导体器件和方法
US10163737B2 (en) 2012-09-14 2018-12-25 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages
US10192796B2 (en) 2012-09-14 2019-01-29 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP
US11569136B2 (en) 2012-09-14 2023-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP
CN110098147A (zh) * 2012-12-11 2019-08-06 新科金朋有限公司 半导体器件和形成具有垂直互连单元的低轮廓扇出式封装的方法
CN110098147B (zh) * 2012-12-11 2023-09-19 星科金朋私人有限公司 半导体器件和制作半导体器件的方法
CN104167371B (zh) * 2013-05-17 2017-06-09 矽品精密工业股份有限公司 半导体封装件的制法
CN103367139A (zh) * 2013-07-11 2013-10-23 华进半导体封装先导技术研发中心有限公司 一种tsv孔底部介质层刻蚀方法
CN104617034B (zh) * 2013-11-05 2018-05-01 中芯国际集成电路制造(上海)有限公司 半导体封装结构及其形成方法
CN104617034A (zh) * 2013-11-05 2015-05-13 中芯国际集成电路制造(上海)有限公司 半导体封装结构及其形成方法
CN105765711A (zh) * 2013-12-23 2016-07-13 英特尔公司 封装体叠层架构以及制造方法
CN103681372A (zh) * 2013-12-26 2014-03-26 华进半导体封装先导技术研发中心有限公司 扇出型圆片级三维半导体芯片的封装方法
CN103681372B (zh) * 2013-12-26 2016-07-06 华进半导体封装先导技术研发中心有限公司 扇出型圆片级三维半导体芯片的封装方法
US9893017B2 (en) 2015-04-09 2018-02-13 STATS ChipPAC Pte. Ltd. Double-sided semiconductor package and dual-mold method of making same
US10115672B2 (en) 2015-04-09 2018-10-30 STATS ChipPAC Pte. Ltd. Double-sided semiconductor package and dual-mold method of making same
CN106409699A (zh) * 2015-07-30 2017-02-15 商升特公司 形成小z半导体封装的方法和半导体器件
CN108604571A (zh) * 2015-11-20 2018-09-28 德卡科技公司 全模制周边堆叠封装设备
CN108604571B (zh) * 2015-11-20 2023-02-17 美国德卡科技公司 全模制周边堆叠封装设备
CN106952879B (zh) * 2016-01-06 2019-07-19 爱思开海力士有限公司 包括贯通式模具连接器的半导体封装件及其制造方法
CN106952879A (zh) * 2016-01-06 2017-07-14 爱思开海力士有限公司 包括贯通式模具连接器的半导体封装件及其制造方法
CN107146780A (zh) * 2016-03-01 2017-09-08 日月光半导体制造股份有限公司 半导体芯片及半导体装置
CN107146780B (zh) * 2016-03-01 2019-10-18 日月光半导体制造股份有限公司 半导体芯片及半导体装置
CN109075133B (zh) * 2016-04-25 2022-08-09 京瓷株式会社 电子部件搭载用基板、电子装置以及电子模块
CN109075133A (zh) * 2016-04-25 2018-12-21 京瓷株式会社 电子部件搭载用基板、电子装置以及电子模块
CN107452686A (zh) * 2016-05-31 2017-12-08 爱思开海力士有限公司 包括升高焊盘上的贯穿模球的半导体封装及其制造方法
CN107887324B (zh) * 2016-09-30 2019-09-13 上海微电子装备（集团）股份有限公司 一种半导体重布线方法
US10727112B2 (en) 2016-09-30 2020-07-28 Shanghai Micro Electronics Equipment (Group) Co., Ltd. Rewiring method for semiconductor
CN107887324A (zh) * 2016-09-30 2018-04-06 上海微电子装备（集团）股份有限公司 一种半导体重布线方法
CN106653699B (zh) * 2016-10-26 2019-06-11 江苏吉祥星智能科技有限公司 一种ic裸芯片组的互连技系统集成方法
CN106653699A (zh) * 2016-10-26 2017-05-10 安徽扬远信息科技有限公司 一种ic裸芯片组的互连技系统集成方法
CN110890320A (zh) * 2018-09-07 2020-03-17 三星电子株式会社 半导体封装件及其制造方法
US12009350B2 (en) 2018-09-07 2024-06-11 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
CN111863772A (zh) * 2019-04-29 2020-10-30 矽磐微电子(重庆)有限公司 定位方法、封装组件及封装结构

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