TWI538131B - 形成在半導體晶粒的接觸墊上的晶種層上方的互連結構而在互連結構下方無底切的晶種層之方法和半導體裝置 - Google Patents

形成在半導體晶粒的接觸墊上的晶種層上方的互連結構而在互連結構下方無底切的晶種層之方法和半導體裝置 Download PDF

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TWI538131B
TWI538131B TW101116628A TW101116628A TWI538131B TW I538131 B TWI538131 B TW I538131B TW 101116628 A TW101116628 A TW 101116628A TW 101116628 A TW101116628 A TW 101116628A TW I538131 B TWI538131 B TW I538131B
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conductive
insulating layer
layer
hole
semiconductor
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TW101116628A
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TW201306210A (zh
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催源璟
潘迪 琪帆 瑪莉姆蘇
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史達晶片有限公司
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Description

形成在半導體晶粒的接觸墊上的晶種層上方的互連結構而在互連結構下方無底切的晶種層之方法和半導體裝置
本發明一般有關於一種半導體裝置，以及更尤其有關於一種形成在半導體晶粒的接觸墊上的晶種層上方的互連結構而在互連結構下方無底切的晶種層之方法和半導體裝置。
在現代電子產品中通常可以發現半導體裝置。半導體裝置之電性組件之數目與密度可以改變。離散半導體裝置通常包括一種形式電性組件，例如：發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器以及功率金屬氧化物半導體場效應電晶體(MOSFET)。積體半導體裝置典型地包括數百個至數百萬個電性組件。積體半導體裝置之例包括：微控制器、微處理器、電荷耦合裝置(CCD)、太陽電池以及數位微鏡裝置(DMD)。
半導體裝置可以實施廣大範圍功能，例如：信號處理、高速計算、發射與接收電磁信號、控制電子裝置、將陽光轉換成電力以及產生用電視顯示之視覺投影。可以在娛樂、通信、電力轉換、網路、電腦以及消費產品之領域中發現半導體裝置。亦可以在軍事用途、航空、汽車、工業控制器以及辦公室設備中發現半導體裝置。
半導體裝置使用半導體材料之電氣性質。半導體材料之原子結構允許藉由施加電場或基極電流、或經由掺雜過 程，而操控其導電性。掺雜會將雜質導入於半導體材料中，以操縱與控制半導體裝置之導電性。
半導體裝置包含主動與被動電性結構。此主動結構包括雙載子與場效應電晶體，以控制電流之流動。藉由改變掺雜位準與所施加電場或基極電流，電晶體可以增強或限制電流之流動。被動結構包括電阻器、電容器以及電感器，其在實施各種電性功能所須之電壓與電流之間產生關係。可以將被動與主動結構電性連接以形成電路，其使得半導體裝置可以實施高速計算與其他有用功能。
半導體裝置通常使用兩個複雜製造過程製成，即前端製造過程與後端製造過程，其各可能涉及數百可能步驟。前端製造過程涉及在半導體晶圓表面上形成複數個晶粒。各半導體晶粒典型地相同，且包含藉由將主動組件與被動組件電性連接所形成之電路。後端製造過程涉及將所製成晶圓單一化為個別半導體晶粒，且將晶粒封裝以提供結構支持與環境隔離。在此使用“半導體晶粒”此名詞以指其單數與複數形式，且因此可以指單個半導體裝置或多個半導體裝置。
製造半導體之目標為產生較小半導體裝置。較小裝置典型地消耗較少電力、具有較佳性能表現、且更有效地製造。此外，較小半導體裝置具有較小占用面積，此對於較小終端產品為令人所欲。較小半導體晶粒尺寸可以藉由以下方式達成：改善前端製造過程，以產生具有較小尺寸較高密度之主動與被動組件之半導體晶粒。後端製造過程可 以藉由改善電性互連與封裝材料，以產生具有較小占用面積之半導體裝置封裝。
半導體晶粒典型地包括一互連結構，用於將晶粒安裝至基板。例如，此互連結構可以為突塊或導電柱，其形成於半導體晶粒上絕緣層中之孔中接觸墊上。藉由將突塊材料回流，在半導體晶粒與基板之間提供機械與電性互連，將突塊或導電柱接合至基板。導電柱所提供之優點為：較小互連間距、較高互連與路線密度。
通常在半導體晶粒之導電柱與接觸墊之間須要晶種層，用於良好黏著。在形成導電柱之前，在半導體晶粒之絕緣層與接觸墊之上沉積晶種層，且然後經常藉由濕性蝕刻過程，將其從導電柱之占用面積外之區域去除。此濕性蝕刻被知為將導電柱下晶種層之一部份去除，即此濕性蝕刻將導電柱下之晶種層底切。然而，將導電柱下之晶種層底切，會使得半導體晶粒之導電柱與接觸墊之間黏著變弱，導致接合破裂與製造可靠度問題。由於無法準確地控制濕性蝕刻速率，此較小互連間距會增加晶種層底切之發生。此外，形成此導電柱，一直至在半導體晶粒上絕緣層之邊緣。在靠近半導體晶粒上絕緣層之導電柱基底周圍存在高電流密度，此會增加互連阻抗。
因此，存在一種須要在半導體晶粒接觸墊上之晶種層上形成互連結構，例如導電柱或墊，而未底切此互連結構 下之晶種層。因此，在一實施例中，本發明為一種製造半導體裝置之方法，包括以下步驟：提供一半導體晶圓；在此晶圓上形成第一導電層；在半導體晶圓上形成第一絕緣層，其具有設置在第一導電層上第一絕緣層中之第一孔；在第一絕緣層上形成第二導電層，且進入於第一導電層上之第一孔中；在第一與第二導電層上形成一導電柱；在第一與第二導電層上形成導電柱；且將在第一絕緣層中第一孔外第一絕緣層上第二導電層之一部份去除，而留下導電柱下之第二導電層。此導電柱之寬度小於第一絕緣層中第一孔之寬度。
在另一實施例中，本發明為一種製造半導體裝置之方法，其包括以下步驟：提供一半導體晶圓；在半導體晶圓上形成一第一導電層；在半導體晶圓上形成一第一絕緣層，其具有設置在第一導電層上第一絕緣層中之第一孔；在第一絕緣層上形成一第二導電層，且進入於第一導電層上之第一孔中；在第一與第二導電層上形成一互連結構；以及將在第一絕緣層中之第一孔外第一絕緣層上第二導電層之一部份去除。此互連結構之寬度小於第一絕緣層中第一孔之寬度。
在另一實施例中，本發明為一種製造半導體裝置之方法，其包括以下步驟：提供一半導體晶粒；在半導體晶粒上形成一第一絕緣層，其具有在第一絕緣層中之第一孔；在第一絕緣層上形成一第一導電層，且進入於第一絕緣層中之第一孔中；以及在第一導電層上形成一互連結構。此 互連結構之寬度小於第一絕緣層中第一孔之寬度。
在另一實施例中，本發明為一種半導體裝置，其包括：一半導體晶粒；以及形成於此一半導體晶粒上之第一導電層。第一絕緣層形成於半導體晶粒上，其具有設置在第一導電層上第一絕緣層中之一第一孔。第二導電層形成於第一絕緣層上，且進入於第一導電層上之第一孔中。互連結構形成於第一與第二導電層上。此互連結構之寬度小於第一絕緣層中第一孔之寬度。
本發明可以參考所附圖示在以下一或更多個實施例中說明，在其中相同數字代表相同或類似元件。雖然本發明是以最佳模式說明，以達成本發明之目的，但熟習此技術人士瞭解，其用意為包括由所附申請專利範圍與其等同物所界定本發明精神與範圍中之替代、修正、以及等同物，而其由以下揭示內容與圖式所支持。
半導體裝置通常使用兩個複雜製造過程製成，即前端製造過程與後端製造過程。前端製造過程涉及在半導體晶圓表面上形成複數個晶粒。在晶圓上各晶粒包含主動與被動電性組件，其各電性連接以形成功能性電路。主動電性組件例如電晶體與二極體，具有能力以控制電流之流動。被動電性組件例如電容器、電感器、電阻器以及變壓器，產生此實施電路功能所須之電壓與電流間之關係。
被動與主動組件藉由一系列過程步驟，形成於半導體 晶圓之表面上，此過程步驟包括：掺雜、沉積、微影術、蝕刻以及平坦化。掺雜藉由例如離子植入或熱擴散之技術，將雜質導入於半導體材料中。此掺雜過程修正主動裝置中半導體材料之導電性，且將半導體材料轉換成絕緣體、導電體，或動態地改變此半導體材料之導電性，以響應於電場或基極電流。電晶體包括改變形式之區域與掺雜程度，其如同所須地配置，在當施加電場或基極電流時，可以使得電晶體增強或限制電流之流動。
此等主動與被動組件由具有不同電氣性質之材料層形成。此等層藉由各種沉積技術形成，此沉積技術部份是由所沉積材料之形式所決定。例如，薄膜沉積可以涉及化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解電鍍以及無電極電鍍過程。通常將各層圖案化，以形成主動組件、被動組件之部份或組件間之電性連接。
使用微影術將此等層圖案化，其涉及將光敏感材料例如光阻沉積在被圖案化之層上。使用光線將圖案由光罩移轉至光阻。在一實施例中，使用溶劑將受到光線照射之光阻圖案之部份去除，以曝露被圖案化下層之部份。
在另一實施例中，使用溶劑將未受到光線照射之光阻圖案之部份(負光阻)去除，以曝露被圖案化下層之部份。然後將光阻之剩餘部份去除，而留下被圖案化之層。以替代方式，可以藉由將材料直接沉積區域或洞孔中，將一些形式材料圖案化，此等區域或洞孔藉由使用像是無電極電鍍或電解電鍍之技術之先前沉積/蝕刻過程形成。
在現有圖案上沉積薄膜材料可以將下面圖案放大，且產生一非均勻平坦表面。須要一均勻平坦表面以產生更小且更密集封裝之主動與被動組件。可以使用平坦化，將材料從晶圓表面去除，且產生均勻平坦表面。平坦化涉及以拋光墊將晶圓表面拋光。在拋光期間，將研磨材料與腐蝕性化學物加至晶圓表面。此研磨之機械動作與化學物之腐蝕動作之組合可以去除任何不規則形狀，以導致均勻平坦表面。
後端製造過程是指將所完成晶圓切割或單一化成個別晶粒，以及然後將此晶粒封裝，用於結構支持與環境隔離。為了將半導體晶粒單一化，將晶圓沿著此稱為鋸道或鋸線之晶圓之非功能性區域劃線或切開。使用雷射切割工具或鋸刀將晶圓單一化。在單一化之後，將個別半導體晶粒安裝至一封裝基板，其包括接腳或接觸墊，用於與其他系統組件之互連。將接觸墊形成於半導體晶粒上，然後將其連接至封裝中之接觸墊。此電性連接可以焊料突塊、突塊、導電漿或接線製成。可以將包封劑或其他模製材料沉積在封裝上，以提供實體支持與電性隔離。然後將所完成封裝插入於電性系統中，且將半導體裝置之功能提供給其他系統組件。
圖1說明電子裝置50，其所設晶片載體基板或印刷電路板(PCB)52具有複數個安裝至其表面上之半導體封裝。取決其應用，此電子裝置50可以具有一種形式半導體封裝或多種形式半導體封裝。圖1顯示用於說明目的之不同形式 半導體封裝。
電子裝置50可以為獨立式(stand-alone)系統，其使用半導體封裝，以實施一或更多個電性功能。以替代方式，電子裝置50可以為一較大系統之次組件。例如，此電子裝置50可以為蜂巢電話、個人數位助理(PDA)、數位視訊攝影機(DVC)或其他電子通訊裝置之一部份。以替代方式，電子裝置50可以為插入於電腦中之圖形卡、網路介面卡或其他信號處理卡。此半導體封裝可以包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散裝置或其他半導體晶粒或電性組件。微形化與減輕重量對於此等產品為重要，以便為市場所接受。必須將半導體裝置間距離縮小，以達成較高密度。
在圖1中，PCB 52提供一種一般性基板，用於此安裝於PCB上半導體封裝之結構支持與電性互連。使用蒸鍍、電解電鍍、無電極電鍍、絲網印刷或其他適當金屬沉積過程，在PCB 52之表面上或層中形成信號傳導跡線54。信號傳導跡線54提供各半導體封裝、安裝組件以及其他外部系統組件間之電性連通。跡線54亦提供至各此等半導體封裝之電力與接地連接。
在一些實施例中，半導體裝置具有兩個封裝位準。此第一位準封裝為一種技術，用於將半導體晶粒機械地與電性地裝附於一中間載體。第二位準封裝涉及將此中間載體機械地與電性地裝附至PCB。在其他實施例中，半導體裝置可以僅具有第一位準封裝，將晶粒機械地與電性地直接 安裝至PCB。
為了說明目的，顯示在PCB 52上數種形式第一位準封裝，其包括接線封裝56與覆晶58。此外，顯示在PCB 52上安裝數種形式第二位準封裝，其包括：球格柵陣列(BGA)60、突起晶片載體(BCC)62、雙線封裝(DIP)64、閘格柵陣列(LGA)66、多晶片模組(MCM)68、四扁平無引線封裝(QFN)70以及四扁平封裝72。取決於系統須求，可以將半導體封裝之任何組合、其以第一與第二位準封裝形式之任何組合而組態，與其他電子組件連接至PCB 52。在一些實施例中，此電子裝置50包括單一裝附半導體封裝，而在其他實施例中須要多個互連封裝。藉由將一或更多個半導體封裝組合於單一基板上，製造廠商可以將預製組件裝附於電子裝置與系統中。因為半導體封裝包括精密複雜功能，可以使用更便宜組件與合理化製造過程以製造電子裝置。此所製造之裝置較不容易故障，且其製造較便宜，以造成對消費者較低成本。
圖2a-2c顯示典範半導體封裝。圖2a說明安裝於PCB 52上之DIP 64之進一步細節。半導體晶粒74具有一主動區域，其包含：類比或數位電路，其執行作為主動裝置；被動裝置；導電層；以及形成於晶粒中之介電層，且根據晶粒之電性設計而電性互連。例如，此電路可以包括：一或更多個電晶體、二極體、電感器、電容器、電阻器、以及形成於半導體晶粒74中之主動區域中之其他電路元件。接觸墊76為一或更多層之導電材料，例如：鋁(Al)、銅(Cu)、 錫(Sn)、鎳(Ni)、金(Au)、或銀(Ag)，且電性連接至形成於半導體晶粒74中之電路元件。在DIP 64之組裝期間，使用金-矽共晶層或黏著材料例如熱樹脂或環氧樹脂，將半導體晶粒74安裝至中間載體78。此封裝體包括絕緣封裝材料，例如聚合物或陶瓷。導線80與接線82提供半導體晶粒74與PCB 52間之電性互連。將包封劑84沉積在封裝上用於環境保護，以防止濕氣與粒子進入此封裝且污染半導體晶粒74或接線82。
圖2b說明安裝於PCB 52上BCC 62之進一步細節。使用一種填料或環氧樹脂黏著材料92，將半導體晶粒88安裝至載體90。接線94提供在接觸墊96與98間第一位準封裝互連。將模製複合物或包封劑100沉積在半導體晶粒88與接線94上，以提供用於此裝置之實體支持與電性隔離。使用適當之金屬沉積過程，例如電解電鍍或無電極電鍍，將接觸墊102形成於PCB 52之表面上，以防止氧化。將接觸墊102電性地連接至在PCB 52中之一或更多個信號傳導跡線54。將突塊104形成於BCC 62之接觸墊98與PCB 52之接觸墊102之間。
在圖2c中，將半導體晶粒58以覆晶型式第一位準封裝，面向下安裝至中間載體106。半導體晶粒58之主動區域108包括：類比或數位電路，其執行作為主動裝置；被動裝置；導電層；以及根據晶粒電性設計所形成之介電層。例如，此電路可以包括：一或更多個電晶體、二極體、電感器、電容器、電阻器以及在主動區域108中之其他電路 元件。將半導體晶粒58經由突塊110電性地與機械地連接至載體106。
以BGA形式第二位準封裝使用突塊112，將BGA 60電性地與機械地連接至PCB 52。將半導體晶粒58經由突塊110、信號線114以及突塊112，電性地連接至PCB 52中之信號傳導跡線54。將模製複合物或包封劑116沉積在半導體晶粒58與載體106上，以提供用於此裝置之實體支持與電性隔離。此覆晶半導體裝置提供從在半導體晶粒58上主動裝置、至PCB 52上導軌之短電性傳導路徑，以便縮短信號傳播距離、減少電容以及改善整體電路性能表現。在另一實施例中，使用覆晶形式第一位準封裝，無須中間載體106，將半導體晶粒58機械地與電性地直接連接至PCB 52。
圖3a-3m相對於圖1與2a-2c說明一種過程，在半導體晶粒之接觸墊上之晶種層上形成互連結構，並無法底切此互連結構下之晶種層。圖3a顯示具有基礎基板材料122之半導體晶圓120，此等材料例如為矽、鍺、砷化鎵、磷化錪或碳化矽，用於結構支持。如同以上說明，此等複數個形成於晶圓120上之半導體晶粒或組件124，藉由非主動、晶粒間晶圓區域、或鋸道126而分開。鋸道126提供切割區域，將半導體晶圓120單一化成個別半導體晶粒124。
圖3b顯示半導體晶圓120一部份之橫截面圖。各半導體晶粒124具有一背表面128與主動表面130，其包含類比或數位電路，其執行作為主動裝置、被動裝置、導電層以及在晶粒中所形成之介電層，其根據晶粒電性設計與功 能，電性地互連。例如，此電路可以包括：一或更多個電晶體、二極體、以及形成於主動表面130中之其他電路元件，以執行類比電路或數位電路，例如數位信號處理器(DSP)、特殊應用積體電路(ASIC)、記憶體、或其他信號處理電路。半導體晶粒124亦包含積體被動裝置(IPD)，例如：電感器、電容器以及電阻器，用於射頻(RF)信號處理。在一實施例中，半導體晶粒124為覆晶式裝置。
可以使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、濺鍍塗佈、燒結、或熱氧化，在主動表面130上形成絕緣層或介電層132。
絕緣層132包含一或更多層之二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、苯並環丁烯(BCB)、聚亞醯胺(FI)、聚苯噁唑(PBO)或其他適當介電材料。
在圖3c中，使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、電解電鍍、無電極電鍍過程、或其他適當金屬沉積過程，在絕緣層132上形成導電層134。導電層134可以為為一或更多層鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他適當導電材料。導電層134操作為接觸墊，其例如經由通過絕緣層132所形成之導電通孔電性連接至在主動表面130上之電路。
在圖3d中，使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、濺鍍塗佈、燒結或熱氧化，在絕緣層132與導電層134上形成絕緣層或鈍化層136。絕緣層 136包含一或更多層SiO2、Si3N4、SiON、Ta2O5、Al2O3或其他具有類似絕緣與結構性質之材料。藉由蝕刻過程，經由光阻層(未圖示)，將絕緣層136之一部份去除以形成孔137，其設置在導電層134之上且將其曝露。在一實施例中，絕緣層136中孔137之寬度，與相對應所曝露導電層134之寬度為50μm。
在圖3e中，使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、電解電鍍、無電極電鍍過程、或其他適當金屬沉積過程，在導電層134與絕緣層136上均勻一致地塗佈導電層138。導電層138可以為為一或更多層鋁(Al)、銅(Cu)、鈦(Ti)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或其他適當導電材料。導電層138具有與導電層134以及絕緣層136相同輪廓。在一實施例中，導電層138為晶種層，其包含多層Ti/Cu或Ti/Au，且電性連接至導電層134。
在圖3f中，在絕緣層136與導電層138上形成厚的絕緣層140。在一實施例中，絕緣層140為一具有PET支持薄膜之乾薄膜材料。絕緣層140之厚度為120μm。藉由將受光照射DFR材料浸入顯影液，以選擇性地溶解此DFR材料未收光照射之部份，將絕緣層140之一部份去除，而在導電層134與138上之絕緣層140中產生圖案化孔142，而留下光阻材料之受光照射部份原封不動。在一實施例中，絕緣層140中圖案化孔142之寬度為40μm，其小於孔137之寬度。因此，絕緣層140部份地外伸於孔137上。
在另一實施例中，絕緣層140可以包含一或更多層之 二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二氮(Ta2O5)、氧化鋁(Al2O3)、焊料電阻、或其他光敏材料，其藉由物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、濺鍍塗佈、燒結、或熱氧化所形成。藉由以下方式，以去除絕緣層140之一部份：將絕緣層140圖案化，將其曝露於紫外線(UV)光，且顯影以形成孔142，以及將導電層134上導電層138之一部份曝露此於孔137中。再度說明，此在絕緣層140中圖案化孔142之寬度小於孔137之寬度，以致於絕緣層140部份地外伸於孔137上。
以替代方式，在須要精細互連尺寸之應用中，如同於圖3g中所顯示，可以使用雷射144藉由雷射直接剝離(LDA)，以形成圖案化孔142，將絕緣層140之一些部份去除，且將在導電層134上導電層138之一部份曝露於圖案化孔137中。
在圖3h中，使用金屬沉積過程，例如：物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍、電解電鍍、無電極電鍍，將導電材料沉積在絕緣層140中圖案化孔142中導電層138上。此導電層可以為多層之鋁(Al)、鈀(Pd)、銦(In)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)。此導電材料部份地填入絕緣層140中圖案化孔142，以形成圓柱形導電柱146，作為在半導體晶粒124之導電層138上之互連結構。由於此較窄之圖案化孔142與在孔137上外伸之絕緣層140，此導電材料亦覆蓋孔142之側壁外、即圓柱形導電柱146之垂直占用面積外之孔137中導電層138之部份。在一 實施例中，圓柱形導電柱146之高度為40-50μm。此圓柱形導電柱146電性連接至導電層134與138。
圖3i顯示絕緣層140與圓柱形導電柱146之頂視圖，其形成於該絕緣層中圖案化孔142中。
圖3j中，使用蒸鍍、電解電鍍、無電極電鍍、球滴、或絲網印刷過程，將導電突塊材料148沉積在絕緣層140中圖案化孔142中導電柱146之表面150上。此突塊材料148可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、铋(Bi)、銅(Cu)、焊料、以及其組合，而具有選擇性通量溶液。例如，突塊材料148可以為共晶Sn/Pb、高鉛焊料、或無鉛焊。可以使用適當裝附或接合過程，將突塊材料148接合至導電柱146之表面150。
在一實施例中，藉由將突塊材料148加熱至其熔點以上而回流，以形成突塊蓋152，如同於圖3k中所示。在一些應用中，將突塊蓋152第二次回流，以改善其至導電柱146之電性接觸。亦可將突塊蓋152壓縮接合至導電柱146。導電柱146與突塊蓋152代表一種形式互連結構，其形成於導電層134與138上。
在圖3l中，將絕緣層140去除，而留下圓柱形導電柱146，其具有設置於導電層134與138上之突塊蓋152。在圖3m中，藉由一濕性蝕刻過程，將在絕緣層136上、即在孔137外，導電層138之部份去除。由於導電材料覆蓋圓柱形導電柱146之占用面積外孔137中導電層138之一些部份，此濕性蝕刻過程並無法將靠近圓柱形導電柱146之 導電層138去除。這即是，此濕性蝕刻過程並無法底切此在圓柱形導電柱146下之導電層138。以此方式控制導電層138之蝕刻終止是在導電層136之邊緣發生，即一直至孔137之終端為止。由於在絕緣層140中圖案化孔142之寬度小於在絕緣層136中孔137之寬度，圓柱形導電柱146之寬度亦小於在絕緣層136之孔137中導電層138之寬度。使用鋸刀或雷射切割工具154經由鋸道126，將半導體晶圓120單一化成個別半導體晶粒124。
圖4顯示半導體晶粒124，其具有形成於導電層134與138上之圓柱形導電柱146與突塊蓋152。此圓柱形導電柱146具有用於高密度互連之細微間距。特別是，在絕緣層136中孔137之寬度、與相對應在絕緣層中孔中導電層134與138之寬度，是大於圓柱形導電柱146之寬度。此較寬之導電層134與138、以及在絕緣層136中孔137中導電材料，會降低在圓柱形導電柱146基底周圍之電流密度。由於導電材料覆蓋圓柱形導電柱146之占用面積外之孔137中導電層138之部份，此濕性蝕刻過程無法去除此靠近圓柱形導電柱146之導電層138。藉由避免將導電柱146下之導電層138底切，可以維持在導電柱146與導電層138間之黏著，以增加接合強度。此較窄導電柱146會減少在絕緣層136上之應力，此可以減少絕緣層136之破裂且增加製造可靠度。
圖5類似於圖3a-3l，以顯示半導體晶粒124，其具有形成於導電層134與138上之導電墊156。此導電墊156具 有用於高密度互連之細微間距。特別是，在絕緣層136中孔137之寬度、相對應導電層134與138之寬度，以及在絕緣層中之孔中導電材料之寬度，是大於導電墊156之寬度。此較寬之導電層134與138、以及在絕緣層136中孔137中導電材料，會降低在導電墊156基底周圍之電流密度。由於導電材料覆蓋導電墊156之占用面積外之孔137中導電層138之一些部份，此濕性蝕刻過程無法去除此靠近導電墊156之導電層138。藉由避免將導電墊156下之導電層138底切，可以維持在導電墊156與導電層138間之黏著，而可以增加接合強度。此較窄導電墊156會減少在絕緣層136上之應力，以減少絕緣層136之破裂且增加製造可靠度。
圖6a~6g相對於圖1與2a~2c說明一種過程，在半導體晶粒之接觸墊上之晶種層上形成堆疊式導電墊，並無法底切此堆疊式導電墊下之晶種層。繼續參考圖3f，如同於圖6a中顯示，使用金屬沉積過程，例如：使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍、電解電鍍、無電極電鍍，將導電材料沉積在導電層134與138上絕緣層140中圖案化孔142中。此導電材料可以為多層之鋁(Al)、鈀(Pd)、銦(In)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或銀(Ag)。此導電材料部份地填滿絕緣層140中圖案化孔142，以形成導電墊160。由於此較窄之圖案化孔142與在孔137上外伸之絕緣層140，此導電材料亦覆蓋孔142之側壁外之孔137中導電層138之一些部份。此導電墊160電性連接至導電 層134與138。
在圖6b中，此具有圖案化孔164之保護遮罩層162形成於：導電墊160之表面166上絕緣層140中圖案化孔142中。此保護遮罩層162中圖案化孔164之寬度小於絕緣層140中圖案化孔142之寬度。
在圖6c中，使用金屬沉積過程，例如：物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍、電解電鍍、無電極電鍍，將導電材料沉積在保護遮罩層162中圖案化孔164中導電墊160之表面166上。此導電材料可以為多層之鋁(Al)、鈀(Pd)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或銀(Ag)。此導電材料填滿保護遮罩層162中孔164，以形成堆疊在導電墊160上之導電墊168。導電墊160與168電性連接至導電層134與138。
圖6d顯示絕緣層140與保護遮罩層162之頂視圖，其具有形成於保護遮罩層中圖案化孔164中之導電墊168。
在圖6e中，將保護遮罩層162去除，而留下堆疊在導電墊160上之導電墊168。此在保護遮罩層162中較小圖案化孔164，會造成導電墊168之寬度小於導電墊160之寬度。
使用蒸鍍、電解電鍍、無電極電鍍、球滴、或絲網印刷過程，將導電突塊材料沉積在絕緣層140中圖案化孔142中堆疊式導電墊160與168上。此突塊材料可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、焊料、以及其組合，而具有選擇性通量溶液。例如，突塊材料148可以為共晶Sn/Pb、高鉛焊料、或無鉛焊料。可以 使用適當裝附或接合過程，將突塊材料接合至堆疊式導電墊160與168。在一實施例中，藉由將突塊材料加熱至其熔點以上而回流，以形成突塊170。在一些應用中，將突塊170第二次回流，以改善其至堆疊式導電墊160與168之電性接觸。亦可將突塊170壓縮接合至堆疊式導電墊160與168。此在堆疊式導電墊160與168上所形成突塊170代表一種形式互連結構，其形成於半導體晶粒124之導電層134與138上。以替代方式，此在堆疊式導電墊160與168上之突塊170為一種SPOP。
在圖6f中，將絕緣層140去除，而留下設置在導電層134與138上之突塊170與堆疊式導電墊160與168。在圖6g中，藉由濕性蝕刻過程，將在絕緣層136上導電層138之部份、即在孔137外部份去除。由於導電材料覆蓋孔137中導電層138之一些部份。此濕性蝕刻過程無法將靠近導電墊160之導電層138去除。這即是，此濕性蝕刻過程並無法底切此在導電墊160與168下之導電層138。控制導電層138之蝕刻終止是在絕緣層136之邊緣發生，即一直至孔137之終端為止。使用鋸刀或雷射切割工具172經由鋸道126，將半導體晶圓120單一化成個別半導體晶粒124。
圖7顯示半導體晶粒124，其具有形成於導電層134與138上之突塊170與堆疊式導電墊160與168。此堆疊式導電墊160與168具有細微間距，用於高密度互連。此較寬之導電層134與138、以及在絕緣層136中孔137中導電材料，會降低在堆疊式導電墊160與168基底周圍之電流密 度。由於導電材料覆蓋孔137中導電層138之一些部份，此濕性蝕刻過程無法去除此靠近堆疊式導電墊160與168之導電層138。藉由避免將堆疊式導電墊160與168下之導電層138底切，可以維持在導電墊160與導電層138間之黏著，而可以增加接合強度。此較窄導電墊160會減少在絕緣層136上之應力，此可以減少絕緣層136之破裂且增加製造可靠度。
圖8a~8g相對於圖1與2a~2c說明另一種過程，在半導體晶粒之接觸墊上之晶種層上形成堆疊式導電墊，並無法底切此堆疊式導電墊下之晶種層。繼續參考圖3f，如同於圖8a中顯示，使用金屬沉積過程，例如：物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍、電解電鍍、無電極電鍍，將導電材料沉積在導電層134與138上絕緣層140中圖案化孔142中。此導電材料可以為多層之鋁(Al)、鈀(Pd)、銦(In)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或銀(Ag)。此導電材料部份地填滿絕緣層140中圖案化孔142，以形成導電墊180。由於此較窄之圖案化孔142與在孔137上外伸之絕緣層140，此導電材料亦覆蓋孔142之側壁外之孔137中導電層138之一些部份。此導電墊180電性連接至導電層134與138。
在圖8b中，此具有圖案化孔184之保護遮罩層182形成於：導電墊180之表面186上絕緣層140中圖案化孔142中。此保護遮罩層182中圖案化孔184之寬度小於絕緣層140中圖案化孔142之寬度。
在圖8c中，使用金屬沉積過程，例如：物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍、電解電鍍、無電極電鍍，將導電材料沉積在保護遮罩層182中圖案化孔184中導電墊180之表面186上。此導電材料可以為多層之鋁(Al)、鈀(Pd)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或銀(Ag)。此導電材料填滿保護遮罩層182中孔184，以形成堆疊在導電墊180上之導電墊188。導電墊180與188電性連接至導電層134與138。
圖8d顯示絕緣層140與保護遮罩層182之頂視圖，其具有形成於保護遮罩層中圖案化孔184中之導電墊188。
在圖8e中，將保護遮罩層182去除，而留下堆疊在導電墊180上之導電墊188。此在保護遮罩層182中較小圖案化孔184造成導電墊188之寬度小於導電墊180之寬度。
使用蒸鍍、電解電鍍、無電極電鍍、球滴、或絲網印刷過程，將導電突塊材料沉積在絕緣層140中圖案化孔142中堆疊式導電墊180與188上。此突塊材料可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、焊料、以及其組合，而具有選擇性通量溶液。例如，突塊材料可以為共晶Sn/Pb、高鉛焊料、或無鉛焊料。可以使用適當裝附或接合過程，將突塊材料接合至堆疊式導電墊180與188。在一實施例中，藉由將突塊材料加熱至其熔點以上而回流，以形成突塊190。在一些應用中，將突塊190第二次回流，以改善其至堆疊式導電墊180與188之電性接觸。亦可將突塊190壓縮接合至堆疊式導電墊180與188。此在 堆疊式導電墊180與188上所形成突塊190，其代表在半導體晶粒124之導電層134與138上之一種形式互連結構。以替代方式，此在堆疊式導電墊180與188上所形成突塊190為一種SPOP。
在圖8f中，將絕緣層140去除，而留下設置在導電層134與138上之突塊190與堆疊式導電墊180與188。在圖8g中，藉由濕性蝕刻過程，將在絕緣層136上導電層138之部份、即在孔137外部份去除。由於導電材料覆蓋孔137中導電層138之一些部份。此濕性蝕刻過程無法將靠近導電墊180與188之導電層138去除。這即是，此濕性蝕刻過程並無法底切此在導電墊180與188下之導電層138。控制導電層138之蝕刻終止是在導電層136之邊緣開始，即一直至孔137之終端為止。使用鋸刀或雷射切割工具192經由鋸道126，將半導體晶圓120單一化成個別半導體晶粒124。
圖9顯示半導體晶粒124，其具有形成於導電層134與138上之突塊190與堆疊式導電墊180與188。堆疊式導電墊180與188具有細微間距，用於高密度互連。此較寬之導電層134與138、以及在絕緣層136中孔137中導電材料，會降低在堆疊式導電墊160與168基底周圍之電流密度。由於導電材料覆蓋孔137中導電層138之一些部份，此濕性蝕刻過程無法去除靠近堆疊式導電墊180與188之導電層138。藉由避免將堆疊式導電墊180與188下之導電層138底切，可以維持在導電墊180與導電層138間之黏著， 以增加接合強度。此較窄導電墊180會減少在絕緣層136上之應力，此可以減少絕緣層136之破裂且增加製造可靠度。
雖然，以上已經詳細說明本發明之一或更多個實施例，熟習此技術人士瞭解，可以對此等實施例作修正與調整，而不會偏離在以下申請專利範圍中所界定本發明之範圍。
50‧‧‧電子裝置
52‧‧‧印刷電路板(PCB)
54‧‧‧信號傳導跡線
56‧‧‧接線封裝
58‧‧‧覆晶
60‧‧‧球格柵陣列(BGA)
62‧‧‧突起晶片載體(BCC)
64‧‧‧雙線封裝(DIP)
66‧‧‧閘格柵陣列(LGA)
68‧‧‧多晶片模組(MCM)
70‧‧‧四扁平無引線封裝(QFN)
72‧‧‧四扁平封裝
74‧‧‧半導體晶粒
76‧‧‧接觸墊
78‧‧‧中間載體
80‧‧‧導線
82‧‧‧接線
88‧‧‧半導體晶粒
90‧‧‧載體
92‧‧‧黏著材料
94‧‧‧接線
96‧‧‧接觸墊
98‧‧‧接觸墊
100‧‧‧包封劑
102‧‧‧接觸墊
104‧‧‧突塊
106‧‧‧載體
108‧‧‧主動區域
110‧‧‧突塊
112‧‧‧突塊
114‧‧‧信號線
116‧‧‧包封劑
120‧‧‧半導體晶圓
122‧‧‧基板材料
124‧‧‧半導體晶粒
126‧‧‧鋸道
128‧‧‧表面
130‧‧‧主動表面
132‧‧‧介電層
134‧‧‧導電層
136‧‧‧絕緣層
137‧‧‧孔
138‧‧‧導電層
140‧‧‧絕緣層
142‧‧‧圖案化孔
146‧‧‧導電柱
150‧‧‧表面
152‧‧‧突塊蓋
156‧‧‧導電墊
160‧‧‧導電墊
162‧‧‧遮罩層
164‧‧‧圖案化孔
166‧‧‧表面
168‧‧‧導電墊
170‧‧‧突塊
180‧‧‧導電墊
182‧‧‧遮罩層
184‧‧‧圖案化孔
186‧‧‧表面
188‧‧‧導電墊
190‧‧‧突塊
192‧‧‧雷射切割工具
圖1說明一種印刷電路板(PCB)，其具有安裝至其表面之不同形式封裝；圖2a~2c說明此代表安裝至PCB之半導體封裝之進一步細節；圖3a~3m說明一種過程，在半導體晶粒之接觸墊上之晶種層上形成互連結構，並無法底切此互連結構下之晶種層；圖4說明一種半導體晶粒，其具有形成於半導體晶粒之接觸墊上之晶種層上之互連結構；圖5說明一種半導體晶粒，其具有形成於半導體晶粒之接觸墊上之晶種層上之導電墊；圖6a~6g說明一種過程，在半導體晶粒之接觸墊上之晶種層上形成互連結構，並無法底切此互連結構下之晶種層；圖7說明一種半導體晶粒，其具有形成於半導體晶粒 之接觸墊上之晶種層上之堆疊式導電墊；圖8a~8g說明另一種過程，在半導體晶粒之接觸墊上之晶種層上形成互連結構，並無法底切此互連結構下之晶種層；以及圖9說明一種半導體晶粒，其具有形成於半導體晶粒之接觸墊上之晶種層上之堆疊式導電墊。
124‧‧‧半導體晶粒
128‧‧‧表面
130‧‧‧主動表面
132‧‧‧介電層
134‧‧‧導電層
136‧‧‧絕緣層
138‧‧‧導電層
146‧‧‧導電柱
150‧‧‧表面
152‧‧‧突塊蓋

Claims (15)

  1. 一種製造半導體裝置之方法，包括：提供一基板；在該基板上形成一第一絕緣層；在該第一絕緣層中的一孔中形成一導電層；以及在該導電層上形成一互連結構，並且包含設置在該第一絕緣層中的該孔內的一第一部份且設置在該第一部份上的一第二部份以及包括小於在該第一絕緣層中的該孔的寬度之一寬度。
  2. 如申請專利範圍第1項之方法，更包括：在該互連結構上沉積一突塊材料。
  3. 如申請專利範圍第2項之方法，進一步包括在該互連結構中的一孔中沉積該突塊材料。
  4. 如申請專利範圍第1項之方法，其中在該導電層上形成該互連結構包括：在該第一絕緣層上形成一第二絕緣層，並且包含設置在該導電層上的一孔以及包括小於在該第一絕緣層中的該孔的寬度之一寬度；以及將一第一導電材料沉積在該第二絕緣層中之該孔中。
  5. 如申請專利範圍第4項之方法，更包括：藉由雷射直接在該第二絕緣層中剝離來形成該孔。
  6. 如申請專利範圍第4項之方法，更包括：在該第二絕緣層中的該孔中形成一遮罩層；將一第二導電材料沉積在該第一導電材料上的該遮罩 層中的該孔中；以及將一突塊材料沉積在該第二導電材料上。
  7. 一種製造半導體裝置之方法，包括以下步驟：提供一半導體晶粒；在該半導體晶粒上形成一第一絕緣層；以及在該第一絕緣層中的一孔中形成一互連結構，並且包含小於該第一絕緣層中的該孔的寬度之一寬度。
  8. 如申請專利範圍第7項之方法，更包括：在該第一絕緣層之上以及在該第一絕緣層中的該開口中形成一導電層；以及將該第一絕緣層中的該孔外的該導電層之一部份去除。
  9. 如申請專利範圍第8項之方法，更包括於該互連結構上沉積一突塊材料。
  10. 如申請專利範圍第7項之方法，其中形成該互連結構包括：在該第一絕緣層上形成一第二絕緣層，並且包括含有小於在該第一絕緣層中該孔的寬度之一寬度；以及將一第一導電材料沉積在該第二絕緣層中之該孔中。
  11. 如申請專利範圍第10項之方法，更包括：在該第一導電材料上形成一遮罩層，並且包括含有小於在該第二絕緣層中的該孔的寬度之一寬度；將一第二導電材料沉積在該遮罩層中之該孔中；將該遮罩層去除；以及 將一突塊材料沉積在該第二導電材料上。
  12. 一種半導體裝置，包括：一基板；一導電層，其形成於該基板上；一絕緣層，其形成於該基板上，以及包括在該導電層上之一孔；以及一導電材料，其沉積於該導電層上且包括在該第一絕緣層中的該孔內的一第一寬度以及比該第一寬度還小的一第二寬度。
  13. 如申請專利範圍第12項之半導體裝置，進一步包括沉積在該導電材料上的一突塊材料。
  14. 如申請專利範圍第13項之半導體裝置，其中該突塊材料沉積在該導電材料中的一孔中。
  15. 如申請專利範圍第12項之半導體裝置，其中該基板包括一半導體晶粒。
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