CN102842531A - 在种子层之上形成互连结构的半导体器件和方法 - Google Patents

在种子层之上形成互连结构的半导体器件和方法 Download PDF

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CN102842531A
CN102842531A CN2012102070207A CN201210207020A CN102842531A CN 102842531 A CN102842531 A CN 102842531A CN 2012102070207 A CN2012102070207 A CN 2012102070207A CN 201210207020 A CN201210207020 A CN 201210207020A CN 102842531 A CN102842531 A CN 102842531A
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insulating barrier
opening
conductive
conductive layer
width
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CN102842531B (zh
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W.K.蔡
P.C.马里穆图
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及在种子层之上形成互连结构的半导体器件和方法。一种半导体器件具有半导体管芯，在管芯之上形成有第一导电层。在管芯之上形成第一绝缘层，第一绝缘层中的第一开口被设置在第一导电层之上。在第一绝缘层之上并进入到第一导电层之上的第一开口中形成第二导电层。通过在第一绝缘层之上形成具有具有小于第一开口的宽度的第二开口的第二绝缘层并向第二开口中沉积导电材料来构造互连结构。该互连结构可以是导电柱或导电焊盘。互连结构具有比第一开口的宽度小的宽度。去除第一开口外面的第一绝缘层之上的第二导电层，同时留下互连结构下面的第二导电层。

Description

在种子层之上形成互连结构的半导体器件和方法
技术领域
本发明一般地涉及半导体器件，并且更具体地涉及在不掏蚀（undercut）互连结构下面的种子层的情况下在半导体管芯的接触焊盘上的种子层之上形成互连结构的半导体器件和方法。 
背景技术
常常在现代电子产品中发现半导体器件。半导体器件在电部件的数目和密度方面变化。分立的半导体器件一般包含一种类型的电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含几百个到数以百万的电部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池以及数字微镜器件（DMD）。 
半导体器件执行各种的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将太阳光转变为电力以及产生用于电视显示的视觉投影。在娱乐、通信、功率转换、网络、计算机以及消费产品的领域中发现半导体器件。还在军事应用、航空、汽车、工业控制器和办公设备中发现半导体器件。 
半导体器件利用半导体材料的电属性。半导体材料的原子结构允许通过施加电场或基电流（base current）或通过掺杂工艺而操纵其导电性。掺杂向半导体材料引入杂质以操纵和控制半导体器件的导电性。 
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和施加电场或基电流，晶体管要么促进要么限制电流的流动。包括电阻器、电容器和电感器的无源结构创建为执行各种电功能所必须的电压和电流之间的关系。无源和有源结构电连接以形成电路，这使得半导体器件能够执行高速计算和其他有用功能。 
半导体器件一般使用两个复杂的制造工艺来制造，即，前端制造和和后端制造，每一个可能涉及成百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。每个半导体管芯典型地是相同的且包含通过电连接有源和无源部件而形成的电路。后端制造涉及从完成的晶片分割（singulate）各个半导体管芯且封装管芯以提供结构支撑和环境隔离。本文所使用的术语“半导体管芯”指的是词语的单数和复数形式两者，并且因此可以指的是单个半导体器件和多个半导体器件两者。 
半导体制造的一个目的是生产较小的半导体器件。较小的器件典型地消耗较少的功率、具有较高的性能且可以更高效地生产。另外，较小的半导体器件具有较小的覆盖区，这对于较小的终端产品而言是希望的。较小的半导体管芯尺寸可以通过前端工艺中的改进来获得，该前端工艺中的改进导致半导体管芯具有较小、较高密度的有源和无源部件。后端工艺可以通过电互联和封装材料中的改进而导致具有较小覆盖区的半导体器件封装。 
半导体管芯通常包括用于将管芯安装到基板的互连结构。例如，该互连结构可以是在半导体管芯上的绝缘层中的开口内的接触焊盘之上形成的凸块或导电柱。该凸块或导电柱被通过回流凸块材料而接合到基板以提供半导体管芯与基板之间的机械和电互连。导电柱提供较小互连节距和较高互连和布线密度的优点。 
在导电柱与半导体管芯的接触焊盘之间通常需要种子层以获得良好的粘附。种子层在形成导电柱之前被沉积在绝缘层与半导体管芯的接触焊盘之上，并且随后被从覆盖区导电柱的外面的区域去除（常常通过湿法蚀刻工艺）。已知该湿法蚀刻去除在导电柱下面的种子层的一部分，即湿法蚀刻掏蚀导电柱下面的种子层。然而，掏蚀导电柱下面的种子层弱化了导电柱与半导体管芯的接触焊盘之间的粘附，导致接合点裂缝和制造可靠性问题。较小的互连节距由于不能精确地控制湿法蚀刻速率而增加种子层掏蚀的发生。另外，导电柱被形成上至半导体管芯之上的绝缘层的边缘。在邻近于半导体管芯之上的绝缘层的导电柱的底座周围存在高电流密度，这增加互连电阻。 
发明内容
需要在不掏蚀互连结构下面的种子层的情况下在半导体管芯的接触焊盘上的种子层之上形成诸如导电柱或焊盘的互连结构。因此，在一个实施例中，本发明是一种制造半导体器件的方法，包括步骤：提供半导体晶片；在半导体晶片之上形成第一导电层；在半导体晶片之上形成第一绝缘层，第一绝缘层中的第一开口被设置在第一导电层之上；在第一绝缘层之上并进入第一导电层之上的第一开口中形成第二导电层；在第一和第二导电层之上形成导电柱；以及在留下导电柱下面的第二导电层的同时去除在第一绝缘层中的第一开口外面的第一绝缘层之上的第二导电层的一部分。导电柱具有比第一绝缘层中的第一开口的宽度小的宽度。 
在另一个实施例中，本发明是一种制造半导体器件的方法，包括步骤：提供半导体晶片；在半导体晶片之上形成第一导电层；在半导体晶片之上形成第一绝缘层，第一绝缘层中的第一开口被设置在第一导电层之上；在第一绝缘层之上并进入第一导电层之上的第一开口中形成第二导电层；在第一和第二导电层之上形成互连结构；以及去除在第一绝缘层中的第一开口外面的第一绝缘层之上的第二导电层的一部分。该互连结构具有比第一绝缘层中的第一开口的宽度小的宽度。 
在另一实施例中，本发明是一种制造半导体器件的方法，包括步骤：提供半导体管芯；在半导体管芯之上形成第一绝缘层，在第一绝缘层中具有第一开口；在第一绝缘层之上并进入第一绝缘层中的第一开口中形成第一导电层；以及在第一导电层之上形成互连结构。该互连结构具有比第一绝缘层中的第一开口的宽度小的宽度。 
在另一实施例中，本发明是一种包括半导体管芯和在半导体管芯之上形成的第一导电层的半导体器件。在半导体管芯之上形成有第一绝缘层，第一绝缘层中的第一开口被设置在第一导电层之上。在第一绝缘层之上并进入第一导电层之上的第一开口中形成第二导电层。在第一和第二导电层之上形成互连结构。该互连结构具有比第一绝缘中的第一开口的宽度小的宽度。 
附图说明
图1举例说明具有安装到其表面的不同类型的封装的PCB； 
图2a～2c举例说明被安装到PCB的代表性半导体封装的更多细节；
图3a～3m举例说明在不掏蚀互连结构下面的种子层的情况下在半导体管芯的接触焊盘上的种子层之上形成互连结构的工艺；
图4举例说明具有在半导体管芯的接触焊盘上的种子层之上形成的互连结构的半导体管芯；
图5举例说明具有在半导体管芯的接触焊盘上的种子层之上形成的导电焊盘的半导体管芯；
图6a～6g举例说明在不掏蚀互连结构下面的种子层的情况下在半导体管芯的接触焊盘上的种子层之上形成互连结构的工艺；
图7举例说明具有在半导体管芯的接触焊盘上的种子层之上形成的堆叠导电焊盘的半导体管芯；
图8a～8g举例说明在不掏蚀互连结构下面的种子层的情况下在半导体管芯的接触焊盘上的种子层之上形成互连结构的另一工艺；以及
图9举例说明具有在半导体管芯的接触焊盘上的种子层之上形成的堆叠导电焊盘的半导体管芯。
具体实施方式
在下面的描述中，参考图以一个或更多实施例描述本发明，在这些图中相似的标号代表相同或类似的元件。尽管就用于实现本发明目的的最佳模式描述本发明，但是本领域技术人员应当理解，其旨在覆盖可以包括在如下面的公开和图支持的所附权利要求及其等价物限定的本发明的精神和范围内的替换、修改和等价物。 
半导体器件一般使用两个复杂制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电部件，它们电连接以形成功能电路。诸如晶体管和二极管的有源电部件具有控制电流流动的能力。诸如电容器、电感器、电阻器和变压器的无源电部件创建为执行电路功能所必须的电压和电流之间的关系。 
通过包括掺杂、沉积、光刻、蚀刻和平坦化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺修改了有源器件中半导体材料的导电性，将半导体材料转变为绝缘体、导体，或者响应于电场或基电流而动态地改变半导体材料的导电性。晶体管包含不同类型和掺杂程度的区域，其按照需要被布置为使得当施加电场或基电流时晶体管能够促进或限制电流的流动。 
通过具有不同电属性的材料层形成有源和无源部件。层可以通过部分由被沉积的材料类型确定的各种沉积技术来形成。例如，薄膜沉积可能涉及化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解镀覆和化学镀覆工艺。每一层一般被图案化以形成有源部件、无源部件或部件之间的电连接的部分。 
可以使用光刻对层进行图案化，光刻涉及例如光刻胶的光敏材料在待被图案化的层上的沉积。使用光，图案从光掩模转印到光刻胶。在一个实施例中，经受光的光刻胶图案的部分使用溶剂来去除，露出待被图案化的底层的部分。在另一实施例中，使用溶剂来去除未经受光的那部分光刻胶图案，即负性光刻胶，使待被图案化的底层的部分露出。光刻胶的剩余部分被去除，留下图案化层。替换地，一些类型的材料通过使用诸如化学镀覆和电解镀覆这样的技术来直接向原先沉积/蚀刻工艺形成的区域或空位沉积材料而被图案化。 
在现有图案上沉积材料的薄膜可以放大底层图案且形成不均匀的平坦表面。需要均匀的平坦表面来生产更小且更致密堆叠的有源和无源部件。平坦化可以用于从晶片的表面去除材料且产生均匀的平坦表面。平坦化涉及使用抛光垫对晶片的表面进行抛光。研磨材料和腐蚀化学物在抛光期间被添加到晶片的表面。组合的研磨物的机械行为和化学物的腐蚀行为去除任何不规则外貌，导致均匀的平坦表面。 
后端制造指将完成的晶片切割或分割为各个管芯且然后封装管芯以用于结构支撑和环境隔离。为了分割半导体管芯，晶片沿着称为锯道或划线的晶片的非功能区域被划片且折断。使用激光切割工具或锯条来分割晶片。在分割之后，各个半导体管芯被安装到封装基板，该封装基板包括引脚或接触焊盘以用于与其他系统部件互连。在半导体管芯上形成的接触焊盘然后连接到封装内的接触焊盘。电连接可以使用焊料凸块、柱形凸块、导电胶或引线接合来制成。密封剂或其他模塑料沉积在封装上以提供物理支撑和电隔离。完成的封装然后被插入到电系统中且使得半导体器件的功能性对于其他系统部件可用。 
图1说明具有芯片载体基板或印刷电路板（PCB）52的电子器件50，该芯片载体基板或印刷电路板（PCB）52具有安装在其表面上的多个半导体封装。取决于应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。用于说明性目的，在图1中示出了不同类型的半导体封装。 
电子器件50可以是使用半导体封装以执行一个或更多电功能的独立系统。替换地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数码摄像机（DVC）或其他电子通信器件的一部分。替换地，电子器件50可以是图形卡、网络接口卡或可以被插入到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件或其他半导体管芯或电部件。微型化和重量减小对于这些产品被市场接受是至关重要的。半导体器件之间的距离必须减小以实现更高的密度。 
在图1中，PCB 52提供用于安装到PCB上的半导体封装的结构支撑和电互连的一般性基板。使用蒸发、电解镀覆、化学镀覆、丝网印刷或者其他合适的金属沉积工艺，导电信号迹线54在PCB 52的表面上或其层内形成。信号迹线54提供半导体封装、安装的部件以及其他外部系统部件中的每一个之间的电通信。迹线54还向半导体封装中的每一个提供功率和接地连接。 
在一些实施例中，半导体器件具有两个封装级别。第一级封装是用于机械和电附连半导体管芯到中间载体的技术。第二级封装涉及机械和电附连中间载体到PCB。在其他实施例中，半导体器件可以仅具有第一级封装，其中管芯被直接机械和电地安装到PCB。 
用于说明目的，在PCB 52上示出包括接合引线封装56和倒装芯片58的若干类型的第一级封装。另外，示出在PCB 52上安装的若干类型的第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（LGA）66、多芯片模块（MCM）68、四方扁平无引脚封装（QFN）70以及方形扁平封装72。取决于系统需求，使用第一和第二级封装类型的任何组合配置的半导体封装以及其他电子部件的任何组合可以连接到PCB 52。在一些实施例中，电子器件50包括单一附连的半导体封装，而其他实施例需要多个互连封装。通过在单个基板上组合一个或更多半导体封装，制造商可以将预制部件结合到电子器件和系统中。因为半导体封装包括复杂的功能性，可以使用较廉价的部件和流水线制造工艺来制造电子器件。所得到的器件较不倾向于发生故障且对于制造而言较不昂贵，导致针对消费者的较少的成本。 
图2a-2c示出示例性半导体封装。图2a说明安装在PCB 52上的DIP 64的进一步细节。半导体管芯74包括有源区域，该有源区域包含实现为根据管芯的电设计而在管芯内形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及在半导体管芯74的有源区域内形成的其他电路元件。接触焊盘76是诸如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag）的一层或多层导电材料，且电连接到半导体管芯74内形成的电路元件。在DIP 64的组装期间，半导体管芯74使用金-硅共熔层或者诸如热环氧物或环氧树脂的粘合剂材料而安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导线80和接合引线82提供半导体管芯74和PCB 52之间的电互连。密封剂84沉积在封装上，以通过防止湿气和颗粒进入封装且污染半导体管芯74或接合引线82而进行环境保护。 
图2b说明安装在PCB 52上的BCC 62的进一步细节。半导体管芯88使用底层填料或者环氧树脂粘合剂材料92而安装到载体90。接合引线94提供接触焊盘96和98之间的第一级封装互连。模塑料或密封剂100沉积在半导体管芯88和接合引线94上，从而为器件提供物理支撑和电隔离。接触焊盘102使用诸如电解镀覆或化学镀覆之类的合适的金属沉积工艺而在PCB 52的表面上形成以防止氧化。接触焊盘102电连接到PCB 52中的一个或更多导电信号迹线54。凸块104在BCC 62的接触焊盘98和PCB 52的接触焊盘102之间形成。 
在图2c中，使用倒装芯片类型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区域108包含实现为根据管芯的电设计而形成的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及有源区域108内的其他电路元件。半导体管芯58通过凸块110电和机械连接到载体106。 
使用利用凸块112的BGA类型第二级封装，BGA 60电且机械连接到PCB 52。半导体管芯58通过凸块110、信号线114和凸块112电连接到PCB 52中的导电迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电迹线的短导电路径以便减小信号传播距离、降低电容且改善整体电路性能。在另一实施例中，半导体管芯58可以使用倒装芯片类型第一级封装来直接机械和电地连接到PCB 52而不使用中间载体106。 
图3a～3m相对于图1和2a～2c举例说明在不掏蚀互连结构下面的种子层的情况下在半导体管芯的接触焊盘上的种子层之上形成互连结构的工艺。图3a示出具有基础基板材料122的半导体晶片120，基础基板材料122诸如硅、锗、砷化镓、磷化铟、或碳化硅，用于结构支撑。如上所述，在被非有源、管芯间晶片区域或锯道126分离的晶片120上形成多个半导体管芯或部件124。锯道126提供切割区域以将半导体晶片120分割成单独的半导体管芯124。 
图3b示出半导体晶片120的一部分的横截面图。每个半导体管芯124具有背表面128和有源表面130，有源表面130包含被实现为在管芯内形成并根据管芯的电设计和功能电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，该电路可以包括在有源表面130内形成的一个或多个晶体管、二极管及其它电路元件以实现模拟电路或数字电路，诸如数字信号处理器（DSP）、ASIC、存储器或其它信号处理电路。半导体管芯124还可以包含集成无源器件（IPD），诸如电感器、电容器和电阻器，以进行RF信号处理。在一个实施例中，半导体管芯124是倒装式器件。 
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在有源表面130上形成绝缘或电介质层132。绝缘层132包含二氧化硅（SiO2）、氮化硅（Si3N4）、氧氮化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、苯并环丁烯 （BCB）、聚酰亚胺（PI）、聚苯并恶唑（PBO）或其它适当电介质材料的一个或多个层。 
在图3c中，使用PVD、CVD、电解镀覆、化学镀覆工艺或其它适当的金属沉积工艺在绝缘层132之上形成导电层134。导电层134可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层134充当例如通过通过绝缘层132形成的导电过孔被电连接到有源表面130上的电路的接触焊盘。 
在图3d中，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在绝缘层132和导电层134之上形成绝缘或钝化层136。绝缘层136包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它材料的一层或多层。通过光刻胶层（未示出）用蚀刻工艺去除绝缘层136的一部分以形成设置在导电层134之上并使其露出的开口137。在一个实施例中，绝缘层136中的开口137的宽度和相应地已露出导电层134的宽度是50微米（μm）。 
在图3e中，使用PVD、CVD、电解镀覆、化学镀覆工艺或其它适当的金属沉积工艺在导电层134和绝缘层136之上共形地施加导电层138。导电层138可以是一层或多层Al、Cu、钛（Ti）Sn、Ni、Au、Ag或其它适当的导电材料。导电层138遵循导电层134和绝缘层136的轮廓。在一个实施例中，导电层138是包含Ti/Cu或Ti/Au的多个层且被电连接到导电层134的种子层。 
在图3f中，在绝缘层136和导电层138之上形成厚绝缘层140。在一个实施例中，绝缘层140是具有PET支撑膜的干膜材料。绝缘层140可以具有120μm的厚度。通过使被照射的DFR材料经受显影剂来去除绝缘层140的一部分，显影剂选择性地溶解DFR材料的未被照射部分以在设置于导电层134和138之上的绝缘层140中产生图案化开口142，同时原封不动地留下光刻胶材料的被照射部分。在一个实施例中，绝缘层140中的图案化开口142具有40μm的宽度，其小于开口137的宽度。因此，绝缘层140部分地悬于开口137上。 
在另一实施例中，绝缘层140可以包含通过PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成的一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3、阻焊剂或其它感光材料。通过图案化、暴露于UV光以及显影来去除绝缘层140的一部分以形成开口142并使设置于图案化开口137内的导电层134之上的导电层138的一部分露出。再次地，绝缘层140中的图案化开口142的宽度小于开口137的宽度，使得绝缘层140部分地悬于开口137上。 
替换地，在要求更精细互连尺寸的应用中，可以使用激光器144通过激光直接烧蚀（LDA）来形成图案化开口142以去除绝缘层140的一部分并使设置于图案化开口137内的导电层134之上的导电层138的一部分露出，如图3g所示。 
在图3h中，使用诸如PVD、CVD、溅射、电解镀覆和化学镀覆的金属沉积工艺在绝缘层140中的图案化开口142内的导电层138之上沉积导电材料。导电材料可以是多层的Al、钯（Pd）、铟（In）、Cu、Sn、Ni、Au或Ag。导电材料部分地填充绝缘层140中的图案化开口142以在半导体管芯124的导电层138之上形成圆筒形导电柱146作为互连结构。由于较窄的图案化开口142和使绝缘层140悬于开口137上，导电材料还在开口142的侧壁外面、即在圆筒形导电柱146的垂直覆盖区外面覆盖开口137内的导电层138的一部分。在一个实施例中，导电柱146具有40～50μm的高度。导电柱146被电连接到导电层134和138。 
图3i示出绝缘层140和在绝缘层中的图案化开口142内形成的圆筒形导电柱146的顶视图。 
在图3j中，使用蒸发、电解镀覆、化学镀覆、球滴或丝网印刷工艺在绝缘层140中的图案化开口142内的导电柱146的表面150之上沉积导电凸块材料148。凸块材料148可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，具有可选助熔剂溶液。例如，凸块材料148可以是共熔Sn/Pb、高铅焊料或无铅焊料。使用适当的附着或接合工艺将凸块材料148接合到导电柱146的表面150。在一个实施例中，通过将材料加热至其熔点以上来回流凸块材料148以形成凸块帽152，如图3k所示。在某些应用中，第二次回流凸块帽152以改善到导电柱146的电接触。还可以将凸块帽152压缩接合到导电柱146。导电柱146和凸块帽152表示能够在导电层134和138之上形成的一类互连结构。 
在图3l中，去除绝缘层140，留下圆筒形导电柱146，凸块帽152被设置在导电层134和138之上。在图3m中，用湿法蚀刻工艺来去除在绝缘层136之上、即在开口137外面的那部分导电层138。由于导电材料在圆筒形导电柱146的覆盖区外面覆盖开口137内的那部分导电层138，所以湿法蚀刻工艺不去除接近于导电柱146的导电层138。也就是说，湿法蚀刻工艺不掏蚀导电柱146下面的导电层138。以在绝缘层136的边缘处、即直至开口137的末端发生的方式来控制导电层138的蚀刻终止。由于绝缘层140中的图案化开口142的宽度小于绝缘层136中的开口137的宽度，所以圆筒形导电柱146的宽度也小于绝缘层136的开口137内的导电层138的宽度。使用锯条或激光切割工具154通过锯道126将半导体晶片120分割成单独半导体管芯124。 
图4示出具有在导电层134和138之上形成的圆筒形导电柱146和凸块帽152的半导体管芯124。导电柱146具有小节距以获得高密度互连。特别地，绝缘层136中的开口137的宽度以及相应地绝缘层中的开口内的导电层134和138的宽度大于圆筒形导电柱146的宽度。较宽的导电层134和138及绝缘层136中的开口137内的导电材料减小导电柱146的底座周围的电流密度。由于导电材料在导电柱146的覆盖区外面覆盖开口137内的那部分导电层138，所以湿法蚀刻工艺不去除接近于导电柱146的导电层138。通过避免对导电柱146下面的导电层138的掏蚀，保持了导电柱146与导电层138之间的粘附，这增加接合点强度。较窄的导电柱146减小绝缘层136上的应力，这减少绝缘层136的开裂并增加制造可靠性。 
图5示出具有在导电层134和138之上形成的导电焊盘156的半导体管芯124，类似于图3a～3l。导电焊盘156具有小节距以获得高密度互连。特别地，绝缘层136中的开口137的宽度以及相应地导电层134和138及绝缘层中的开口内的导电材料的宽度大于导电焊盘156的宽度。较宽的导电层134和138及绝缘层136中的开口137内的导电材料减小导焊盘156的底座周围的电流密度。由于导电材料在导电焊盘156的覆盖区外面覆盖开口137内的那部分导电层138，所以湿法蚀刻工艺不去除接近于导电焊盘156的导电层138。通过避免对导电焊盘156下面的导电层138的掏蚀，保持了导电焊盘156与导电层138之间的粘附，这增加接合点强度。较窄的导电焊盘156减小绝缘层136上的应力，这减少绝缘层136的开裂并增加制造可靠性。 
图6a～6g相对于图1和2a～2c举例说明在不掏蚀堆叠导电焊盘下面的种子层的情况下在半导体管芯的接触焊盘上的种子层之上形成堆叠导电焊盘的工艺。从图3f继续，使用诸如PVD、CVD、溅射、电解镀覆和化学镀覆的金属沉积工艺在设置于导电层134和138之上的绝缘层140中的图案化开口142内沉积导电材料，如图6a所示。导电材料可以是多层的Al、Pd、In、Cu、Sn、Ni、Au或Ag。导电材料部分地填充绝缘层140中的图案化开口142以形成导电焊盘160。由于较窄的图案化开口142和使绝缘层140悬于开口137上，导电材料还在开口142的侧壁外面覆盖开口137内的那部分导电层138。导电焊盘160被电连接到导电层134和138。 
在图6b中，在导电焊盘160的表面之上的绝缘层140中的图案化开口142内形成具有图案化开口164的保护性掩模层162。保护性掩模层162中的图案化开口164具有比绝缘层140中的图案化开口142的宽度小的宽度。 
在图6c中，使用诸如PVD、CVD、溅射、电解镀覆和化学镀覆的金属沉积工艺在保护性掩模层162中的图案化开口164内的导电焊盘160的表面166之上沉积导电材料。导电材料可以是多层的Al、Pd、Cu、Sn、Ni、Au或Ag。导电材料填充保护性掩模层162中的开口164以形成堆叠在导电焊盘160之上的导电焊盘168。导电焊盘160和168被电连接到导电层134和138。 
图6d示出绝缘层140和保护性掩模层162的顶视图，在保护性掩模层中的图案化开口164内形成有导电焊盘168。 
在图6e中，去除保护性掩模层162，留下堆叠在导电焊盘160之上的导电焊盘168。掩模层162中的较小图案化开口164促使导电焊盘168的宽度小于导电焊盘160的宽度。 
使用蒸发、电解镀覆、化学镀覆、球滴或丝网印刷工艺在绝缘层140中的图案化开口142内的堆叠导电焊盘160和168之上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，具有可选助熔剂溶液。例如，凸块材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。使用适当的附着或接合工艺将凸块材料接合到堆叠导电焊盘160和168。在一个实施例中，通过将材料加热至其熔点以上对凸块材料进行回流以形成凸块170。在某些应用中，第二次回流凸块170以改善到堆叠导电焊盘160和168的电接触。还可以将凸块170压缩接合到堆叠导电焊盘160和168。在堆叠导电焊盘160和168之上形成的凸块170表示半导体管芯124的导电层134和138之上的一种互连结构。替换地，堆叠导电焊盘160和168之上的凸块170是SPOP。 
在图6f中，去除绝缘层140，留下设置在导电层134和138之上的凸块170和堆叠导电焊盘160和168。在图6g中，用湿法蚀刻工艺来去除在绝缘层136之上、即在开口137外面的那部分导电层138。由于导电材料覆盖开口137内的那部分导电层138，所以湿法蚀刻工艺不去除接近于导电焊盘160的导电层138。也就是说，湿法蚀刻工艺不掏蚀导电焊盘160和168下面的导电层138。导电层138的蚀刻终止被控制为在绝缘层136的边缘处、即直至开口137的末端发生。使用锯条或激光切割工具172通过锯道126将半导体晶片120分割成单独半导体管芯124。 
图7示出具有在导电层134和138之上形成的凸块170和堆叠导电焊盘160和168的半导体管芯124。堆叠导电焊盘160和168具有小节距以获得高密度互连。较宽的导电层134和138及绝缘层136中的开口137内的导电材料减小堆叠导焊盘160和168的底座周围的电流密度。由于导电材料覆盖开口137内的那部分导电层138，所以湿法蚀刻工艺不去除接近于堆叠导电焊盘160和168的导电层138。通过避免对堆叠导电焊盘160和168下面的导电层138的掏蚀，保持了导电焊盘160与导电层138之间的粘附，这增加接合点强度。较窄的导电焊盘160减小绝缘层136上的应力，这减少绝缘层136的开裂并增加制造可靠性。 
图8a～8g相对于图1和2a～2c举例说明在不掏蚀堆叠导电焊盘下面的种子层的情况下在半导体管芯的接触焊盘上的种子层之上形成堆叠导电焊盘的另一工艺。从图3f继续，使用诸如PVD、CVD、溅射、电解镀覆和化学镀覆的金属沉积工艺在设置于导电层134和138之上的绝缘层140中的图案化开口142内沉积导电材料，如图8a所示。导电材料可以是多层的Al、Pd、In、Cu、Sn、Ni、Au或Ag。导电材料部分地填充绝缘层140中的图案化开口142以形成导电焊盘180。由于较窄的图案化开口142和使绝缘层140悬于开口137上，导电材料还在开口142的侧壁外面覆盖开口137内的那部分导电层138。导电焊盘180被电连接到导电层134和138。 
在图8b中，在导电焊盘180的表面186之上的绝缘层140中的图案化开口142内形成具有图案化开口184的保护性掩模层182。保护性掩模层182中的图案化开口184具有比绝缘层140中的图案化开口142的宽度小的宽度。 
在图8c中，使用诸如PVD、CVD、溅射、电解镀覆和化学镀覆的金属沉积工艺在保护性掩模层182中的图案化开口184内的导电焊盘180的表面186之上沉积导电材料。导电材料可以是多层的Al、Pd、Cu、Sn、Ni、Au或Ag。导电材料填充保护性掩模层182中的开口184以形成堆叠在导电焊盘180之上的导电焊盘188。导电焊盘180和188被电连接到导电层134和138。 
图8d示出绝缘层140和保护性掩模层182的顶视图，在保护性掩模层中的图案化开口184内形成有导电焊盘188。 
在图8e中，去除保护性掩模层182，留下堆叠在导电焊盘180之上的导电焊盘188。掩模层182中的较小图案化开口184促使导电焊盘188的宽度小于导电焊盘180的宽度。 
使用蒸发、电解镀覆、化学镀覆、球滴或丝网印刷工艺在绝缘层140中的图案化开口142内的堆叠导电焊盘180和188之上沉积导电凸块材料。凸块材料234可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，具有可选助熔剂溶液。例如，凸块材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。使用适当的附着或接合工艺将凸块材料接合到堆叠导电焊盘180和188。在一个实施例中，通过将材料加热至其熔点以上对凸块材料进行回流以形成凸块190。在某些应用中，第二次回流凸块190以改善到堆叠导电焊盘180和188的电接触。还可以将凸块190压缩接合到堆叠导电焊盘180和188。在堆叠导电焊盘180和188之上形成的凸块190表示半导体管芯124的导电层134和138之上的一种互连结构。替换地，堆叠导电焊盘180和188之上的凸块190是SPOP。 
在图8f中，去除绝缘层140，留下设置在导电层134和138之上的凸块190和堆叠导电焊盘180和188。在图8g中，用湿法蚀刻工艺来去除在绝缘层136之上、即在开口137外面的那部分导电层138。由于导电材料覆盖开口137内的那部分导电层138，所以湿法蚀刻工艺不去除接近于导电焊盘180和188的导电层138。也就是说，湿法蚀刻工艺不掏蚀导电焊盘180和188下面的导电层138。导电层138的蚀刻终止被控制以在绝缘层136的边缘处、即直至开口137的末端发生。使用锯条或激光切割工具192通过锯道126将半导体晶片120分割成单独半导体管芯124。 
图9示出具有在导电层134和138之上形成的凸块190和堆叠导电焊盘180和188的半导体管芯124。堆叠导电焊盘180和188具有小节距以获得高密度互连。较宽的导电层134和138及绝缘层136中的开口137内的导电材料减小堆叠导焊盘160和168的底座周围的电流密度。由于导电材料覆盖开口137内的那部分导电层138，所以湿法蚀刻工艺不去除接近于堆叠导电焊盘180和188的导电层138。通过避免对堆叠导电焊盘180和188下面的导电层138的掏蚀，保持了导电焊盘180与导电层138之间的粘附，这增加接合点强度。较窄的导电焊盘180减小绝缘层136上的应力，这减少绝缘层136的开裂并增加制造可靠性。 
尽管已经详细说明了本发明的一个或更多实施例，但是本领域技术人员应当意识到，可以在不偏离如随后的权利要求提及的本发明的范围的情况下对那些实施例做出修改和改写。 

Claims (15)

1.一种制造半导体器件的方法，包括：
提供半导体晶片；
在半导体晶片之上形成第一导电层；
在半导体晶片之上形成第一绝缘层，第一绝缘层中的第一开口被设置在第一导电层之上；
在第一绝缘层之上并进入到第一导电层之上的第一开口中形成第二导电层；
在第一和第二导电层之上形成互连结构；以及
在第一绝缘层中的第一开口外面去除第一绝缘层之上的第二导电层的一部分，该互连结构具有比第一绝缘层中的第一开口的宽度小的宽度。
2.权利要求1的方法，其中，该互连结构包括导电柱或导电焊盘。
3.权利要求2的方法，还包括在导电柱或导电焊盘之上形成凸块材料。
4.权利要求1的方法，其中，在第一和第二导电层之上形成互连结构包括：
在第一绝缘层之上形成第二绝缘层，第二绝缘层中的第二开口被设置在第一和第二导电层之上，该第二开口具有比第一绝缘层中的第一开口的宽度小的宽度；
向第二绝缘层的第二开口中沉积导电材料以形成互连结构；以及
去除第二绝缘层以留下具有小于第一绝缘层中的第一开口的宽度的宽度的互连结构。
5.权利要求4的方法，还包括通过激光直接烧蚀在第二绝缘层中形成第二开口以使第二导电层露出。
6.权利要求1的方法，其中，在第一和第二导电层之上形成互连结构包括：
在第一绝缘层之上形成第二绝缘层，第二绝缘层中的第二开口被设置在第一和第二导电层之上，该第二开口具有比第一绝缘层中的第一开口的宽度小的宽度；以及
向第二绝缘层的第二开口中沉积第一导电材料以形成第一导电焊盘。
7.权利要求6的方法，其中，在第一和第二导电层之上形成互连结构还包括：
在第一导电材料之上形成掩模层，掩模层中的第三开口被设置在第一导电焊盘之上，该第三开口具有比第二绝缘层中的第二开口的宽度小的宽度；
向掩模层的第三开口中沉积第二导电材料以形成堆叠在第一导电焊盘之上的第二导电焊盘；
去除掩模层；
在第一和第二导电焊盘之上沉积凸块材料；以及
去除第二绝缘层以留下互连结构。
8.一种制造半导体器件的方法，包括：
提供半导体管芯；
在半导体管芯之上形成第一绝缘层，在第一绝缘层中具有第一开口；
在第一绝缘层之上并进入到第一绝缘层中的第一开口中形成第一导电层；以及
在第一导电层之上形成互连结构，该互连结构具有比第一绝缘层中的第一开口的宽度小的宽度。
9.权利要求8的方法，还包括在第一绝缘层中的第一开口外面去除第一绝缘层之上的第一导电层的一部分。
10.权利要求8的方法，其中，在第一和第二导电层之上形成互连结构包括：
在第一绝缘层之上形成第二绝缘层，第二绝缘层中的第二开口被设置在第一导电层之上，该第二开口具有比第一绝缘层中的第一开口的宽度小的宽度；
向第二绝缘层的第二开口中沉积导电材料以形成互连结构；以及
去除第二绝缘层以留下具有小于第一绝缘层中的第一开口的宽度的宽度的互连结构。
11.权利要求8的方法，其中，在第一和第二导电层之上形成互连结构包括：
在第一绝缘层之上形成第二绝缘层，第二绝缘层中的第二开口被设置在第一导电层之上，该第二开口具有比第一绝缘层中的第一开口的宽度小的宽度；以及
向第二绝缘层的第二开口中沉积第一导电材料以形成第一导电焊盘。
12.权利要求11的方法，其中，在第一和第二导电层之上形成互连结构还包括：
在第一导电材料之上形成掩模层，掩模层中的第三开口被设置在第一导电焊盘之上，该第三开口具有比第二绝缘层中的第二开口的宽度小的宽度；
向掩模层的第三开口中沉积第二导电材料以形成堆叠在第一导电焊盘之上的第二导电焊盘；
去除掩模层；
在第一和第二导电焊盘之上沉积凸块材料；以及
去除第二绝缘层以留下具有小于第一绝缘层中的第一开口的宽度的宽度的互连结构。
13.一种半导体器件，包括：
半导体管芯；
在半导体管芯之上形成的第一导电层；
在半导体管芯之上形成的第一绝缘层，第一绝缘层中的第一开口被设置在第一导电层之上；
在第一绝缘层之上并进入到第一导电层之上的第一开口中而形成的第二导电层；以及
在第一和第二导电层之上形成的互连结构，该互连结构具有比第一绝缘层中的第一开口的宽度小的宽度。
14.权利要求13的半导体器件，其中，在第一绝缘层中的第一开口外面去除第一绝缘层之上的第二导电层的一部分。
15.权利要求13的半导体器件，其中，该互连结构包括导电柱或导电焊盘。
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