CN105980840B - 制造具有凸起接触的半导体器件的方法 - Google Patents

制造具有凸起接触的半导体器件的方法 Download PDF

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CN105980840B
CN105980840B CN201580007271.2A CN201580007271A CN105980840B CN 105980840 B CN105980840 B CN 105980840B CN 201580007271 A CN201580007271 A CN 201580007271A CN 105980840 B CN105980840 B CN 105980840B
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conductor
another
dielectric layer
conductive material
opening
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CN105980840A (zh
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约亨·克拉夫特
卡尔·罗拉赫尔
马丁·施雷姆斯
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Ams Osram AG
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Austriamicrosystems AG
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Abstract

在半导体衬底(1)上或上方的介电层(2)中形成包括电导体(4、5、6、7)的布线(3)，在所述介电层中形成开口使由所述导体之一形成的接触焊垫(8)露出，并且在所述介电层中形成另一开口使与所述接触焊垫分离的另一导体(5)的区域露出。用导电材料(9)填充所述另一开口，并且从与所述衬底相对的侧使所述介电层变薄，从而使得所述导电材料从所述介电层凸起。

Description

制造具有凸起接触的半导体器件的方法
US 5 767 001公开了一种用于三维集成的半导体器件，其包括穿透衬底并且从后表面凸起的触针。
US 5 910 020公开了一种用于半导体器件的制造方法，所述制造方法通过在布线上形成钨柱并且施加铝合金以使钨柱的上表面和侧表面接触，所述铝合金在氧化硅层的上方延伸。
EP 2554980 A1公开了一种具有传感器的集成电路，其包括具有通过介电层彼此绝缘的堆叠的图案化金属层的衬底。上部金属层包括第一电极、第二电极、接合焊垫和加热元件。
US 2009/0200664 A1公开了一种包括晶片、SiN钝化膜及聚酰亚胺膜的半导体器件的制造方法。金属层包括在半导体晶片表面上的铝电极垫片(特别地，接合焊垫)，在聚酰亚胺膜的上方延伸的布线层，以及焊锡凸块。布线层的一些被拉长为基本上矩形的形状。
M.-S.Wang等在Advanced Materials 22(2010)的第93页至第98页发表的：“Interface Dynamic Behavior Between a Carbon Nanotube and Metal Electrode”中描述了单个碳纳米管(CNTs)和磨尖钨电极之间的接触。电极的末端吸收源CNT原子，然后源CNT原子穿透至电极本体深处，形成碳化物，并且最终沉淀为新形成的石墨管壳以封装电极。
本发明的目的是公开一种制造便利电连接至纳米管结构的半导体器件的方法。
该目的是根据权利要求1所述的制造半导体器件的方法实现的。实施例和变型来自从属权利要求。
该半导体器件包括：半导体衬底；在衬底上或上方的介电层；布置在介电层中的包括电导体的布线；以及由所述导体中的一个导体形成的接触焊垫。导电材料的另一导体被布置在介电层中与所述导体中的另一个导体接触，所述导体中的另一个导体与接触焊垫分离。所述另一导体在介电层相对于衬底的远侧上从介电层凸起。
该半导体器件还可以包括在介电层的远侧上的钝化层，使得所述另一电导体也从钝化层凸起。介电层和钝化层可以包括不同的材料。特别地，例如介电层可以是氧化硅如SiO2，并且钝化层可以是氮化硅如Si3N4。
特别地，所述另一导体可以具有以纵向延伸的细长脊的形状。脊通常可以具有沿它的纵向延伸的长度和垂直其纵向延伸的宽度，长度至少是宽度的三倍。所述另一导体可以凸起在20nm至100nm范围中的高度。所述另一导体可以包括多个单导体。单导体的每一个可以具有以纵向延伸的细长脊的形状，并且特别地，纵向延伸可以彼此平行。所述另一导体可以包括钨或铜。
通孔可以穿透半导体衬底，并且金属化层可以被布置在通孔中与所述导体中的一个导体接触，由此形成贯通衬底通路。
本方法包括：在半导体衬底上或上方的介电层中形成电导体的布线；在介电层中形成开口使由所述导体中的一个导体形成的接触焊垫露出；以及在介电层中形成另一开口使与接触焊垫分离的所述导体中的另一个导体的区域露出。用导电材料填充另一开口，并且从与衬底相对的侧使介电层变薄，从而使得导电材料从介电层凸起。
在本方法的一个变型中，导电材料还被填充在露出接触焊垫的开口中，并且导电材料的一部分被去除，使得在开口中由导电材料的剩余部分形成间隔物，同时另一开口保持至少一半被填充。
在本方法的另一变型中，另一开口由沟槽形成。
在本方法的另一变型中，另一开口由多个平行沟槽形成。
在本方法的另一变型中，填充另一开口的导电材料包括与电导体不同的金属。
下面是结合附图对制造方法的示例的详细描述。
图1是半导体器件的截面图。
图2是根据图1的包括纳米管布置的截面图。
图3是根据图1的器件的顶视图。
图4是根据图2的布置的顶视图。
图5是该制造方法的中间产品的截面图。
图6是在施加导电材料之后根据图5的截面图。
图7是在部分去除导电材料之后根据图6的截面图。
图8是包括贯通衬底通路的另一半导体器件的截面图。
图1是半导体器件的截面图，包括可以是例如硅的半导体衬底1，在半导体衬底1上的介电层2，以及嵌在可以是氧化硅，特别地，例如二氧化硅的介电层2中的布线3。布线3包括电导体，特别地，所述电导体可以由例如结构化的金属层6和竖直互连部7如金属塞形成。布线3可以被设置用于集成电路，如在半导体衬底1中集成的CMOS电路。接触焊垫8由通常可以属于最上部的金属化层的所述电导体中的一个电导体4形成。
与接触焊垫8分离的所述电导体中的另一个电导体5被设置有另一电导体9，所述另一电导体9从介电层2相对于半导体衬底1的远侧上凸起。钝化层10可以被施加在如图1所示的介电层2上，特别地，所述钝化层10可以由例如与介电层2的材料不同的材料形成，并且可以包括氮化硅如Si3N4。如果钝化层10存在，则另一导体9也从钝化层10凸起。另一导体9凸起的高度h通常可以从20nm至100nm的范围变化。例如，在标准方式中，接触焊垫8可以被设置有另一导电材料如凸点下金属化层18。
图2是根据图1的截面图，并且示意性地示出了具有另一器件的半导体器件的布置，特别地，另一器件可以是被设置有气敏材料如SnO2或碳纳米管的气体传感器、化学传感器或湿度传感器。通过示例的方式，图2示出了与另一导体9的凸起端接触的纳米管11的平行布置。
图3是根据图1的半导体器件的顶视图。在图3中用水平点划线示出了图1所示横截面的位置。图3所示与图1所示元件对应的元件用相同的附图标记表示。接触焊垫8由被介电层2和/或钝化层10部分地覆盖的电导体4形成。电导体4和另一电导体5的轮廓线在图3中用虚线示为隐藏的轮廓。在图3中还示出了连接至电导体4和另一电导体5的竖直互连部17的位置。在根据图1和图3的半导体器件中，另一导体9包括多个单导体19，单导体19的每一个具有具有纵向延伸e的细长脊12的形状。特别地，纵向延伸e可以彼此平行。通过示例的方式，如图3所示，脊12可以全部具有相同的尺寸或可以具有不同的尺寸。脊12沿它的纵向延伸e测量的长度d，通常超过它的宽度w至少3倍。
图4是根据图2的布置的顶视图，并且示出了跨形成另一导体9的单导体19延伸的纳米管11的布置。图4所示的与图3所示的元件对应的其他元件用相同的附图标记表示。形成单导体19的脊12的平行布置并且纳米管11的横向平行布置是优选的，以便于纳米管11与另一导体9的连接。
图5是该制造方法的中间产品的截面图。半导体衬底1设置有包括布线3的介电层2。图5未示出钝化层10，该钝化层10可以选择性地被施加在介电层2上，并且本质上不改变该方法的步骤。在介电层2中形成开口13，使由导体中的一个导体4形成的接触焊垫8露出，并且在介电层2中形成另一开口14，使导体中与接触焊垫8分离的另一个导体5的区域露出。开口13和另一开口14可以用相同的方法步骤形成，特别地，通过在开口13和另一开口14要被形成的区域中使用具有窗口的掩模。特别地，例如另一开口14可以是多个平行沟槽。沟槽的长度大于沟槽的宽度，通常是至少3倍。
图6是在施加导电材料15之后的根据图5的截面图，特别地，导电材料15是包括金属如钨或铜的材料，所述金属可以形成整层。在施加导电材料15之前，可以是例如TiN并且未在图6中示出的薄衬套可以被施加在要被导电材料15覆盖的整个表面上。用导电材料15填充另一开口14，由此形成另一导体9。然后，去除覆盖介电层2(或钝化层10，如果钝化层10被设置)上表面的导电材料15的上部。这可以通过相对于介电层2(或钝化层10，如果钝化层10被设置)和/或衬套选择性地蚀刻导电材料15，特别地，通过反应离子蚀刻(RIE)来实现。蚀刻步骤可能在另一开口14的区域中产生轻微凹陷，然而另一开口14保持至少一半被填充。或者可以通过化学机械抛光(CMP)去除导电材料15的上部，其产生基本上平整的表面，同时另一开口14保持完全被填充。
图7是通过选择性蚀刻去除导电材料15的上部之后根据图6的截面图。蚀刻步骤优选地被各向异性地执行，使得在接触焊垫8上方的开口13的侧壁处产生由导电材料15的剩余部分组成的间隔物16。然后，从与半导体衬底1相对的表面使介电层2(或钝化层10，如果钝化层10被设置)变薄，直到另一导体9足够远地从介电层2凸起，并且由此获得与图1所示实施例相似的实施例。
通过所述的方法，可以在标准CMOS工艺中仅附加很少的与标准CMOS工艺完全兼容的方法步骤来制造半导体器件。凸起的另一导体9便利电连接至另一器件的元件，特别地，例如连接至包括气敏材料的元件，如碳纳米管。
图8是包括贯通衬底通路的另一半导体器件的截面图。从背侧进入半导体衬底1蚀刻通孔20，并且露出布线3的导体中的一个导体6的背侧接触区域。形成另一介电层21使半导体材料绝缘。金属化层22被布置在通孔20中与布线3的电导体6的背侧接触区域接触。金属化层22可以与在金属化层背部上的另一背侧接触区域23电连接，所述另一背侧接触区域23被设置用于外部电连接。由此形成穿透半导体衬底1的电互连部。在接触区域23上方开口的另一钝化层24可以被施加在背侧上以及通孔20内的金属化层22上。
附图标记列表
1 半导体衬底
2 介电层
3 布线
4 电导体
5 另一电导体
6 金属层
7 竖直互连部
8 接触焊垫
9 另一导体
10 钝化层
11 纳米管
12 脊
13 开口
14 另一开口
15 导电材料
16 间隔物
17 竖直互连部
18 凸点下金属化层
19 单导体
20 通孔
21 另一介电层
22 金属化层
23 接触区域
24 另一钝化层
d 长度
e 纵向方向
f 高度
w 宽度

Claims (5)

1.一种制造半导体器件的方法，包括：
在半导体衬底上或上方的介电层中形成包括电导体的布线；
在所述介电层中形成开口使由所述电导体中的一个导体形成的接触焊垫露出；
在所述介电层中形成另一开口，并且由此露出与所述接触焊垫分离的所述电导体中的另一个导体的区域；
用导电材料填充所述另一开口；以及
从与所述衬底相对的侧使所述介电层变薄，
其中，在不进一步暴露最上部的金属化层的情况下使所述介电层变薄，使得所述最上部的金属化层保持被变薄的介电层部分地覆盖，
其中，所述导电材料从变薄的介电层凸起并且形成所述另一个导体，
其中，所述另一个导体凸起的高度从20nm至100nm的范围变化，
其中，形成所述接触焊垫的所述一个导体以及其上施加有其他导体的所述另一个导体都属于所述最上部的金属化层。
2.根据权利要求1所述的方法，其中，
所述导电材料还填充在露出所述接触焊垫的所述开口中，以及
所述导电材料的一部分被去除，使得由所述导电材料的剩余部分在所述开口中形成间隔物，并且所述另一开口保持至少一半被填充。
3.根据权利要求1所述的方法，其中，所述另一开口由沟槽形成。
4.根据权利要求1所述的方法，其中，所述另一开口由多个平行沟槽形成。
5.根据权利要求1所述的方法，其中，填充所述另一开口的所述导电材料包括与所述电导体不同的金属。
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