CN105977203A - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN105977203A
CN105977203A CN201610326224.0A CN201610326224A CN105977203A CN 105977203 A CN105977203 A CN 105977203A CN 201610326224 A CN201610326224 A CN 201610326224A CN 105977203 A CN105977203 A CN 105977203A
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layer
substrate
opening
dielectric layer
crystal seed
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CN105977203B (zh
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许芝菁
欧英德
府玠辰
黄哲豪
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明关于一种半导体元件及其制造方法。该半导体元件包括一基板、一第一重布层及一导电孔。该基板具有一基板本体及一焊垫。该焊垫及该第一重布层邻近于该基板本体的第一表面，且彼此电性连接。互连金属位于该基板本体的一贯穿孔中，且接触该第一重布层。藉此，该焊垫可经由该第一重布层及该导电孔电性连接至该基板本体的第二表面。

Description

半导体元件及其制造方法
本申请是申请人于2013年1月14日提交的、申请号为“201310012910.7”的、发明名称为“半导体元件及其制造方法”的发明专利申请的分案申请。
技术领域
本发明关于一种半导体封装，特别的是，关于三维(3D)半导体封装。
背景技术
已知半导体元件的制造方法的起始步骤中，晶圆厂所提供的基板可能具有各种不良的特性。举例而言，焊垫的尺寸可能太小，或者其可能具有太多不同电路、金属层及介电层而阻碍导电孔(Conductive Vias)形成于该基板中。特言之，要进行后钻孔(Via Last)工艺以从该晶圆背面蚀刻贯穿该基板以到达该原始焊垫是有困难的。
发明内容
本揭露的一方面关于一种半导体元件。在一实施例中，该半导体元件包括一基板，具有一焊垫；一第一重布层，邻近于该基板的一第一表面，且电性连接至该焊垫；及一导电孔，形成于该基板中。该导电孔包含一环状晶种层及一互连层，该环状晶种层位于该基板上，该互连层具有一位于该晶种层的一内表面上的外表面，且电性连接至该第一重布层。该基板具有一介电层，位于该基板的该第一表面上，该介电层具有一显露该焊垫的第一开口及一对应该导电孔的第二开口。该导电孔延伸至该介电层的该第二开口内。在一实施例中，该第一重布层的一部分延伸至该介电层的该第二开口内。该半导体元件更包括一第二重布层，邻近于该基板的一第二表面，且电性连接至该导电孔。此外，该半导体元件包括一球下金属层(Under BumpMetallurgy，简称UBM)，位于该第二重布层上；及一焊球，位于该球下金属层(UnderBump Metallurgy，简称UBM)上。
本揭露的另一方面关于一种制造方法。在一实施例中，一种半导体元件的制造方法包括提供一基板，该基板具有一焊垫；形成一第一重布层邻近于该基板的一第一表面，其中该第一重布层电性连接至该焊垫；将该基板附着至一载体上；及形成一导电孔于该基板中，该导电孔电性连接至该第一重布层。该基板具有一介电层，位于该基板的该第一表面上，且该第一介电层具有一显露该焊垫的第一开口。该方法更包括形成一第二重布层邻近于该基板的一第二表面，其中该第二重布层电性连接至该导电孔。
附图说明
图1显示本发明的一实施例的半导体元件的剖视示意图；
图2至图16显示本发明图1的该半导体元件的制造方法的一实施例的示意图；
图17显示本发明的另一实施例的半导体元件的剖视示意图；及
图18至图20显示本发明图17的该半导体元件的制造方法的另一实施例的示意图。
具体实施方式
参考图1，显示本发明的一实施例的半导体元件1的剖视示意图。该半导体元件1包括一基板10、一第一重布层24、一第二重布层39、一保护层40、一球下金属层(Under Bump Metallurgy，简称UBM)44及一焊球45。
如图1所示，该基板10具有一基板本体11(包含一导电孔20形成于其内)、一焊垫12及一第一介电层13。在本实施例中，该基板本体11的材质为硅。然而，在其他实施例中，该基板本体11的材质可以是玻璃。该基板本体11具有一第一表面111、一第二表面112及一通孔113。该焊垫12邻近于该基板本体11的第一表面111。在本实施例中，该第一介电层13位于该基板本体11的该第一表面111上，且具有一第一开口131及一第二开口132。该第一介电层13覆盖该焊垫12，除了该第一开口131显露该焊垫12的一部份。该第二开口132的位置对应该导电孔20的位置。该第一介电层13的材质可以是聚亚酰胺(PI)或聚丙烯(PP)。
在图1中，该第一重布层24邻近于该基板本体11的该第一表面111，且电性连接至该焊垫12。在本实施例中，该第一重布层24包括一第一晶种层21及一第一金属层23。该第一晶种层21的材质为氮化钽(Tantalum Nitride)或钨化钽(TantalumTungsten)，且该第一金属层23的材质为铜。然而，该第一晶种层21可以被省略；亦即，该第一金属层23可以直接位于该第一介电层13上。该第一重布层24位于该第一介电层13上，且接触位于该第一介电层13第一开口131内的焊垫12。
在图1中，该导电孔20位于该基板本体11的该通孔113中，且接触该第一重布层24。在本实施例中，该导电孔20更延伸至该第一介电层13的该第二开口132内。该导电孔20包含一中心绝缘材料31及一互连金属30。在本实施例中，该互连金属30为杯状且定义出一中心槽，且该中心绝缘材料31位于该中心槽中。可以理解的是，该互连金属30可以是一实心柱(因此该中心绝缘材料31可以被省略)。较佳地，该导电孔20更具有一互连晶种层29，其环绕该互连金属30，且该互连晶种层29的底部接触该第一重布层24，且该导电孔20与该第一重布层24间具有一界面(Interface)。在本实施例中，该基板10更具有一外绝缘材料34，位于该通孔113中且环绕该互连金属30及该互连晶种层29。如图1所示，该外绝缘材料34并未延伸至该第一介电层13的该第二开口132中；因此，该导电孔20的底面并未和该外绝缘材料34的底面共平面，且该导电孔20的长度大于该外绝缘材料34的长度。在本实施例中，该中心绝缘材料31的材质为高分子聚合物，其与该外绝缘材料34相同。
在图1中，该半导体元件1更包括一第二介电层35。该第二介电层35位于该基板本体11的该第二表面112上，且具有一开口351以显露该导电孔20及该外绝缘材料34。该第二介电层35的材质可以是聚亚酰胺(PI)或聚丙烯(PP)。该第二重布层39邻近于该基板本体11的该第二表面112，且电性连接至该导电孔20。在本实施例中，该第二重布层39包括一第二金属层38及一第二晶种层36。该第二晶种层36的材质为氮化钽(Tantalum Nitride)或钨化钽(Tantalum Tungsten)，且该第二金属层38的材质为铜。然而，该第二晶种层36可以被省略；亦即，该第二金属层38可以直接位于该第二介电层35上。该第二重布层39位于该第二介电层35上，且接触位于该第二介电层35的开口351内的导电孔20。
在图1中，该保护层40覆盖该第二重布层39及该第二介电层35，且具有开口401以显露该第二重布层39的一部分。该保护层40的材质与该第二介电层35的材质相同。该球下金属层(UBM)44位于该保护层40的该开口401中，且位于该第二重布层39上，以电性连接该第二重布层39。在本实施例中，该球下金属层(UBM)44更延伸至该保护层40的顶面。该球下金属层(UBM)44包括一第三金属层43及一第三晶种层41。该第三金属层43为单层或多层结构，且该第三晶种层41的材质为氮化钽(Tantalum Nitride)。然而，该第三晶种层41可以被省略；亦即，该第三金属层43可以接触该第二重布层39。该焊球45位于该球下金属层(UBM)44上。
参考图2至图16，显示本发明该半导体元件1的制造方法的一实施例的示意图。
参考图2，提供一基板10。该基板10具有一基板本体11、一第一介电层13及一焊垫12。在本实施例中，该基板本体11的材质为硅。然而，在其他实施例中，该基板本体11的材质可以是玻璃。该基板本体11具有一第一表面111及一第二表面112，且该焊垫12邻近于该基板本体11的第一表面111。在本实施例中，该第一介电层13位于该基板本体11的该第一表面111上，且具有一第一开口131。该第一介电层13覆盖该焊垫12，除了该第一开口131显露该焊垫12的一部份。该第一介电层13的材质可以是聚亚酰胺(PI)或聚丙烯(PP)。要注意的是，如果在起始步骤中仅提供该基板本体11，则该方法更包括形成该第一介电层13及该焊垫12的步骤。
参考图3，形成一第一晶种层21于该第一介电层13及其第一开口131上。该第一晶种层21接触位于该第一开口131中的焊垫12。接着，形成一光阻层22于该第一晶种层21上，该光阻层22具有一开口221以显露该第一晶种层21的一部分。接着，形成一第一金属层23于该光阻层22的开口221中。该第一金属层23的材质为铜，且该第一晶种层21的材质为氮化钽(Tantalum Nitride)或钨化钽(Tantalum Tungsten)。
参考图4，移除该光阻层22。接着，移除未被该第一金属层23覆盖的第一晶种层21的一部分以形成该第一重布层24。该第一重布层24邻近于该基板本体11的该第一表面111，且电性连接至该焊垫12。在本实施例中，该第一重布层24位于该第一介电层13上，且接触位于该第一介电层13第一开口131内的焊垫12。
参考图5，利用一黏胶层25将该基板10附着至一载体26，其中该基板本体11的该第一表面111面对该载体26。接着，从该基板本体11的该第二表面112薄化该基板本体11。
参考图6，形成一光阻层27于该基板本体11的该第二表面112上，该光阻层27具有一开口271以显露该第二表面112的一部分。接着，根据该光阻层27的开口271从该基板本体11的该第二表面112形成一孔洞28。该孔洞28贯穿该基板本体11及该第一介电层13，使得该第一介电层13具有一第二开口132。亦即，该第二开口132为该孔洞28的一部份，且贯穿该第一介电层13。因此，该第一重布层24的一部分被该孔洞28所显露。要注意的是，该孔洞28的位置并不对应该焊垫12。
参考图7，形成一互连晶种层29于该孔洞28中，其中该互连晶种层29接触该第一重布层24。接着，形成一互连金属30于该互连晶种层29上。在本实施例中，该互连金属30为杯状且定义出一中心槽301。
参考图8，将一中心绝缘材料31填满该中心槽301。因此，一导电孔20形成于该孔洞28中，且更延伸至该第一介电层13的该第二开口132内以接触该第一重布层24。在其他实施例中，该互连金属30可以是一实心柱，且该中心绝缘材料31可以被省略。
参考图9，形成一光阻层32于该基板本体11的该第二表面112上，该光阻层32具有一开口321以显露该导电孔20。接着，根据该开口321从该基板本体11的该第二表面112形成一圆形槽33，其中该圆形槽33环绕该导电孔20。在本实施例中，该圆形槽33仅贯穿该基板本体11以形成该通孔113。
参考图10，形成一外绝缘材料34于该圆形槽33中以环绕该互连金属30及该互连晶种层29。较佳地，该中心绝缘材料31的材质为高分子聚合物，其与该外绝缘材料34相同。在本实施例中，该外绝缘材料34并未延伸至该第一介电层13中；因此，该导电孔20的底面并未和该外绝缘材料34的底面共平面。
参考图11，形成一第二介电层35于该基板本体11的该第二表面112上，该第二介电层35且具有一开口351以显露该导电孔20及该外绝缘材料34。该第二介电层35的材质可以是聚亚酰胺(PI)或聚丙烯(PP)。接着，形成一第二晶种层36于该第二介电层35及其开口351上。该第二晶种层36接触位于该开口351内的导电孔20。
参考图12，形成一光阻层37于该第二晶种层36上，该光阻层37具有一开口371以显露该第二晶种层36的一部分。接着，形成一第二金属层38于该光阻层37的开口371中。该第二金属层38的材质为铜，且该第二晶种层36的材质为氮化钽(TantalumNitride)或钨化钽(Tantalum Tungsten)。
参考图13，移除该光阻层37。接着，移除未被该第二金属层38覆盖的第二晶种层36的一部分以形成一第二重布层39。在本实施例中，该第二重布层39位于该第二介电层35上，且接触位于该第二介电层35的开口351内的导电孔20。
参考图14，形成一保护层40于该第二介电层35及该第二重布层39上，该保护层40具有开口401以显露该第二重布层39的一部分。该保护层40的材质与该第二介电层35的材质可以相同。接着，形成一第三晶种层41于该保护层40及其开口401。该第三晶种层41的材质为氮化钽(Tantalum Nitride)或钨化钽(Tantalum Tungsten)。
参考图15，形成一光阻层42于该第三晶种层41上，该光阻层42具有一开口421以显露该第三晶种层41的一部分。接着，形成一第三金属层43于该光阻层42的开口421中。该第三金属层43为单层或多层结构。
参考图16，移除该光阻层42。接着，移除未被该第三金属层43覆盖的第三晶种层41的部分以形成一球下金属层(UBM)44。接着，形成一焊球45于该球下金属层(UBM)44上，且移除该载体26及该黏胶层25，以制得该半导体元件1。
在本实施例中，如果晶圆厂所提供的该基板10具有各种不良的电路，例如，该焊垫12的尺寸太小，该焊垫12具有太多层，或者该焊垫12位于不符需求的位置，该焊垫12仍可经由该第一重布层24及该导电孔20电性连接至该基板本体11的该第二表面112。
参考图17，显示本发明的另一实施例的半导体元件2的剖视示意图。本实施例的半导体元件2与图1所示的半导体元件1大致相同，其中相同元件赋予相同的编号。本实施例的半导体元件2与图1所示的半导体元件1的不同处在于该第一介电层13的第二开口132a内的结构不同。在本实施例中，该第一重布层24具有一第一部份241及一第二部份242。该第一重布层24的第一部份241位于该第一介电层13的第一开口131内，且包含该第一金属层23的一第一部份231及该第一晶种层21的一第一部份211。该第一重布层24的第二部份242位于该第一介电层13的第二开口132a内，且包含该第一金属层23的一第二部份232及该第一晶种层21的一第二部份212。该第一重布层24的第一部份241接触该焊垫12，且该导电孔20接触该第一重布层24的第二部份242。
在图17中，该导电孔20并未延伸至该第一介电层13内。因此，该导电孔20的底面和该外绝缘材料34的底面实质上共平面，且该导电孔20的长度等于该外绝缘材料34的长度。较佳地，该第一介电层13的第二开口132a的尺寸略大于该导电孔20的尺寸，使得该第一重布层24的第二部份242的尺寸略大于该导电孔20的尺寸，以确保其彼此间的电性连接。
参考图18至图20，显示本发明该半导体元件2的制造方法的另一实施例的示意图。本实施例的方法与图2至16所示的方法大致相同，其不同处如下所示。
参考图18，提供一基板10。该基板10具有一基板本体11、一第一介电层13及一焊垫12。在本实施例中，该基板本体11的材质为硅。然而，在其他实施例中，该基板本体11的材质可以是玻璃。该基板本体11具有一第一表面111及一第二表面112。该第一介电层13位于该基板本体11的该第一表面111上，且具有一第一开口131及一第二开口132a。该第一介电层13覆盖该焊垫12，且该第一开口131显露该焊垫12的一部份。该第二开口132a显露该基板本体11的该第一表面111的一部份。要注意的是，如果在此起始步骤所提供的该基板10不具有该第二开口132a，则该方法更包括形成该第二开口132a的步骤。
参考图19，形成一第一晶种层21于该第一介电层13及其第一开口131及第二开口132a上。该第一晶种层21具有一位于该第一开口131内的第一部份211，及一位于该第二开口132a内的第二部份212。该第一晶种层21的第一部份211接触该焊垫12，且该第一晶种层21的第二部份212接触该基板本体11。接着，形成一光阻层22于该第一晶种层21上，该光阻层22具有一开口221以显露该第一晶种层21的一部分。接着，形成一第一金属层23于该光阻层22的开口221中。该第一金属层23的材质为铜，且该第一晶种层21的材质为氮化钽(Tantalum Nitride)或钨化钽(TantalumTungsten)。该第一金属层23具有一位于该第一开口131内的第一部份231，及一位于该第二开口132a内的第二部份232。
参考图20，移除该光阻层22。接着，移除未被该第一金属层23覆盖的第一晶种层21的部分以形成该第一重布层24。该第一重布层24具有该第一部份241及该第二部份242。该第一重布层24的第一部份241位于该第一介电层13的第一开口131内，且包含该第一金属层23的一第一部份231及该第一晶种层21的一第一部份211。该第一重布层24的第二部份242位于该第一介电层13的第二开口132a内，且包含该第一金属层23的一第二部份232及该第一晶种层21的一第二部份212。该第一重布层24的第一部份241接触该焊垫12。
在图20中，利用一黏胶层25将该基板10附着至一载体26。接着，从该基板本体11的该第二表面112薄化该基板本体11。接着，根据该光阻层27的开口271从该基板本体11的该第二表面112形成一孔洞28。在本实施例中，该孔洞28仅贯穿该基板本体11，以显露该第一重布层24的第二部分242。
参考图17，形成该导电孔20于该孔洞28中以接触该第一重布层24的第二部分242。接着，形成一外绝缘材料34、一第二介电层35、一第二重布层39、一保护层40、一球下金属层(UBM)44及一焊球45于该基板本体11的该第二表面112，如图9至16所示，以制得该半导体元件2。
惟上述实施例仅为说明本发明的原理及其功效，而非用以限制本发明。因此，习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如权利要求书所列。

Claims (10)

1.一种半导体元件，其特征在于，包括
一基板，具有一焊垫及一介电层，该介电层位于该基板的一第一表面上，该介电层具有一显露该焊垫的第一开口；
一第一重布层，邻近于该基板的该第一表面，且电性连接至该焊垫；及
一导电孔，形成于该基板中，该导电孔包含一互连晶种层及一互连层，该互连晶种层位于该基板上，该互连层具有一位于该互连晶种层的一内表面上的外表面，且电性连接至该第一重布层，其中该介电层更具有一对应该导电孔的第二开口，该互连晶种层的底部接触该第一重布层，且该导电孔与该第一重布层间具有一界面。
2.如权利要求1的半导体元件，其特征在于，更包括一第二重布层，邻近于该基板的一第二表面，且电性连接至该互连层。
3.如权利要求1的半导体元件，其特征在于，该导电孔延伸至该介电层的该第二开口内。
4.如权利要求1的半导体元件，其特征在于，该第一重布层的一部分延伸至该介电层的该第二开口内。
5.如权利要求1的半导体元件，其特征在于，更包括：
一第二重布层，邻近于该基板的一第二表面，且电性连接至该互连层；
一球下金属层，位于该第二重布层上；及
一焊球，位于该球下金属层上。
6.如权利要求1的半导体元件，其特征在于，更包括一第二介电层，位于该基板的一第二表面上，该第二介电层具有一开口以显露该导电孔。
7.一种半导体元件，其特征在于，包括
一基板，具有一焊垫及一介电层，该介电层位于该基板的一第一表面上，该介电层具有一显露该焊垫的第一开口；
一第一重布层，邻近于该基板的该第一表面，且电性连接至该焊垫；及
一导电孔，形成于该基板中，该导电孔包含一互连晶种层，该互连晶种层位于该基板上，且电性连接至该第一重布层，该互连晶种层的底部接触该第一重布层，且该导电孔与该第一重布层间具有一界面。
8.如权利要求7的半导体元件，其特征在于，该介电层更具有一对应该导电孔的第二开口。
9.如权利要求8的半导体元件，其特征在于，该第一重布层的一部分延伸至该介电层的该第二开口内。
10.如权利要求7的半导体元件，其特征在于，更包括一第二介电层，位于该基板的一第二表面上。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023010601A1 (zh) * 2021-08-05 2023-02-09 长鑫存储技术有限公司 一种半导体结构及其制造方法

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9258907B2 (en) 2012-08-09 2016-02-09 Lockheed Martin Corporation Conformal 3D non-planar multi-layer circuitry
US8937387B2 (en) * 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
WO2014071813A1 (zh) 2012-11-08 2014-05-15 南通富士通微电子股份有限公司 半导体器件的封装件和封装方法
US9548282B2 (en) * 2012-11-08 2017-01-17 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device
CN102915986B (zh) 2012-11-08 2015-04-01 南通富士通微电子股份有限公司 芯片封装结构
TWI517328B (zh) * 2013-03-07 2016-01-11 矽品精密工業股份有限公司 半導體裝置
US9196587B2 (en) * 2013-03-14 2015-11-24 Maxim Integrated Products, Inc. Semiconductor device having a die and through substrate-via
CN104934391B (zh) * 2014-03-18 2018-05-18 日月光半导体制造股份有限公司 半导体装置和半导体工艺
TWI560837B (en) * 2014-03-24 2016-12-01 E Ink Holdings Inc Contact window structure, pixel structure and method for manufacturing thereof
US9418877B2 (en) * 2014-05-05 2016-08-16 Qualcomm Incorporated Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US10123410B2 (en) * 2014-10-10 2018-11-06 Lockheed Martin Corporation Fine line 3D non-planar conforming circuit
US9478512B2 (en) * 2015-02-11 2016-10-25 Dawning Leading Technology Inc. Semiconductor packaging structure having stacked seed layers
US11037802B2 (en) * 2016-12-28 2021-06-15 Intel Corporation Package substrate having copper alloy sputter seed layer and high density interconnects
US20180342473A1 (en) * 2017-05-25 2018-11-29 Advanced Semiconductor Engineering, Inc. Via structure, substrate structure including the same, and method for manufacturing the same
US10304765B2 (en) * 2017-06-08 2019-05-28 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US10687419B2 (en) * 2017-06-13 2020-06-16 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
CN107611042B (zh) * 2017-08-24 2021-09-21 通富微电子股份有限公司 一种扇出型封装方法
CN107527823A (zh) * 2017-08-24 2017-12-29 通富微电子股份有限公司 一种封装基板的制备方法及封装基板
CN107516638A (zh) * 2017-08-24 2017-12-26 通富微电子股份有限公司 一种扇出型封装方法
CN107564880A (zh) * 2017-08-24 2018-01-09 通富微电子股份有限公司 一种扇出型封装器件
CN107611043A (zh) * 2017-08-24 2018-01-19 通富微电子股份有限公司 一种扇出型封装方法
CN107481940A (zh) * 2017-08-24 2017-12-15 通富微电子股份有限公司 一种封装基板的制备方法及封装基板
US11716819B2 (en) * 2018-06-21 2023-08-01 Averatek Corporation Asymmetrical electrolytic plating for a conductive pattern
US10483201B1 (en) * 2018-10-26 2019-11-19 Nanya Technology Corporation Semiconductor structure and method for manufacturing the same
US11581289B2 (en) * 2019-07-30 2023-02-14 Stmicroelectronics Pte Ltd Multi-chip package
US11300727B2 (en) * 2019-07-31 2022-04-12 Advanced Semiconductor Engineering, Inc. Optical communication package structure and method for manufacturing the same
GB2587374B (en) * 2019-09-25 2022-08-17 X Fab Semiconductor Foundries Gmbh Through silicon via and redistribution layer
US20230125383A1 (en) * 2019-11-27 2023-04-27 Boe Technology Group Co., Ltd. Driving substrate and method for manufacturing the same, light-emitting substrate and display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101131947A (zh) * 2006-08-25 2008-02-27 日月光半导体制造股份有限公司 立体式封装结构及其制造方法
US20080251871A1 (en) * 2007-04-12 2008-10-16 Micron Technology, Inc. Semiconductor fabrication method and system
US20100140752A1 (en) * 2008-12-10 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Compliant Polymer Layer Between UBM and Conformal Dielectric Layer/RDL for Stress Relief
CN102136430A (zh) * 2010-01-27 2011-07-27 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
CN102263086A (zh) * 2010-05-28 2011-11-30 日月光半导体制造股份有限公司 半导体封装结构

Family Cites Families (130)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761782A (en) 1971-05-19 1973-09-25 Signetics Corp Semiconductor structure, assembly and method
US4499655A (en) 1981-03-18 1985-02-19 General Electric Company Method for making alignment-enhancing feed-through conductors for stackable silicon-on-sapphire
US4394712A (en) 1981-03-18 1983-07-19 General Electric Company Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers
US4807021A (en) 1986-03-10 1989-02-21 Kabushiki Kaisha Toshiba Semiconductor device having stacking structure
US4897708A (en) 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
US4842699A (en) 1988-05-10 1989-06-27 Avantek, Inc. Method of selective via-hole and heat sink plating using a metal mask
US5191405A (en) 1988-12-23 1993-03-02 Matsushita Electric Industrial Co., Ltd. Three-dimensional stacked lsi
US5160779A (en) 1989-11-30 1992-11-03 Hoya Corporation Microprobe provided circuit substrate and method for producing the same
US5166097A (en) 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5239448A (en) 1991-10-28 1993-08-24 International Business Machines Corporation Formulation of multichip modules
US5386627A (en) 1992-09-29 1995-02-07 International Business Machines Corporation Method of fabricating a multi-layer integrated circuit chip interposer
US5643831A (en) 1994-01-20 1997-07-01 Fujitsu Limited Process for forming solder balls on a plate having apertures using solder paste and transferring the solder balls to semiconductor device
AU3415095A (en) 1994-09-06 1996-03-27 Sheldahl, Inc. Printed circuit substrate having unpackaged integrated circuit chips directly mounted thereto and method of manufacture
US6962829B2 (en) 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP4255161B2 (ja) 1998-04-10 2009-04-15 株式会社野田スクリーン 半田バンプ形成装置
JP3447961B2 (ja) 1998-08-26 2003-09-16 富士通株式会社 半導体装置の製造方法及び半導体製造装置
US20020017855A1 (en) 1998-10-01 2002-02-14 Complete Substrate Solutions Limited Visual display
US6295730B1 (en) 1999-09-02 2001-10-02 Micron Technology, Inc. Method and apparatus for forming metal contacts on a substrate
US6329631B1 (en) 1999-09-07 2001-12-11 Ray Yueh Solder strip exclusively for semiconductor packaging
TW434854B (en) 1999-11-09 2001-05-16 Advanced Semiconductor Eng Manufacturing method for stacked chip package
TW569424B (en) 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
JP4023076B2 (ja) 2000-07-27 2007-12-19 富士通株式会社 表裏導通基板及びその製造方法
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6406934B1 (en) 2000-09-05 2002-06-18 Amkor Technology, Inc. Wafer level production of chip size semiconductor packages
US6448506B1 (en) 2000-12-28 2002-09-10 Amkor Technology, Inc. Semiconductor package and circuit board for making the package
US6740950B2 (en) 2001-01-15 2004-05-25 Amkor Technology, Inc. Optical device packages having improved conductor efficiency, optical coupling and thermal transfer
JP4113679B2 (ja) 2001-02-14 2008-07-09 イビデン株式会社 三次元実装パッケージの製造方法
JP2002270718A (ja) 2001-03-07 2002-09-20 Seiko Epson Corp 配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
JP4092890B2 (ja) 2001-05-31 2008-05-28 株式会社日立製作所 マルチチップモジュール
JP2002373957A (ja) 2001-06-14 2002-12-26 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US7334326B1 (en) 2001-06-19 2008-02-26 Amkor Technology, Inc. Method for making an integrated circuit substrate having embedded passive components
JP3875867B2 (ja) 2001-10-15 2007-01-31 新光電気工業株式会社 シリコン基板の穴形成方法
JP3904484B2 (ja) 2002-06-19 2007-04-11 新光電気工業株式会社 シリコン基板のスルーホールプラギング方法
US7057269B2 (en) 2002-10-08 2006-06-06 Chippac, Inc. Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package
US7098117B2 (en) 2002-10-18 2006-08-29 The Regents Of The University Of Michigan Method of fabricating a package with substantially vertical feedthroughs for micromachined or MEMS devices
JP2004228135A (ja) 2003-01-20 2004-08-12 Mitsubishi Electric Corp 微細孔への金属埋め込み方法
JP2004273563A (ja) 2003-03-05 2004-09-30 Shinko Electric Ind Co Ltd 基板の製造方法及び基板
US6908856B2 (en) 2003-04-03 2005-06-21 Interuniversitair Microelektronica Centrum (Imec) Method for producing electrical through hole interconnects and devices made thereof
US20050048772A1 (en) * 2003-09-02 2005-03-03 Applied Materials, Inc. Bond pad techniques for integrated circuits
US7224056B2 (en) 2003-09-26 2007-05-29 Tessera, Inc. Back-face and edge interconnects for lidded package
US7101792B2 (en) 2003-10-09 2006-09-05 Micron Technology, Inc. Methods of plating via interconnects
US7276787B2 (en) 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
EP1720794A2 (en) 2004-03-01 2006-11-15 Tessera, Inc. Packaged acoustic and electromagnetic transducer chips
TWI232571B (en) * 2004-04-09 2005-05-11 Advanced Semiconductor Eng Wafer structure and method for forming a redistribution layer therein
US7358174B2 (en) * 2004-04-13 2008-04-15 Amkor Technology, Inc. Methods of forming solder bumps on exposed metal pads
US20050258545A1 (en) 2004-05-24 2005-11-24 Chippac, Inc. Multiple die package with adhesive/spacer structure and insulated die surface
US7608534B2 (en) 2004-06-02 2009-10-27 Analog Devices, Inc. Interconnection of through-wafer vias using bridge structures
JP4271625B2 (ja) 2004-06-30 2009-06-03 株式会社フジクラ 半導体パッケージ及びその製造方法
JP4343044B2 (ja) 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
US7204737B2 (en) 2004-09-23 2007-04-17 Temic Automotive Of North America, Inc. Hermetically sealed microdevice with getter shield
TWI242869B (en) 2004-10-15 2005-11-01 Advanced Semiconductor Eng High density substrate for multi-chip package
TWI254425B (en) 2004-10-26 2006-05-01 Advanced Semiconductor Eng Chip package structure, chip packaging process, chip carrier and manufacturing process thereof
JP4369348B2 (ja) 2004-11-08 2009-11-18 新光電気工業株式会社 基板及びその製造方法
JP3987521B2 (ja) 2004-11-08 2007-10-10 新光電気工業株式会社 基板の製造方法
JP2006173557A (ja) 2004-11-22 2006-06-29 Toshiba Corp 中空型半導体装置とその製造方法
KR100687069B1 (ko) 2005-01-07 2007-02-27 삼성전자주식회사 보호판이 부착된 이미지 센서 칩과 그의 제조 방법
TWI264807B (en) 2005-03-02 2006-10-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TWI244186B (en) 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
US7285434B2 (en) 2005-03-09 2007-10-23 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same
TWI261325B (en) 2005-03-25 2006-09-01 Advanced Semiconductor Eng Package structure of semiconductor and wafer-level formation thereof
US7989958B2 (en) 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7767493B2 (en) 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
JP2007027451A (ja) 2005-07-19 2007-02-01 Shinko Electric Ind Co Ltd 回路基板及びその製造方法
JP4889974B2 (ja) 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
JP4716819B2 (ja) 2005-08-22 2011-07-06 新光電気工業株式会社 インターポーザの製造方法
US7488680B2 (en) 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers
KR100621438B1 (ko) * 2005-08-31 2006-09-08 삼성전자주식회사 감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법
US7772116B2 (en) 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
TWI311356B (en) 2006-01-02 2009-06-21 Advanced Semiconductor Eng Package structure and fabricating method thereof
TWI303105B (en) 2006-01-11 2008-11-11 Advanced Semiconductor Eng Wafer level package for image sensor components and its fabricating method
TWI287273B (en) 2006-01-25 2007-09-21 Advanced Semiconductor Eng Three dimensional package and method of making the same
TWI293499B (en) 2006-01-25 2008-02-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
TWI287274B (en) 2006-01-25 2007-09-21 Advanced Semiconductor Eng Three dimensional package and method of making the same
US7304859B2 (en) 2006-03-30 2007-12-04 Stats Chippac Ltd. Chip carrier and fabrication method
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US7446424B2 (en) 2006-07-19 2008-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for semiconductor package
JP5026038B2 (ja) 2006-09-22 2012-09-12 新光電気工業株式会社 電子部品装置
TWI315295B (en) 2006-12-29 2009-10-01 Advanced Semiconductor Eng Mems microphone module and method thereof
US7598163B2 (en) 2007-02-15 2009-10-06 John Callahan Post-seed deposition process
TW200839903A (en) 2007-03-21 2008-10-01 Advanced Semiconductor Eng Method for manufacturing electrical connections in wafer
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
TWI335654B (en) 2007-05-04 2011-01-01 Advanced Semiconductor Eng Package for reducing stress
US7553752B2 (en) 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
TWI335059B (en) 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
TWI387019B (zh) 2007-08-02 2013-02-21 Advanced Semiconductor Eng 在基材上形成穿導孔之方法
TWI357118B (en) 2007-08-02 2012-01-21 Advanced Semiconductor Eng Method for forming vias in a substrate
TWI344694B (en) 2007-08-06 2011-07-01 Siliconware Precision Industries Co Ltd Sensor-type package and method for fabricating the same
TWI345296B (en) 2007-08-07 2011-07-11 Advanced Semiconductor Eng Package having a self-aligned die and the method for making the same, and a stacked package and the method for making the same
JP5536322B2 (ja) 2007-10-09 2014-07-02 新光電気工業株式会社 基板の製造方法
US7691747B2 (en) 2007-11-29 2010-04-06 STATS ChipPAC, Ltd Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
TWI365483B (en) 2007-12-04 2012-06-01 Advanced Semiconductor Eng Method for forming a via in a substrate
US7838395B2 (en) 2007-12-06 2010-11-23 Stats Chippac, Ltd. Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same
US7851246B2 (en) 2007-12-27 2010-12-14 Stats Chippac, Ltd. Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device
US8072079B2 (en) 2008-03-27 2011-12-06 Stats Chippac, Ltd. Through hole vias at saw streets including protrusions or recesses for interconnection
US7666711B2 (en) 2008-05-27 2010-02-23 Stats Chippac, Ltd. Semiconductor device and method of forming double-sided through vias in saw streets
US7741156B2 (en) 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
TWI420640B (zh) 2008-05-28 2013-12-21 矽品精密工業股份有限公司 半導體封裝裝置、半導體封裝結構及其製法
US8101460B2 (en) 2008-06-04 2012-01-24 Stats Chippac, Ltd. Semiconductor device and method of shielding semiconductor die from inter-device interference
US7851893B2 (en) 2008-06-10 2010-12-14 Stats Chippac, Ltd. Semiconductor device and method of connecting a shielding layer to ground through conductive vias
US7863721B2 (en) 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
TWI365528B (en) 2008-06-27 2012-06-01 Advanced Semiconductor Eng Semiconductor structure and method for manufacturing the same
TWI453877B (zh) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
US8183087B2 (en) 2008-09-09 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component
US9559046B2 (en) 2008-09-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-in package-on-package structure using through silicon vias
US7772081B2 (en) 2008-09-17 2010-08-10 Stats Chippac, Ltd. Semiconductor device and method of forming high-frequency circuit structure and method thereof
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US7741148B1 (en) 2008-12-10 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support
US8283250B2 (en) 2008-12-10 2012-10-09 Stats Chippac, Ltd. Semiconductor device and method of forming a conductive via-in-via structure
US8900921B2 (en) 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
US7786008B2 (en) 2008-12-12 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof
US7839163B2 (en) 2009-01-22 2010-11-23 International Business Machines Corporation Programmable through silicon via
US7816945B2 (en) 2009-01-22 2010-10-19 International Business Machines Corporation 3D chip-stack with fuse-type through silicon via
TWI387084B (zh) 2009-01-23 2013-02-21 Advanced Semiconductor Eng 具有穿導孔之基板及具有穿導孔之基板之封裝結構
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
TWI470766B (zh) 2009-03-10 2015-01-21 Advanced Semiconductor Eng 晶片結構、晶圓結構以及晶片製程
TWI380421B (en) 2009-03-13 2012-12-21 Advanced Semiconductor Eng Method for making silicon wafer having through via
TW201034150A (en) 2009-03-13 2010-09-16 Advanced Semiconductor Eng Silicon wafer having interconnection metal
TWI394253B (zh) 2009-03-25 2013-04-21 Advanced Semiconductor Eng 具有凸塊之晶片及具有凸塊之晶片之封裝結構
US8329578B2 (en) 2009-03-27 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure and via etching process of forming the same
US8227288B2 (en) 2009-03-30 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Image sensor and method of fabricating same
TWI394221B (zh) 2009-04-30 2013-04-21 Advanced Semiconductor Eng 具有測試銲墊之矽晶圓及其測試方法
US20100327465A1 (en) 2009-06-25 2010-12-30 Advanced Semiconductor Engineering, Inc. Package process and package structure
US8471156B2 (en) 2009-08-28 2013-06-25 Advanced Semiconductor Engineering, Inc. Method for forming a via in a substrate and substrate with a via
TWI406380B (zh) 2009-09-23 2013-08-21 Advanced Semiconductor Eng 具有穿導孔之半導體元件及其製造方法及具有穿導孔之半導體元件之封裝結構
TWI431739B (zh) * 2010-09-23 2014-03-21 矽品精密工業股份有限公司 具有重佈線路層之晶片結構及其製法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101131947A (zh) * 2006-08-25 2008-02-27 日月光半导体制造股份有限公司 立体式封装结构及其制造方法
US20080251871A1 (en) * 2007-04-12 2008-10-16 Micron Technology, Inc. Semiconductor fabrication method and system
US20100140752A1 (en) * 2008-12-10 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Compliant Polymer Layer Between UBM and Conformal Dielectric Layer/RDL for Stress Relief
CN102136430A (zh) * 2010-01-27 2011-07-27 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
CN102263086A (zh) * 2010-05-28 2011-11-30 日月光半导体制造股份有限公司 半导体封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023010601A1 (zh) * 2021-08-05 2023-02-09 长鑫存储技术有限公司 一种半导体结构及其制造方法

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