TWI499021B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI499021B
TWI499021B TW102100177A TW102100177A TWI499021B TW I499021 B TWI499021 B TW I499021B TW 102100177 A TW102100177 A TW 102100177A TW 102100177 A TW102100177 A TW 102100177A TW I499021 B TWI499021 B TW I499021B
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layer
substrate
opening
redistribution
dielectric layer
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TW201334136A (zh
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Chih Jing Hsu
Ying Te Ou
Chieh Chen Fu
Che Hau Huang
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Advanced Semiconductor Eng
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Description

半導體元件及其製造方法
本發明係關於一種半導體封裝，特別的是，係關於三維(3D)半導體封裝。
習知半導體元件之製造方法之起始步驟中，晶圓廠所提供的基板可能具有各種不良的特性。舉例而言，銲墊的尺寸可能太小，或者其可能具有太多不同電路、金屬層及介電層而阻礙導電孔(Conductive Vias)形成於該基板中。特言之，要進行後鑽孔(Via Last)製程以從該晶圓背面蝕刻貫穿該基板以到達該原始銲墊是有困難的。
本揭露之一方面係關於一種半導體元件。在一實施例中，該半導體元件包括一基板，具有一銲墊；一第一重佈層，鄰近於該基板之一第一表面，且電性連接至該銲墊；及一導電孔，形成於該基板中。該導電孔包含一環狀晶種層及一互連層，該環狀晶種層位於該基板上，該互連層具有一位於該晶種層之一內表面上之外表面，且電性連接至該第一重佈層。該基板具有一介電層，位於該基板之該第一表面上，該介電層具有一顯露該銲墊之第一開口及一對應該導電孔之第二開口。該導電孔延伸至該介電層之該第二開口內。在一實施例中，該第一重佈層之一部分延伸至該介電層之該第二開口內。該半導體元件更包括一第二重佈層，鄰近於該基板之一第二表面，且電性連接至該導電 孔。此外，該半導體元件包括一球下金屬層(Under Bump Metallurgy，簡稱UBM)，位於該第二重佈層上；及一銲球，位於該球下金屬層(Under Bump Metallurgy，簡稱UBM)上。
本揭露之另一方面係關於一種製造方法。在一實施例中，一種半導體元件之製造方法包括提供一基板，該基板具有一銲墊；形成一第一重佈層鄰近於該基板之一第一表面，其中該第一重佈層電性連接至該銲墊；將該基板附著至一載體上；及形成一導電孔於該基板中，該導電孔電性連接至該第一重佈層。該基板具有一介電層，位於該基板之該第一表面上，且該第一介電層具有一顯露該銲墊之第一開口。該方法更包括形成一第二重佈層鄰近於該基板之一第二表面，其中該第二重佈層電性連接至該導電孔。
參考圖1，顯示本發明之一實施例之半導體元件1之剖視示意圖。該半導體元件1包括一基板10、一第一重佈層24、一第二重佈層39、一保護層40、一球下金屬層(Under Bump Metallurgy，簡稱UBM)44及一銲球45。
如圖1所示，該基板10具有一基板本體11(包含一導電孔20形成於其內)、一銲墊12及一第一介電層13。在本實施例中，該基板本體11之材質係為矽。然而，在其他實施例中，該基板本體11之材質可以是玻璃。該基板本體11具有一第一表面111、一第二表面112及一通孔113。該銲墊12係鄰近於該基板本體11之第一表面111。在本實施例中， 該第一介電層13位於該基板本體11之該第一表面111上，且具有一第一開口131及一第二開口132。該第一介電層13覆蓋該銲墊12，除了該第一開口131顯露該銲墊12之一部份。該第二開口132之位置係對應該導電孔20之位置。該第一介電層13之材質可以是聚亞醯胺(PI)或聚丙烯(PP)。
在圖1中，該第一重佈層24鄰近於該基板本體11之該第一表面111，且電性連接至該銲墊12。在本實施例中，該第一重佈層24包括一第一晶種層21及一第一金屬層23。該第一晶種層21之材質係為氮化鉭(Tantalum Nitride)或鎢化鉭(Tantalum Tungsten)，且該第一金屬層23之材質係為銅。然而，該第一晶種層21可以被省略；亦即，該第一金屬層23可以直接位於該第一介電層13上。該第一重佈層24係位於該第一介電層13上，且接觸位於該第一介電層13第一開口131內之銲墊12。
在圖1中，該導電孔20係位於該基板本體11之該通孔113中，且接觸該第一重佈層24。在本實施例中，該導電孔20更延伸至該第一介電層13之該第二開口132內。該導電孔20包含一中心絕緣材料31及一互連金屬30。在本實施例中，該互連金屬30係為杯狀且定義出一中心槽，且該中心絕緣材料31係位於該中心槽中。可以理解的是，該互連金屬30可以是一實心柱(因此該中心絕緣材料31可以被省略)。較佳地，該導電孔20更具有一互連晶種層29，其環繞該互連金屬30，且該互連晶種層29之底部接觸該第一重佈層24。在本實施例中，該基板10更具有一外絕緣材料 34，位於該通孔113中且環繞該互連金屬30及該互連晶種層29。如圖1所示，該外絕緣材料34並未延伸至該第一介電層13之該第二開口132中；因此，該導電孔20之底面並未和該外絕緣材料34之底面共平面，且該導電孔20之長度係大於該外絕緣材料34之長度。在本實施例中，該中心絕緣材料31之材質係為高分子聚合物，其與該外絕緣材料34相同。
在圖1中，該半導體元件1更包括一第二介電層35。該第二介電層35位於該基板本體11之該第二表面112上，且具有一開口351以顯露該導電孔20及該外絕緣材料34。該第二介電層35之材質可以是聚亞醯胺(PI)或聚丙烯(PP)。該第二重佈層39鄰近於該基板本體11之該第二表面112，且電性連接至該導電孔20。在本實施例中，該第二重佈層39包括一第二金屬層38及一第二晶種層36。該第二晶種層36之材質係為氮化鉭(Tantalum Nitride)或鎢化鉭(Tantalum Tungsten)，且該第二金屬層38之材質係為銅。然而，該第二晶種層36可以被省略；亦即，該第二金屬層38可以直接位於該第二介電層35上。該第二重佈層39係位於該第二介電層35上，且接觸位於該第二介電層35之開口351內之導電孔20。
在圖1中，該保護層40覆蓋該第二重佈層39及該第二介電層35，且具有開口401以顯露該第二重佈層39之一部分。該保護層40之材質與該第二介電層35之材質相同。該球下金屬層(UBM)44位於該保護層40之該開口401中，且 位於該第二重佈層39上，以電性連接該第二重佈層39。在本實施例中，該球下金屬層(UBM)44更延伸至該保護層40之頂面。該球下金屬層(UBM)44包括一第三金屬層43及一第三晶種層41。該第三金屬層43係為單層或多層結構，且該第三晶種層41之材質係為氮化鉭(Tantalum Nitride)。然而，該第三晶種層41可以被省略；亦即，該第三金屬層43可以接觸該第二重佈層39。該銲球45係位於該球下金屬層(UBM)44上。
參考圖2至圖16，顯示本發明該半導體元件1之製造方法之一實施例之示意圖。
參考圖2，提供一基板10。該基板10具有一基板本體11、一第一介電層13及一銲墊12。在本實施例中，該基板本體11之材質係為矽。然而，在其他實施例中，該基板本體11之材質可以是玻璃。該基板本體11具有一第一表面111及一第二表面112，且該銲墊12係鄰近於該基板本體11之第一表面111。在本實施例中，該第一介電層13位於該基板本體11之該第一表面111上，且具有一第一開口131。該第一介電層13覆蓋該銲墊12，除了該第一開口131顯露該銲墊12之一部份。該第一介電層13之材質可以是聚亞醯胺(PI)或聚丙烯(PP)。要注意的是，如果在起始步驟中僅提供該基板本體11，則該方法更包括形成該第一介電層13及該銲墊12之步驟。
參考圖3，形成一第一晶種層21於該第一介電層13及其第一開口131上。該第一晶種層21接觸位於該第一開口131 中之銲墊12。接著，形成一光阻層22於該第一晶種層21上，該光阻層22具有一開口221以顯露該第一晶種層21之一部分。接著，形成一第一金屬層23於該光阻層22之開口221中。該第一金屬層23之材質係為銅，且該第一晶種層21之材質係為氮化鉭(Tantalum Nitride)或鎢化鉭(Tantalum Tungsten)。
參考圖4，移除該光阻層22。接著，移除未被該第一金屬層23覆蓋之第一晶種層21之一部分以形成該第一重佈層24。該第一重佈層24鄰近於該基板本體11之該第一表面111，且電性連接至該銲墊12。在本實施例中，該第一重佈層24係位於該第一介電層13上，且接觸位於該第一介電層13第一開口131內之銲墊12。
參考圖5，利用一黏膠層25將該基板10附著至一載體26，其中該基板本體11之該第一表面111面對該載體26。接著，從該基板本體11之該第二表面112薄化該基板本體11。
參考圖6，形成一光阻層27於該基板本體11之該第二表面112上，該光阻層27具有一開口271以顯露該第二表面112之一部分。接著，根據該光阻層27之開口271從該基板本體11之該第二表面112形成一孔洞28。該孔洞28貫穿該基板本體11及該第一介電層13，使得該第一介電層13具有一第二開口132。亦即，該第二開口132係為該孔洞28的一部份，且貫穿該第一介電層13。因此，該第一重佈層24之一部分係被該孔洞28所顯露。要注意的是，該孔洞28之位 置並不對應該銲墊12。
參考圖7，形成一互連晶種層29於該孔洞28中，其中該互連晶種層29接觸該第一重佈層24。接著，形成一互連金屬30於該互連晶種層29上。在本實施例中，該互連金屬30係為杯狀且定義出一中心槽301。
參考圖8，將一中心絕緣材料31填滿該中心槽301。因此，一導電孔20係形成於該孔洞28中，且更延伸至該第一介電層13之該第二開口132內以接觸該第一重佈層24。在其他實施例中，該互連金屬30可以是一實心柱，且該中心絕緣材料31可以被省略。
參考圖9，形成一光阻層32於該基板本體11之該第二表面112上，該光阻層32具有一開口321以顯露該導電孔20。接著，根據該開口321從該基板本體11之該第二表面112形成一圓形槽33，其中該圓形槽33環繞該導電孔20。在本實施例中，該圓形槽33僅貫穿該基板本體11以形成該通孔113。
參考圖10，形成一外絕緣材料34於該圓形槽33中以環繞該互連金屬30及該互連晶種層29。較佳地，該中心絕緣材料31之材質係為高分子聚合物，其與該外絕緣材料34相同。在本實施例中，該外絕緣材料34並未延伸至該第一介電層13中；因此，該導電孔20之底面並未和該外絕緣材料34之底面共平面。
參考圖11，形成一第二介電層35於該基板本體11之該第二表面112上，該第二介電層35且具有一開口351以顯露該 導電孔20及該外絕緣材料34。該第二介電層35之材質可以是聚亞醯胺(PI)或聚丙烯(PP)。接著，形成一第二晶種層36於該第二介電層35及其開口351上。該第二晶種層36接觸位於該開口351內之導電孔20。
參考圖12，形成一光阻層37於該第二晶種層36上，該光阻層37具有一開口371以顯露該第二晶種層36之一部分。接著，形成一第二金屬層38於該光阻層37之開口371中。該第二金屬層38之材質係為銅，且該第二晶種層36之材質係為氮化鉭(Tantalum Nitride)或鎢化鉭(Tantalum Tungsten)。
參考圖13，移除該光阻層37。接著，移除未被該第二金屬層38覆蓋之第二晶種層36之一部分以形成一第二重佈層39。在本實施例中，該第二重佈層39係位於該第二介電層35上，且接觸位於該第二介電層35之開口351內之導電孔20。
參考圖14，形成一保護層40於該第二介電層35及該第二重佈層39上，該保護層40具有開口401以顯露該第二重佈層39之一部分。該保護層40之材質與該第二介電層35之材質可以相同。接著，形成一第三晶種層41於該保護層40及其開口401。該第三晶種層41之材質係為氮化鉭(Tantalum Nitride)或鎢化鉭(Tantalum Tungsten)。
參考圖15，形成一光阻層42於該第三晶種層41上，該光阻層42具有一開口421以顯露該第三晶種層41之一部分。接著，形成一第三金屬層43於該光阻層42之開口421中。 該第三金屬層43係為單層或多層結構。
參考圖16，移除該光阻層42。接著，移除未被該第三金屬層43覆蓋之第三晶種層41之部分以形成一球下金屬層(UBM)44。接著，形成一銲球45於該球下金屬層(UBM)44上，且移除該載體26及該黏膠層25，以製得該半導體元件1。
在本實施例中，如果晶圓廠所提供的該基板10具有各種不良的電路，例如，該銲墊12的尺寸太小，該銲墊12具有太多層，或者該銲墊12位於不符需求的位置，該銲墊12仍可經由該第一重佈層24及該導電孔20電性連接至該基板本體11之該第二表面112。
參考圖17，顯示本發明之另一實施例之半導體元件2之剖視示意圖。本實施例之半導體元件2與圖1所示之半導體元件1大致相同，其中相同元件賦予相同之編號。本實施例之半導體元件2與圖1所示之半導體元件1之不同處在於該第一介電層13之第二開口132a內之結構不同。在本實施例中，該第一重佈層24具有一第一部份241及一第二部份242。該第一重佈層24之第一部份241係位於該第一介電層13之第一開口131內，且包含該第一金屬層23之一第一部份231及該第一晶種層21之一第一部份211。該第一重佈層24之第二部份242係位於該第一介電層13之第二開口132a內，且包含該第一金屬層23之一第二部份232及該第一晶種層21之一第二部份212。該第一重佈層24之第一部份241接觸該銲墊12，且該導電孔20接觸該第一重佈層24之第二 部份242。
在圖17中，該導電孔20並未延伸至該第一介電層13內。因此，該導電孔20之底面和該外絕緣材料34之底面實質上共平面，且該導電孔20之長度係等於該外絕緣材料34之長度。較佳地，該第一介電層13之第二開口132a之尺寸略大於該導電孔20之尺寸，使得該第一重佈層24之第二部份242之尺寸略大於該導電孔20之尺寸，以確保其彼此間之電性連接。
參考圖18至圖20，顯示本發明該半導體元件2之製造方法之另一實施例之示意圖。本實施例之方法與圖2至16所示之方法大致相同，其不同處如下所示。
參考圖18，提供一基板10。該基板10具有一基板本體11、一第一介電層13及一銲墊12。在本實施例中，該基板本體11之材質係為矽。然而，在其他實施例中，該基板本體11之材質可以是玻璃。該基板本體11具有一第一表面111及一第二表面112。該第一介電層13位於該基板本體11之該第一表面111上，且具有一第一開口131及一第二開口132a。該第一介電層13覆蓋該銲墊12，且該第一開口131顯露該銲墊12之一部份。該第二開口132a顯露該基板本體11之該第一表面111之一部份。要注意的是，如果在此起始步驟所提供之該基板10不具有該第二開口132a，則該方法更包括形成該第二開口132a之步驟。
參考圖19，形成一第一晶種層21於該第一介電層13及其第一開口131及第二開口132a上。該第一晶種層21具有一 位於該第一開口131內之第一部份211，及一位於該第二開口132a內之第二部份212。該第一晶種層21之第一部份211接觸該銲墊12，且該第一晶種層21之第二部份212接觸該基板本體11。接著，形成一光阻層22於該第一晶種層21上，該光阻層22具有一開口221以顯露該第一晶種層21之一部分。接著，形成一第一金屬層23於該光阻層22之開口221中。該第一金屬層23之材質係為銅，且該第一晶種層21之材質係為氮化鉭(Tantalum Nitride)或鎢化鉭(Tantalum Tungsten)。該第一金屬層23具有一位於該第一開口131內之第一部份231，及一位於該第二開口132a內之第二部份232。
參考圖20，移除該光阻層22。接著，移除未被該第一金屬層23覆蓋之第一晶種層21之部分以形成該第一重佈層24。該第一重佈層24具有該第一部份241及該第二部份242。該第一重佈層24之第一部份241係位於該第一介電層13之第一開口131內，且包含該第一金屬層23之一第一部份231及該第一晶種層21之一第一部份211。該第一重佈層24之第二部份242係位於該第一介電層13之第二開口132a內，且包含該第一金屬層23之一第二部份232及該第一晶種層21之一第二部份212。該第一重佈層24之第一部份241接觸該銲墊12。
在圖20中，利用一黏膠層25將該基板10附著至一載體26。接著，從該基板本體11之該第二表面112薄化該基板本體11。接著，根據該光阻層27之開口271從該基板本體 11之該第二表面112形成一孔洞28。在本實施例中，該孔洞28僅貫穿該基板本體11，以顯露該第一重佈層24之第二部分242。
參考圖17，形成該導電孔20於該孔洞28中以接觸該第一重佈層24之第二部分242。接著，形成一外絕緣材料34、一第二介電層35、一第二重佈層39、一保護層40、一球下金屬層(UBM)44及一銲球45於該基板本體11之該第二表面112，如圖9至16所示，以製得該半導體元件2。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1‧‧‧本發明之一實施例之半導體元件
2‧‧‧本發明之另一實施例之半導體元件
10‧‧‧基板
11‧‧‧基板本體
12‧‧‧銲墊
13‧‧‧第一介電層
20‧‧‧導電孔
21‧‧‧第一晶種層
22‧‧‧光阻層
23‧‧‧第一金屬層
24‧‧‧第一重佈層
25‧‧‧黏膠層
26‧‧‧載體
27‧‧‧光阻層
28‧‧‧孔洞
29‧‧‧互連晶種層
30‧‧‧互連金屬
31‧‧‧中心絕緣材料
32‧‧‧光阻層
33‧‧‧圓形槽
34‧‧‧外絕緣材料
35‧‧‧第二介電層
36‧‧‧第二晶種層
37‧‧‧光阻層
38‧‧‧第二金屬層
39‧‧‧第二重佈層
40‧‧‧保護層
41‧‧‧第三晶種層
42‧‧‧光阻層
43‧‧‧第三金屬層
44‧‧‧球下金屬層(UBM)
45‧‧‧銲球
111‧‧‧基板本體之第一表面
112‧‧‧基板本體之第二表面
113‧‧‧通孔
131‧‧‧第一開口
132‧‧‧第二開口
132a‧‧‧第二開口
211‧‧‧第一晶種層之第一部份
212‧‧‧第一晶種層之第二部份
221‧‧‧光阻層之開口
231‧‧‧第一金屬層之第一部份
232‧‧‧第一金屬層之第二部份
241‧‧‧第一重佈層之第一部份
242‧‧‧第一重佈層之第二部份
271‧‧‧光阻層之開口
301‧‧‧中心槽
321‧‧‧光阻層之開口
351‧‧‧第二介電層之開口
371‧‧‧光阻層之開口
401‧‧‧保護層之開口
421‧‧‧光阻層之開口
圖1顯示本發明之一實施例之半導體元件之剖視示意圖；圖2至圖16顯示本發明圖1之該半導體元件之製造方法之一實施例之示意圖；圖17顯示本發明之另一實施例之半導體元件之剖視示意圖；及圖18至圖20顯示本發明圖17之該半導體元件之製造方法之另一實施例之示意圖。
1‧‧‧本發明之一實施例之半導體元件
10‧‧‧基板
11‧‧‧基板本體
12‧‧‧銲墊
13‧‧‧第一介電層
20‧‧‧導電孔
21‧‧‧第一晶種層
23‧‧‧第一金屬層
24‧‧‧第一重佈層
29‧‧‧互連晶種層
30‧‧‧互連金屬
31‧‧‧中心絕緣材料
34‧‧‧外絕緣材料
35‧‧‧第二介電層
36‧‧‧第二晶種層
38‧‧‧第二金屬層
39‧‧‧第二重佈層
40‧‧‧保護層
41‧‧‧第三晶種層
43‧‧‧第三金屬層
44‧‧‧球下金屬層(UBM)
45‧‧‧銲球
111‧‧‧基板本體之第一表面
112‧‧‧基板本體之第二表面
113‧‧‧通孔
131‧‧‧第一開口
132‧‧‧第二開口
351‧‧‧第二介電層之開口
401‧‧‧保護層之開口

Claims (16)

  1. 一種半導體元件，包括：一基板，具有一銲墊；一第一重佈層，鄰近於該基板之一第一表面，且電性連接至該銲墊；一導電孔，形成於該基板中，該導電孔包含一環狀晶種層及一互連層，該環狀晶種層位於該基板上，該互連層具有一位於該環狀晶種層之一內表面上之外表面，且電性連接至該第一重佈層；其中該基板更具有一介電層，位於該基板之該第一表面上，該介電層具有一顯露該銲墊之第一開口；及其中該介電層更具有一對應該導電孔之第二開口。
  2. 如請求項1之半導體元件，更包括一第二重佈層，鄰近於該基板之一第二表面，且電性連接至該互連層。
  3. 如請求項1之半導體元件，其中該導電孔延伸至該介電層之該第二開口內。
  4. 如請求項1之半導體元件，其中該第一重佈層之一部分延伸至該介電層之該第二開口內。
  5. 如請求項1之半導體元件，更包括：一第二重佈層，鄰近於該基板之一第二表面，且電性連接至該互連層；一球下金屬層(UBM)，位於該第二重佈層上；及一銲球，位於該球下金屬層(UBM)上。
  6. 如請求項1之半導體元件，更包括一第二介電層，位於 該基板之一第二表面上，該第二介電層具有一開口以顯露該導電孔。
  7. 一種半導體元件，包括：一基板，具有一銲墊；一第一重佈層，鄰近於該基板之一第一表面，且電性連接至該銲墊；一導電孔，形成於該基板中，該導電孔包含一環狀晶種層及一環狀互連層，該環狀晶種層具有一位於該基板上之外表面，該環狀互連層具有一位於該環狀晶種層之一內表面上之外表面，以及一位於一絕緣層之一外表面上之內表面，該環狀互連層電性連接至該第一重佈層；一第二重佈層，鄰近於該基板之一第二表面，且電性連接至該環狀互連層；及一介電層，位於該基板之該第一表面上，該介電層具有一顯露該銲墊之第一開口，以及一對應該基板中之導電孔之第二開口，其中該第一開口及該第二開口係位於不同位置。
  8. 如請求項7之半導體元件，其中該導電孔延伸至該介電層之該第二開口內。
  9. 如請求項7之半導體元件，其中該第一重佈層之一部分延伸至該介電層之該第二開口內。
  10. 如請求項7之半導體元件，更包括：一球下金屬層(UBM)，位於該第二重佈層上；及一銲球，位於該球下金屬層(UBM)上。
  11. 如請求項7之半導體元件，更包括一第二介電層，位於該基板之一第二表面上。
  12. 如請求項11之半導體元件，其中該第二介電層具有一開口以顯露該導電孔。
  13. 如請求項7之半導體元件，其中該基板之材質係為矽或玻璃。
  14. 一種半導體元件之製造方法，包括提供一基板，該基板具有一銲墊；形成一第一重佈層鄰近於該基板之一第一表面，其中該第一重佈層電性連接至該銲墊；將該基板附著至一載體上；及形成一導電孔於該基板中，該導電孔包含一環狀晶種層及一互連層，該環狀晶種層位於該基板上，該互連層具有一位於該環狀晶種層之一內表面上之外表面，且電性連接至該第一重佈層，其中該基板更具有一第一介電層，位於該基板之該第一表面上，該第一介電層具有一顯露該銲墊之第一開口，及其中該第一介電層更具有一對應該導電孔之第二開口，其中該第一開口及該第二開口係位於不同位置。
  15. 如請求項14之方法，更包括：形成一第二重佈層鄰近於該基板之一第二表面，其中該第二重佈層電性連接至該導電孔。
  16. 如請求項14之方法，其中形成該第一重佈層之步驟包括： 形成一第一晶種層於該第一介電層上，其中該第一晶種層接觸位於該第一開口中之銲墊，且接觸位於該第二開口中之基板；形成一光阻層於該第一晶種層上，其中該光阻層具有一開口以顯露該第一晶種層之一部分；形成一第一金屬層於該光阻層之開口中；移除該光阻層；及移除未被該第一金屬層覆蓋之第一晶種層以形成該第一重佈層。
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US20130207260A1 (en) 2013-08-15
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