WO2014071815A1 - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

Info

Publication number
WO2014071815A1
WO2014071815A1 PCT/CN2013/086214 CN2013086214W WO2014071815A1 WO 2014071815 A1 WO2014071815 A1 WO 2014071815A1 CN 2013086214 W CN2013086214 W CN 2013086214W WO 2014071815 A1 WO2014071815 A1 WO 2014071815A1
Authority
WO
WIPO (PCT)
Prior art keywords
columnar electrode
layer
insulating layer
groove
opening
Prior art date
Application number
PCT/CN2013/086214
Other languages
English (en)
French (fr)
Inventor
林仲珉
石磊
陶玉娟
Original Assignee
南通富士通微电子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201210444471.2A external-priority patent/CN102915982B/zh
Priority claimed from CN201210444474.6A external-priority patent/CN102931099B/zh
Application filed by 南通富士通微电子股份有限公司 filed Critical 南通富士通微电子股份有限公司
Priority to US14/440,872 priority Critical patent/US9548282B2/en
Publication of WO2014071815A1 publication Critical patent/WO2014071815A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H01L2224/03472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13011—Shape comprising apertures or cavities, e.g. hollow bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13015—Shape in top view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Definitions

  • the present invention relates to the field of semiconductor packaging, and more particularly to a semiconductor device capable of improving the bonding force between a solder ball and a columnar electrode and a method of forming the same.
  • Chip Scale Package is the latest generation of chip packaging technology.
  • CSP packaged products have the advantages of small size, good electrical performance and good thermal performance.
  • the wafer-level CSP (WCSP) is packaged on a wafer and tested in the form of a wafer, aged and screened, and then the wafer is divided into a single CSP circuit.
  • a semiconductor device of a wafer level CSP structure is disclosed in Chinese Patent Publication No. CN1630029A.
  • the invention includes: a semiconductor substrate 11 having a pad 12 thereon; and a surface of the semiconductor substrate 11 a passivation layer 14 having an opening exposing the surface of the pad 12; a rewiring layer 16 on the surface of the portion of the passivation layer 14 and the opening, the rewiring layer 16 being connected to the pad 12; a columnar electrode 17 on the surface of the rewiring layer 16 outside the opening; an insulating layer 20 covering the surface of the rewiring layer 16 and a portion of the passivation layer 14, the surface of the insulating layer 20 being flush with the surface of the columnar electrode 17; 17 surface solder balls 21.
  • solder balls in the conventional semiconductor device are easily detached from the surface of the columnar electrode.
  • the problem to be solved by the present invention is to provide a semiconductor device and a method of forming the same, which improves the bonding force between the solder ball and the columnar electrode.
  • the present invention provides a semiconductor device including: a semiconductor substrate having a plurality of pads; a columnar electrode on the pad, the columnar electrode including a body and a location a recess in the body, the opening of the recess coincides with a top surface of the columnar electrode; a solder ball on the columnar electrode, the solder ball including a metal bump on a top of the columnar electrode and filling the recess Filling section.
  • the number of the grooves is one, and the radius of the groove is 1% to 99% of the radius of the column electrode body.
  • the number of the grooves is greater than one, and the grooves are independently distributed in the body.
  • the grooves have a straight line distribution, a matrix distribution, a concentric circle distribution, a concentric circle distribution, a polygon distribution, a plurality of rays or an irregular distribution in the body.
  • the semiconductor substrate has a passivation layer
  • the passivation layer has a first opening therein, the first opening exposes all or part of the surface of the pad, the sidewall of the first opening and the outer side of the columnar electrode The walls are in contact.
  • the passivation layer has a first insulating layer, the surface of the first insulating layer is flush with the top surface of the columnar electrode, and the first insulating layer covers the sidewall of the columnar electrode.
  • the passivation layer has a first insulating layer, a surface of the first insulating layer is lower than a top surface of the columnar electrode, and a first annular etching recess is formed between the first insulating layer and the outer sidewall of the columnar electrode.
  • the groove, the first annular etched groove exposes a portion of the surface of the passivation layer.
  • the solder ball further includes a skirt portion on an outer side wall of the columnar electrode body, the upper portion of the skirt portion is connected to the metal tab, and the lower portion of the skirt portion is partially opposite to the passivation layer on both sides of the columnar electrode.
  • a skirt portion on an outer side wall of the columnar electrode body, the upper portion of the skirt portion is connected to the metal tab, and the lower portion of the skirt portion is partially opposite to the passivation layer on both sides of the columnar electrode.
  • the semiconductor substrate has a passivation layer thereon, the passivation layer has a first opening exposing all or part of the surface of the pad, a rewiring layer on the partial passivation layer, and the rewiring layer is filled The first opening, the rewiring layer is a part of the pad, and the columnar electrode is located on the rewiring layer outside the first opening.
  • the method further includes: a second insulating layer on the passivation layer and the rewiring layer, the surface of the second insulating layer being flush with the top surface of the body of the columnar electrode.
  • the method further includes: a second insulating layer on the passivation layer, a surface of the second insulating layer is lower than a top surface of the body of the columnar electrode, and a second ring is formed between the body of the second insulating layer and the columnar electrode
  • the recess is etched, and the second annular etched recess exposes a portion of the surface of the rewiring layer.
  • the solder ball further includes a skirt portion on an outer side wall of the columnar electrode body, the upper portion of the skirt portion is connected to the metal tab, and the lower portion of the skirt portion and a portion of the re-wiring layer on both sides of the columnar electrode Connected and in contact with the sidewall of the second annular etched groove, the width of the lower portion of the skirt portion is greater than the width of the upper portion, and the surface of the lower portion of the skirt portion is lower than the surface of the first insulating layer or The surface of the first insulating layer is flush or higher than the surface of the first insulating layer.
  • the solder ball has a metal barrier layer between the solder ball and the body.
  • the present invention also provides a method of forming a semiconductor device, comprising: providing a semiconductor substrate having a plurality of pads; forming a passivation layer on the semiconductor substrate, the passivation layer having Exposing a first opening of the pad surface; forming a columnar electrode on the pad, the columnar electrode comprising a body and a groove in the body, the opening of the groove coincides with a top surface of the columnar electrode; A solder ball is formed on the columnar electrode, and the solder ball includes a metal bump on a top of the columnar electrode and a filling portion filling the groove.
  • the number of the grooves is one, and the radius of the groove is 1% to 99% of the radius of the column electrode body.
  • the number of the grooves is greater than one, and the grooves are independently distributed in the body.
  • the grooves are linearly distributed, matrix distributed, concentric circle distribution, concentric circle distribution, polygonal distribution or irregular distribution in the body.
  • the columnar electrode is formed by: forming a seed layer on a sidewall and a bottom of the first opening and a surface of the passivation layer; forming a first photoresist on a surface of the seed layer a layer, the first photoresist layer has a second opening corresponding to the first opening; filling the first opening and the second opening with a full metal by an electroplating process to form a body of the columnar electrode; removing the first a photoresist layer; removing a portion of the seed layer on the passivation layer by using the columnar electrode as a mask; forming a first insulating layer on the passivation layer; forming a second photoresist on the surface of the first insulating layer a layer, the second photoresist layer has at least one third opening exposing a surface of the columnar electrode body; a body of the columnar electrode having a partial thickness is etched away along the third opening, and at least one groove is formed in the body, The body and the groove constitute a
  • the surface of the first insulating layer is flush with the top surface of the body of the columnar electrode, and the first insulating layer is in contact with the outer sidewall of the columnar electrode.
  • the second photoresist layer is removed; the printing mesh plate or the stainless steel plate is placed on the surface of the first insulating layer, and the printed mesh plate or the stainless steel plate has an exposed place a body and a through hole of the columnar electrode and a fourth opening of the annular etching groove; using a screen printing process at the Filling the four openings and the recesses with a solder paste; removing the printed screen or the stainless steel sheet, performing a reflow process on the solder paste, forming a metal bump on the top of the body of the columnar electrode, and forming a filling portion in the recess
  • the metal tab and the filling portion form a groove.
  • the surface of the first insulating layer is lower than the top surface of the body of the columnar electrode, and the first insulating layer and the outer sidewall of the body have a first annular etched groove, and the first annular etched groove The surface of a portion of the passivation layer is exposed.
  • the second photoresist layer is removed; and the printing mesh plate or the stainless steel plate is placed on the surface of the first insulating layer, the printed mesh plate or the stainless steel plate has an exposed column shape a top surface of the electrode body and a recess in the body and a fifth opening of the first annular etch recess; filling the fifth opening, the recess and the first annular etch recess with a solder paste by a screen printing process; Removing the printing stencil or stainless steel plate, performing a reflow process on the solder paste, forming a metal bump on the top of the body of the columnar electrode, forming a filling portion in the groove, and forming a skirt portion on the outer side wall of the body The upper portion of the skirt portion is coupled to the metal tab, and the lower portion of the skirt portion is connected to a portion of the passivation layer on both sides of the columnar electrode and is in contact with the sidewall of the first annular etched groove,
  • a metal barrier layer is further formed between the solder ball and the body of the columnar electrode.
  • the columnar electrode in the semiconductor device includes a body and a groove in the body, the opening of the groove coincides with a top surface of the columnar electrode, the column electrode has a solder ball thereon, and the solder ball includes a metal on the top of the column electrode a bump and a filling portion filled with the groove, the solder ball and the column electrode form a plug-like structure, and the solder ball and the column electrode are changed into a multi-plane contact by the existing single plane contact, and the solder ball is not only combined with the column electrode
  • the top surface is in contact with, and is in contact with the inside of the columnar electrode, the contact area of the solder ball with the columnar electrode is increased, and the bonding force of the two is enhanced, so that the solder ball receives an acceptable external force (the force that causes the solder ball to separate from the columnar electrode) Greatly enhanced, the solder balls are not easily detached from the columnar electrodes, and the grooves are only located in the body so that the bonding force between the bottom of the
  • the number of grooves in the body is one, and the radius of the groove is the radius of the column electrode body 1% ⁇ 99%, the number of the corresponding filling portions is one, and the radius of the filling portion is 1% to 99% of the radius of the column electrode body, so that the contact plane between the filling portion and the body is increased, and the contact area is larger.
  • the sidewall of the body maintains a certain mechanical strength, which is beneficial to improve the bonding force between the solder ball and the columnar electrode, so that the acceptable external force of the solder ball (the force for separating the solder ball from the columnar electrode) is greatly enhanced.
  • the solder balls are not easily peeled off from the columnar electrodes.
  • the grooves are independently distributed in the body, and the grooves are linearly distributed in the body, matrix distribution, concentric circle distribution, concentric ring distribution, polygonal distribution, several rays or irregularities.
  • Distribution, the number and position of the filling portions correspond to the number and position of the grooves, so that the number of faces of the solder balls in contact with the columnar electrodes is further increased, and the contact area is further increased, thereby making the solder balls and the columnar electrodes
  • the bonding force between the two is further increased, and the filling portion is regularly distributed in the body, so that the bonding force of the solder ball and the columnar electrode at each moment is evenly distributed.
  • the solder ball further includes a skirt portion "L" type skirt portion on the outer side wall of the body of the columnar electrode, the solder ball being in contact with the top surface of the body and the inner side wall of the groove in the body, and the body
  • the contact of the outer side walls further increases the number of contact faces of the solder balls and the columnar electrodes and the contact area.
  • the depth of the groove formed in the body is 0.5% to 99.9% of the height of the body, so that the filling portion in the groove penetrates to a certain depth in the body, and the bonding force of the solder ball and the pin structure formed by the column electrode is stronger.
  • the width of the groove is gradually reduced.
  • voids bubbles
  • FIG. 1 is a schematic structural view of a semiconductor device of a prior art wafer level structure
  • FIGS. 2 to 4 are schematic structural views of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a method of forming a semiconductor device according to a first embodiment of the present invention
  • FIG. 6 to FIG. 14 are schematic cross-sectional views showing a process of forming a semiconductor device according to a first embodiment of the present invention
  • FIG. 15 is a schematic structural view of a semiconductor device according to a second embodiment of the present invention.
  • 16 is a flow chart showing a method of forming a semiconductor device according to a second embodiment of the present invention.
  • FIG. 17 to FIG. 24 are schematic cross-sectional views showing a process of forming a semiconductor device according to a second embodiment of the present invention.
  • Figure 25 is a schematic structural view of a semiconductor device according to a third embodiment of the present invention.
  • Figure 26 is a block diagram showing the structure of a semiconductor device in accordance with a fourth embodiment of the present invention.
  • the solder ball is only in contact with the upper surface of the columnar electrode, the contact area between the two is small, and the bonding force between the solder ball and the columnar electrode is poor, and when subjected to an external force, The solder ball is easily detached from the surface of the columnar electrode or cracks are formed on the contact surface of the solder ball and the columnar electrode, which is disadvantageous for the subsequent packaging process, and the packaged device is easily broken.
  • a columnar electrode includes a body and a recess in the body, the opening of the recess coincides with a top surface of the columnar electrode, and the columnar electrode has a solder a ball, the solder ball includes a metal bump on a top of the columnar electrode and a filling portion filled with the groove, the solder ball and the column electrode form a plug-like structure, and the solder ball and the column electrode are from an existing single plane
  • the contact becomes a multi-plane contact, and the solder ball not only contacts the top surface of the columnar electrode but also contacts the inside of the columnar electrode, and the contact area between the solder ball and the columnar electrode increases, and the bonding force of the two is enhanced, so that the solder ball is subjected to
  • the external force (the force that causes the solder ball to disengage from the columnar electrode) is greatly enhanced, the solder ball is not easily detached from the columnar electrode, and the groove is only located in the body
  • FIGS. 3 and 4 are top views of the cross-sectional view of FIG. 2 along the cutting line AB, and the metal barrier layer is not shown in FIGS. 3 and 4. show.
  • the semiconductor device includes: a semiconductor substrate 200, a plurality of pads 201 on the semiconductor substrate 200, in this embodiment, a pad as an example; a passivation layer 202 on the semiconductor substrate 200,
  • the passivation layer 202 has a first opening exposing all or part of the surface of the pad 201; a columnar electrode on the exposed opening 201 of the first opening, the columnar electrode
  • the solder ball 217 on the column electrode the solder ball 217 has a top surface of the column electrode body 207 a metal bump 216 on the upper portion and a filling portion 215 filling the recess;
  • the recess in the body 207 is filled with solder to form a filling portion 215 of the solder ball 217.
  • the shape and position of the groove in the body 207 corresponds to the shape and position of the filling portion 215 of the solder ball 217, and the depth of the groove is the body.
  • the height of the filling portion is 0.5% to 99.5%, so that the filling portion in the groove penetrates into a certain depth in the body 207, and the bonding force of the solder ball 217 and the plug structure formed by the columnar electrode is stronger, and the groove does not penetrate the body 207 of the columnar electrode, so that the groove does not penetrate the body 207 of the columnar electrode.
  • the contact surface of the bottom of the body 207 of the columnar electrode with the pad 201 (or the seed layer 203) is a contact between the body material and the pad material, and does not affect the bottom between the body 207 and the pad 201 (or the seed layer 203). Binding force.
  • the width of the groove is gradually reduced.
  • no void (bubble) is generated in the groove, and the reliability between the solder ball 217 and the column electrode is improved.
  • the width of the corresponding filling portion 215 also gradually decreases.
  • the number of the grooves in the body 207 is one, the radius of the groove is 1% to 99% of the radius of the column electrode body, and the number of the corresponding filling portions 215 is 1.
  • the radius of the filling portion 215 is 1% to 99% of the radius of the columnar electrode body, so that the contact portion of the filling portion 215 and the body 207 is increased, and the contact area is large, so that the side wall of the body 207 maintains a certain mechanical mechanism.
  • the strength is beneficial to improve the bonding force between the solder ball 217 and the columnar electrode, so that the acceptable external force of the solder ball (the force for separating the solder ball from the columnar electrode) is greatly enhanced, and the solder ball is not easily peeled off from the columnar electrode.
  • the metal barrier layer is not shown in FIG. 3.
  • the body 207 of the columnar electrode has a filling portion 215, and the center of the filling portion coincides with the center of the columnar electrode, so that the filling portion 215 and the columnar shape
  • the bonding force of the electrodes in all directions is kept uniform, and the cross-sectional shape of the outer side wall of the filling portion 215 is a circle, a polygon, a regular polygon or other regular or irregular patterns, and the outer side wall of the body may also be It is a cross-sectional shape of a circular cross section, a polygon, a regular polygon, or other regular or irregular pattern.
  • the grooves when the number of the grooves is greater than one, the grooves are independently distributed in the body 207, and the grooves are linearly distributed in the body 207, matrix distribution, concentric circle distribution, concentric circles a ring distribution, a polygon distribution, a plurality of rays or an irregular distribution, the number and position of the filling portions 215 correspond to the number and position of the grooves, and when the number of the filling portions 215 is greater than one, the filling portion 215 is in the body 207. Independently distributed, the filling portion 215 has a straight line distribution, a matrix distribution, a concentric circle distribution, a concentric ring distribution, a polygonal distribution, or an irregular distribution in the body 207.
  • the linear distribution includes: a single straight line distribution passing through the center of the body 207, a multi-linear distribution through the center of the body, a multi-line distribution through the center of the body, and a parallel straight line distribution; the polygon distribution includes a regular polygon distribution and a non-normal polygon distributed.
  • the metal barrier layer is not shown in FIG. 3.
  • four filling portions 215 are exemplified, and the four filling portions 215 are distributed in a rectangular shape in the body.
  • the number of the filling portions 215 is larger than one, the number of faces in which the solder balls 217 are in contact with the columnar electrodes is further increased, and the contact area is further increased, so that the bonding force between the solder balls 217 and the columnar electrodes is further increased.
  • the filling portion 215 is regularly distributed in the body such that the bonding force of the solder ball and the columnar electrode is uniform at each moment. It should be noted that the above various distribution modes refer to a pattern formed by the center lines of the respective grooves (or the respective filling portions).
  • FIG. 5 is a schematic flow chart of a method for forming the above semiconductor device, including: Step S20, providing a semiconductor substrate, the semiconductor substrate having a plurality of pads;
  • Step S21 forming a passivation layer on the semiconductor substrate, the passivation layer having a first opening exposing a surface of the pad;
  • Step S22 forming a seed layer on the sidewalls and the bottom of the first opening and the surface of the passivation layer;
  • Step S23 forming a first photoresist layer on the surface of the seed layer, the first photoresist layer having a second opening corresponding to the first opening;
  • Step S24 filling the first opening and the second opening with a full metal by using an electroplating process to form a body of the columnar electrode;
  • Step S25 removing the first photoresist layer; removing a part of the seed layer on the passivation layer by using the columnar electrode as a mask;
  • Step S26 forming a first insulating layer on the passivation layer, a surface of the first insulating layer is flush with a top surface of the body of the columnar electrode, and the first insulating layer is in contact with an outer side wall of the columnar electrode;
  • Step S27 forming a second photoresist layer on the surface of the first insulating layer, the second photoresist layer Having at least one third opening exposing a surface of the columnar electrode body, etching a portion of the columnar electrode having a partial thickness along the third opening, forming at least one groove in the body, the body and the groove forming a columnar electrode;
  • Step S28 removing the second photoresist layer; placing a printing screen or a stainless steel plate on the surface of the first insulating layer, the printing screen or the stainless steel plate having a body and a through hole exposing the columnar electrode and an annular engraving a fourth opening of the etched groove;
  • Step S29 filling the fourth opening and the groove with a solder paste by using a screen printing process; removing the printing mesh plate or the stainless steel plate, performing a reflow process on the solder paste, and forming a metal on the top of the column electrode body
  • the protrusion forms a filling portion in the groove, and the metal bump and the filling portion constitute a solder ball.
  • FIGS. 6 to 14 are schematic cross-sectional views showing a process of forming a semiconductor device according to a first embodiment of the present invention, and the above-described forming steps will be described in detail below with reference to Figs. 6 to 14 .
  • a semiconductor substrate 200 is provided.
  • the semiconductor substrate 200 has a plurality of pads 201.
  • a passivation layer 202 is formed on the semiconductor substrate 200.
  • the passivation layer 202 has a surface exposing the surface of the pad 201.
  • An opening 204; a seed layer 203 is formed on the sidewalls and the bottom of the first opening 204 and the surface of the passivation layer 202.
  • the semiconductor substrate 200 has a plurality of chips (not shown) connected to the corresponding chips.
  • the pad 201 is made of a material such as aluminum, copper, gold or silver, and the pad 201 may be located on the surface of the semiconductor substrate 200 or in the semiconductor substrate 200. Only one pad is shown as an example in this embodiment.
  • the passivation layer 202 is used to protect a chip formed on the semiconductor substrate 200.
  • the material of the passivation layer 202 is silicon nitride, borosilicate glass, phosphosilicate glass or borophosphosilicate glass or polyimide. Wait.
  • the first opening 204 formed in the passivation layer 202 exposes all or part of the surface of the pad 201.
  • the passivation layer 202 is a stacked structure of one or more layers.
  • the seed layer 203 serves as a power supply layer when the columnar electrode body is formed by subsequent plating. Seed layer
  • the seed layer 203 is a stacked structure of a chrome metal layer or a titanium metal layer or a bismuth metal layer single layer structure, or a chrome metal layer or a titanium metal layer or a bismuth metal layer and a copper metal layer or a gold metal layer or a silver metal layer,
  • the seed layer 203 is formed by a sputtering process, and the seed layer 203 can also serve as a diffusion barrier layer to prevent diffusion of metal in the subsequently formed columnar electrode into the first insulating layer 202 and to strengthen the columnar electrode metal and the first The adhesion of an insulating layer 202.
  • the first openings mentioned later refer to the remaining openings after the seed layer 203 is formed.
  • a first photoresist layer 205 is formed on the surface of the seed layer 203, and the first photoresist layer 205 has a second opening 206 corresponding to the first opening 204.
  • the first opening 204 and the second opening 206 are filled with metal to form a body 207 of the columnar electrode.
  • the formation process of the second opening 206 is an exposure and development process, and the width of the two openings 206 is equal to the width of the first opening 204.
  • the width of the second opening 206 may also be greater than the width of the first opening 204, and then the electroplating process is used to form the body of the columnar electrode.
  • the body portion of the columnar electrode is placed on the surface of the seed layer 203 on the insulating layer 202.
  • the metal filled in the first opening 204 and the second opening 206 is copper, and the metal filling process is an electroplating process.
  • the first photoresist layer 205 is removed (refer to FIG. 8); a portion of the seed layer 203 on the passivation layer 202 is removed by using the columnar electrode 207 as a mask.
  • the process of the partial seed layer 203 is a dry etching process or a wet etching process.
  • the surface of the body 207 of the columnar electrode may form a mask layer.
  • the exposed seed layer is also partially located on the surface of the passivation layer, and a surface of the body and a portion of the seed layer is further formed with a mask layer when the seed layer is etched.
  • a first insulating layer 208 is formed on the surface of the passivation layer 202.
  • the surface of the first insulating layer 208 is flush with the top surface of the body 207 of the columnar electrode, and the first insulating layer 208 and the columnar shape The outer side walls of the body 207 of the electrodes are in contact.
  • the first insulating layer 208 serves as an electrical isolation layer and a sealing material layer, and the material of the first insulating layer 208 is an organic resin such as polybenzoxazole (PBO) or polyimide.
  • PBO polybenzoxazole
  • the method further includes: a planarization process of the first insulating layer material formed on the surface of the passivation layer 202 such that the surface of the formed first insulating layer 208 is flush with the surface of the body 207 of the columnar electrode .
  • the formation of the first insulating layer 208 forms a concave in the body 207 of the columnar electrode.
  • the first insulating layer material fills the groove when the first insulating layer is formed, and an additional etching process is required to remove the first insulating layer filled in the groove. material.
  • a second photoresist layer 209 is formed on the surface of the first insulating layer 208, and the second photoresist layer 209 has at least one third opening 210 in the surface of the body 207 exposing the columnar electrode.
  • a body 207 of the columnar electrode having a partial thickness is etched away along the third opening 210, at least one groove 211 is formed in the body 207, and the remaining body 207 and the groove 211 constitute a columnar electrode.
  • the third opening 210 is formed by an exposure and development process, and the number, position, and shape of the third openings 210 correspond to the number, position, and shape of the formed grooves 211.
  • the number of the third openings 210 is greater than or equal to one.
  • For the specific distribution of the third openings 210 refer to the arrangement of the grooves in the foregoing semiconductor device.
  • the process of etching the body 207 is a reactive ion etching process or a wet etching process.
  • the gas used in the plasma etching process is chlorine gas
  • the solution used in the wet etching is diluted sulfuric acid solution or hydrogen peroxide and sulfuric acid. Mix the solution or other suitable etching solution.
  • the depth of the groove 211 formed in the body 207 is 0.5% to 99.5% of the height of the body, so that the filling portion in the groove penetrates to a certain depth in the body 207, and the bonding force between the solder ball 217 and the plug structure formed by the column electrode is stronger. .
  • the width of the recess 211 is gradually reduced, and when the solder is filled in the recess 211, no voids (bubbles) are generated in the recess, and the solder ball 217 and the columnar electrode are raised. Reliability between.
  • the shape of the side wall of the groove 211 may be a step shape, a diagonal line or a diagonal arc or the like. At the time of etching, the groove 211 having a large upper portion width and a small lower portion width is formed by controlling the magnitude of the bias power or the concentration of the etching solution.
  • the bottom shape of the groove 211 is a plane, a curved surface, or an irregular plane.
  • the cross-sectional pattern of the groove 211 is a circle, a polygon, a regular polygon or other regular or irregular pattern.
  • the cross-sectional pattern of the groove is a circle.
  • the number of the grooves 211 in the body 207 is one, and the groove is
  • the radius of the 211 is 1% to 99% of the radius of the columnar electrode body, and the number of correspondingly formed filling portions is also one, so that the contact plane of the filling portion and the body is increased, and the contact area is larger, so that the side of the body is
  • the wall maintains a certain mechanical strength, which is beneficial to improve the bonding force between the solder ball and the columnar electrode, so that the acceptable external force received by the solder ball (the force for separating the solder ball from the columnar electrode) is greatly enhanced, and the solder ball is not easy. Falling off the columnar electrode.
  • the grooves 211 when the number of the grooves 211 is greater than one, the grooves 211 are independently distributed in the body 207, and the grooves 211 are linearly distributed, matrix distributed, and concentrically distributed in the body 207. , concentric ring distribution, polygonal distribution, several rays or irregular distribution, the number and position of the subsequently formed filling portions correspond to the number and position of the grooves, and the number of subsequently formed filling portions is greater than one, when the number of filling portions When more than one, the number of faces of the solder ball in contact with the columnar electrode is further increased, and the contact area is further increased, so that the bonding force between the solder ball and the columnar electrode is further increased, and the filling portion is regular in the body.
  • the distribution is such that the bonding force of the solder ball and the columnar electrode is uniform at each moment. It should be noted that the above various distribution modes refer to a pattern formed by the center lines of the respective grooves (or the respective filling portions).
  • the second photoresist layer 209 is removed (refer to FIG. 11), and a metal barrier layer 212 is formed on the sidewalls and the bottom of the recess 211 and the top surface of the body 207.
  • the metal barrier layer 212 serves to prevent the subsequently formed solder balls and the body 207 of the columnar electrodes from directly contacting the contact surface to form a brittle copper-tin intermetallic compound, which affects the reliability of the solder joint.
  • the metal barrier layer 212 is a two-layer structure of nickel tin, a two-layer structure of nickel silver, a two-layer structure of nickel gold or a two-layer structure of nickel and tin alloy, and a tin layer, a silver layer, a gold layer or a tin alloy layer is formed.
  • the metal barrier layer 212 is a two-layer structure of nickel tin, and nickel is favorable for preventing copper from spreading outward, even if there is a part of copper and tin.
  • the metal barrier layer 212 diffuses, and the nickel-copper compound formed at the interface between the metal barrier layer 212 and the columnar electrode has higher strength and good thermoelectricity, and the nickel-tin compound formed at the interface between the metal barrier layer 212 and the solder ball is more.
  • High strength, high hardness and uniform surface do not cause problems such as reduced mechanical strength and welding damage of existing contact interfaces.
  • the thickness of the metal barrier layer 212 is smaller than the radius of the groove 211, preventing the metal barrier layer from blocking the groove
  • the metal barrier layer 212 is formed by a selective electroless plating process and a selective electroless plating process.
  • a metal barrier layer 212 can be selectively formed on the surface of the metal.
  • ultrasonic vibration can be used to prevent bubbles from forming in the through holes when the electroless plating solution enters the through holes 211 during the electroless plating, thereby affecting the formation of the metal barrier layer 212.
  • the frequency of the ultrasonic waves is greater than 20 kHz.
  • a pressure greater than 1 standard atmospheric pressure may be applied in the electroless plating chamber, so that the electroless plating solution has a pressure, and the electroless plating solution can easily enter the through hole 211 without being in the through hole. Form bubbles.
  • a mask layer is formed on the columnar electrode after electroless plating, and then the mask layer is used as a mask to remove the column electrode a metal barrier layer on an insulating layer.
  • the metal barrier layer may be formed using a sputtering process.
  • a printing screen or a stainless steel plate 213 having a top surface of the body 207 exposing the columnar electrode and a groove in the body is placed on the surface of the first insulating layer 208.
  • a fourth opening of 211 (refer to FIG. 12); filling the fourth opening and the recess with a solder paste 214 by a screen printing process.
  • solder paste 214 is made of tin or a tin alloy.
  • the printed screen or stainless steel plate 213 (refer to FIG. 13) is removed, and the solder paste 214 (refer to FIG. 13) is subjected to a reflow process to form a metal on the top of the body 207 of the columnar electrode.
  • the bump 216 forms a filling portion 215 in the groove 211 (refer to FIG. 12), and the metal bump 216 and the filling portion 215 constitute a solder ball 217.
  • the reflow process includes a heat treatment process.
  • FIG. 15 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention, including: a semiconductor substrate 300 having a plurality of pads 301 thereon; a passivation layer 302 on the semiconductor substrate 300, The passivation layer 302 has a first opening exposing all or part of the surface of the pad 301; a columnar electrode on the pad 301 in the first opening, the columnar electrode includes a body 307 and is located in the body 307 a groove having an opening flush with a top surface of the body 307; a first insulating layer 308 on the passivation layer 302, a surface of the first insulating layer 308 being lower than a body 307 of the columnar electrode Top surface, first insulating layer 308 and body of columnar electrode a first annular etched groove between the outer side walls; a metal bump 320 on the top of the body 307 of the columnar electrode, a filling portion 319 filling the groove, and an outer side wall of the columnar electrode
  • the present embodiment differs from the first embodiment in that the solder ball 321 further includes a skirt portion "L"-type skirt portion 318 on the outer side wall of the body 307 of the columnar electrode, compared to the first embodiment of the present invention.
  • the solder ball 321 is in contact with the outer side wall of the body 307 in addition to the top surface of the body 307 and the inner side wall of the recess in the body 307, so that the contact surface of the solder ball 321 and the columnar electrode is in contact with each other.
  • the area is further increased, and when subjected to an external force, the force applied to the solder ball is further dispersed, and the degree of bonding between the solder ball and the columnar electrode is improved.
  • the three faces are in contact with each other.
  • the width of the lower portion of the "L"-shaped skirt portion 318 is greater than the width of the upper portion, having a function similar to that of the support frame, and the "L"-shaped skirt portion allows the solder ball to receive an acceptable lateral external force ( The force for detaching the solder ball from the columnar electrode is greatly enhanced, and the solder ball is not easily detached from the columnar electrode.
  • FIG. 16 is a schematic flow chart of forming a method for forming the above semiconductor device, including: Step S30, providing a semiconductor substrate, the semiconductor substrate having a plurality of pads;
  • Step S31 forming a passivation layer on the semiconductor substrate, the passivation layer having a first opening exposing a surface of the pad;
  • Step S32 forming a seed layer step S33 on the sidewalls and the bottom of the first opening and the surface of the passivation layer, forming a first photoresist layer on the surface of the seed layer, the first photoresist layer having a second opening corresponding to the first opening;
  • Step S34 filling the first opening and the second opening with a full metal by using an electroplating process to form a body of the columnar electrode;
  • Step S35 removing the first photoresist layer; removing a portion of the seed layer on the passivation layer;
  • Step S36 forming a first insulating layer on the passivation layer, the surface of the first insulating layer being lower than the columnar shape a top surface of the body of the electrode, a first annular etched groove between the first insulating layer and the outer side wall of the body, the first annular etched groove exposing a surface of the portion of the passivation layer;
  • Step S37 forming a second photoresist layer on the surface of the first insulating layer, the second photoresist layer having at least one third opening exposing a surface of the columnar electrode body, and etching a portion of the thickness along the third opening
  • the body of the columnar electrode forms at least one groove in the body, and the body and the groove constitute a columnar electrode;
  • Step S38 removing the second photoresist layer; placing a printing screen or a stainless steel plate on the surface of the first insulating layer, the printing screen or the stainless steel plate having a top surface exposing the columnar electrode body and a groove in the body And a fifth opening of the first annular etched groove;
  • Step S39 filling the fifth opening, the groove and the first annular etching groove with a solder paste by using a screen printing process; removing the printing mesh plate or the stainless steel plate, performing a reflow process on the solder paste,
  • a metal protruding head is formed on the top of the main body of the columnar electrode, a filling portion is formed in the groove, and a skirt portion is formed on the outer side wall of the body, the upper portion of the skirt portion is connected with the metal protruding head, and the lower portion of the skirt portion and the columnar electrode are a portion of the side passivation layer is connected and is in contact with the sidewall of the first annular etched groove, the width of the lower portion of the skirt portion is greater than the width of the upper portion, and the surface of the lower portion of the skirt portion is lower than the first portion
  • the surface of the insulating layer is flush with the surface of the first insulating layer, and the metal bump, the filling portion and the skirt portion constitute a solder ball.
  • 17 to 24 are schematic cross-sectional views showing a process of forming a semiconductor device according to a second embodiment of the present invention, and a step of forming the above semiconductor device will be described in detail below with reference to Figs.
  • a semiconductor substrate 300 having a plurality of pads 301 thereon; a passivation layer 302 is formed on the semiconductor substrate 300, and the passivation layer 302 has exposed all or part of the pads 301.
  • the seed layer is a conductive layer and the body 307 of the columnar electrode is formed by an electroplating process, it is necessary to form a surface of the body 307 covering the columnar electrode and a portion of the seed layer (the seed layer near the surface of the passivation layer 302 of the body 307).
  • a photoresist layer and then using the patterned photoresist layer as a mask, removing a portion of the seed layer of the surface of the passivation layer 302 away from the body 307, and then removing the patterned photoresist layer, so that the remaining seed layer 303 portion Located between the body 307 and the pad, a portion is located near the surface of the passivation layer 302 of the body 303.
  • a first insulating layer 308 is formed on the surface of the passivation layer 302.
  • the surface of the first insulating layer 308 is lower than the surface of the body 307, and the first insulating layer 308 and the outer side of the body 307 of the columnar electrode
  • the first annular etched recess 309 is formed by a photolithography and etching process or other suitable process.
  • a second photoresist layer is formed on the surface of the first insulating layer 308.
  • the second photoresist layer 310 has at least one third opening 311 exposing a surface of the columnar electrode body 307.
  • the body 307 of the columnar electrode is partially etched away along the third opening 311 to form a body in the body.
  • At least one groove 312, the body 307 and the groove 312 constitute a columnar electrode.
  • the second photoresist layer 310 is removed (refer to FIG. 20); in the body 307, the sidewalls and the bottom of the recess 312, the top surface and the outer sidewall of the body 307 form a metal barrier layer 313.
  • the metal barrier layer 313 is partially located on the surface of the seed layer 303 in the first annular etched recess 309.
  • a printing screen or a stainless steel plate 315 having a top surface of the exposed columnar electrode body 307 and a groove in the body is placed on the surface of the first insulating layer 308. 312 and a fifth opening 316 of the first annular etched recess.
  • the solder paste 317 is filled in the fifth opening 316, the recess 312 and the first annular etch recess by a screen printing process; and the printed stencil or stainless steel 315 is removed.
  • the solder paste 317 is subjected to a reflow process, a metal bump 320 is formed on the top of the body 307 of the columnar electrode, a filling portion 319 is formed in the groove, and a skirt portion 318 is formed on the outer side wall of the body 307, and the skirt portion 318 is formed.
  • the upper portion is connected to the metal tab 320, the lower portion of the skirt portion 318 and the sides of the columnar electrode
  • the metal barrier layer 313 is connected and is in contact with the sidewall of the first annular etched groove.
  • the width of the lower portion of the skirt portion 318 is greater than the width of the upper portion, and the surface of the lower portion of the skirt portion 318 is lower than the first portion.
  • the surface of an insulating layer 308 or flush with the surface of the first insulating layer 308 or higher than the surface of the first insulating layer 308, the metal bump 320, the filling portion 319 and the skirt portion 318 constitute a solder ball 321.
  • the solder paste on the top of the columnar electrode forms a metal bump 320 under the surface tension
  • the top surface of the columnar electrode is higher than the surface of the first insulating layer 308, and the solder paste in the middle portion of the outer side wall of the body 307 is only A planar contact with the sidewall of the body, a portion of the solder paste also converges toward the metal bump 320 under the surface tension, and the solder paste in the first annular etch recess at the lower side of the outer sidewall of the body 307 is first
  • the sidewall of the annular etched recess, the metal barrier layer 313 on the outer sidewall portion of the body 307, and the portion of the metal barrier layer 311 on the passivation layer 302 are in contact with each other.
  • FIG. 25 is a schematic structural diagram of a semiconductor device according to a third embodiment of the present invention, including: a semiconductor substrate 500 having a plurality of pads 501 thereon; a passivation layer 503 on the semiconductor substrate 500, The passivation layer 503 has a first opening exposing part or all of the surface of the pad 501; a seed layer 504 located on the sidewall and bottom of the first opening and a portion of the surface of the passivation layer 503; and a surface located on the surface of the seed layer 504 a wiring layer 505, the rewiring layer is filled with the first opening, the rewiring layer 505 is a part of the pad 501; a columnar electrode located on the surface of the rewiring layer 505 outside the first opening, the columnar electrode having the body 511 and located a recess in the body 511, the opening of the recess coincides with a top surface of the body 511 of the columnar electrode; a solder ball 510 on the columnar
  • the rewiring layer 505 can realize the redistribution of the contact points, which is beneficial to improve the integration degree of the packaged device.
  • the forming process of the re-wiring layer 505 is electroplating, and the material of the re-wiring layer 505 is copper.
  • the specific process of forming the wiring layer is: firstly forming a seed layer on the sidewalls and the bottom of the first opening and the surface of the passivation layer; Forming a photoresist layer on a surface of the seed layer, the photoresist layer having an opening exposing a surface of the seed layer, the width and position of the opening corresponding to the width and position of the rewiring layer to be formed; and then using an electroplating process
  • the opening is filled with metal to form a rewiring layer 505, and the rewiring layer 505 is filled with the first opening; then the photoresist layer is removed.
  • the body 511 of the columnar electrode is then formed on the surface of the rewiring layer outside the first opening, and then the excess seed layer on the passivation layer 503 is removed by using the rewiring layer 505 as a mask.
  • FIG. 26 is a schematic structural diagram of a semiconductor device according to a fourth embodiment of the present invention, including: a semiconductor substrate 600 having a plurality of pads 601 thereon; a passivation layer 603 on the semiconductor substrate 600,
  • the passivation layer 603 has a first opening exposing part or all of the surface of the pad 601; a seed layer 604 located on the sidewall and bottom of the first opening and a portion of the surface of the passivation layer 603; and a surface located on the surface of the seed layer 604
  • the wiring layer 605, the re-wiring layer 605 is filled with the first opening, the re-wiring layer 605 is a part of the pad 601;
  • the columnar electrode is located on the surface of the rewiring layer 605 outside the first opening, and the columnar electrode has the body 612 and a recess in the body 612, the opening of the recess coincides with the top surface of the body 612 of the columnar electrode; the second insulating layer 606
  • the rewiring layer 605 is provided, and the rewiring layer 605 is a part of the pad 601, and the columnar electrode is formed on the rewiring layer 605 as compared with the case where the columnar electrode is formed directly on the pad.
  • the rewiring layer 605 can realize the redistribution of the contact points, which is advantageous for improving the integration degree of the packaged device.
  • the columnar electrode in the semiconductor device includes a body and a groove in the body, the opening of the groove coincides with a top surface of the columnar electrode, and the column electrode has a solder ball thereon.
  • the solder ball includes a metal bump on a top of the columnar electrode and a filling portion filled with the groove, and the solder ball and the column electrode form a plug-like structure, and the solder ball and the column electrode are changed from the existing single plane contact
  • the solder ball not only contacts the top surface of the columnar electrode, but also contacts the inside of the columnar electrode, and the contact area between the solder ball and the columnar electrode increases, and the bonding strength between the two increases, making the solder ball acceptable.
  • the external force (the force that causes the solder ball to detach from the columnar electrode) is greatly enhanced, the solder ball is not easily detached from the columnar electrode, and the groove is only located in the body so that the bonding force between the bottom of the body and the pad is not affected.
  • the number of the grooves in the body is one, the radius of the groove is 1% to 99% of the radius of the column electrode body, the number of the corresponding filling portions is one, and the radius of the filling portion is columnar.
  • the radius of the electrode body is 1% ⁇ 99%, so that the contact plane between the filling portion and the body is increased, and the contact area is large, so that the sidewall of the body maintains a certain mechanical strength, which is beneficial to improve the bonding between the solder ball and the columnar electrode.
  • the force causes the acceptable external force of the solder ball (the force that causes the solder ball to disengage from the columnar electrode) to be greatly enhanced, and the solder ball is not easily detached from the columnar electrode.
  • the grooves are independently distributed in the body, and the grooves are linearly distributed in the body, matrix distribution, concentric circle distribution, concentric ring distribution, polygonal distribution, several rays or irregularities.
  • Distribution, the number and position of the filling portions correspond to the number and position of the grooves, so that the number of faces of the solder balls in contact with the columnar electrodes is further increased, and the contact area is further increased, thereby making the solder balls and the columnar electrodes
  • the bonding force between the two is further increased, and the filling portion is regularly distributed in the body, so that the bonding force of the solder ball and the columnar electrode at each moment is evenly distributed.
  • the solder ball further includes a skirt portion "L" type skirt portion on the outer side wall of the body of the columnar electrode, the solder ball being in contact with the top surface of the body and the inner side wall of the groove in the body, and the body
  • the contact of the outer side walls further increases the number of contact faces of the solder balls and the columnar electrodes and the contact area.
  • a columnar electrode of the semiconductor device is formed, the columnar electrode includes a body and a groove in the body, and an opening of the groove coincides with a top surface of the columnar electrode, in a column shape
  • Forming a solder ball on the electrode, the solder ball including a metal bump on the top of the columnar electrode and a filling portion filling the groove, the solder ball and the column electrode form a plug-like structure, and the solder ball and the column electrode are Some single-plane contacts become multi-plane contacts, and the solder balls not only contact the top surface of the columnar electrodes, but also have contact with the inside of the columnar electrodes, and the contact area between the solder balls and the columnar electrodes increases, and the bonding force between the two increases.
  • the acceptable external force (the force that causes the solder ball to detach from the columnar electrode) is greatly enhanced, the solder ball is not easily detached from the columnar electrode, and the groove is only located in the body so that the bonding force between the bottom of the body and the pad is not affected. .
  • the depth of the groove formed in the body is 0.5% to 99.9% of the height of the body, so that the filling portion in the groove penetrates to a certain depth in the body, and the bonding force of the solder ball and the pin structure formed by the column electrode is stronger.
  • the width of the groove is gradually reduced.
  • voids bubbles

Abstract

一种半导体器件及其形成方法，该半导体器件包括：半导体基底（300），该半导体基底（300）具有若干焊盘（301）；位于该焊盘（301）上的柱状电极，该柱状电极包括本体（307）和位于该本体（307）中的凹槽，凹槽的开口与柱状电极的顶部表面重合；位于该柱状电极上的焊球（321），该焊球（321）包括位于柱状电极顶部上的金属凸头（320）和填充满该凹槽的填充部（319）。焊球与柱状电极构成类似插稍的结构，提高了焊球与柱状电极之间的结合力。

Description

半导体器件及其形成方法
本申请要求 2012年 11月 8日提交中国专利局、申请号为 201210444471.2、 发明名称为 "半导体器件"的中国专利申请的优先权和 2012年 11月 8 日提交 中国专利局、申请号为 201210444474.6、发明名称为 "半导体器件的形成方法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体封装领域，特别涉及一种能提高焊球与柱状电极结合力 的半导体器件及其形成方法。
背景技术
芯片级封装（ Chip Scale Package, CSP )作为最新一代的芯片封装技术，
CSP封装的产品具有体积小、电性能好和热性能好等优点。圆片级 CSP( WCSP ) 作为芯片级封装的一种， 是先在圆片上进行封装， 并以圆片的形式进行测试， 老化筛选， 其后再将圆片分割成单一的 CSP电路。
公开号为 CN1630029A的中国专利中公开了一种圆片级 CSP结构的半导 体器件， 请参考图 1 , 包括： 半导体基底 11 , 所述半导体基底 11上具有焊盘 12; 位于所述半导体基底 11表面的钝化层 14, 所述钝化层 14具有暴露焊盘 12表面的开口； 位于部分钝化层 14表面以及开口内的再布线层 16,再布线层 16与焊盘 12相连接； 位于所述开口外的再布线层 16表面的柱状电极 17; 覆 盖所述再布线层 16和部分钝化层 14表面的绝缘层 20, 绝缘层 20的表面与柱 状电极 17的表面平齐； 位于柱状电极 17表面的焊球 21。
现有的半导体器件中的焊球容易从柱状电极的表面脱落。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，提高焊球与柱状 电极之间的结合力。
为解决上述问题， 本发明技术方案提供了了一种半导体器件， 包括： 半导 体基底， 所述半导体基底具有若干焊盘； 位于所述焊盘上的柱状电极， 所述柱 状电极包括本体和位于所述本体中的凹槽，凹槽的开口与柱状电极的顶部表面 重合； 位于所述柱状电极上的焊球， 所述焊球包括位于柱状电极顶部上的金属 凸头和填充满所述凹槽的填充部。 可选的， 所述凹槽的数量为 1个， 所述凹槽的半径为柱状电极本体半径的 1%~99%。
可选的， 所述凹槽的数量大于 1个， 凹槽在本体中独立分布。
可选的， 所述凹槽在本体中呈直线分布、 矩阵分布、 同心圆分布、 同心圆 环分布、 多边形分布、 若干射线或者不规则分布。
可选的， 所述半导体基底上具有钝化层， 所述钝化层中具有第一开口， 第 一开口暴露出焊盘的全部或部分表面，第一开口的侧壁与柱状电极的外侧侧壁 相接触。
可选的， 所述钝化层上具有第一绝缘层， 第一绝缘层的表面与柱状电极的 顶部表面齐平， 第一绝缘层覆盖柱状电极的侧壁。
可选的， 所述钝化层上具有第一绝缘层， 第一绝缘层的表面低于柱状电极 的顶部表面， 第一绝缘层和柱状电极的外侧侧壁之间具有第一环形刻蚀凹槽， 第一环形刻蚀凹槽暴露钝化层的部分表面。
可选的， 所述焊球还包括位于柱状电极本体的外侧侧壁上的裙带部，裙带 部的上部分与金属凸头连接，裙带部的下部分与柱状电极两侧的部分钝化层相 接触， 并与第一环形刻蚀凹槽的侧壁相接触， 所述裙带部的下部分的宽度大于 上部分的宽度，裙带部的下部分的表面低于第一绝缘层的表面或与第一绝缘层 的表面平齐或者高于第一绝缘层的表面。
可选的， 所述半导体基底上具有钝化层， 所述钝化层具有暴露焊盘全部或 部分表面的第一开口，位于部分钝化层上的再布线层，所述再布线层填充满所 述第一开口，再布线层作为焊盘的一部分，柱状电极位于第一开口外的再布线 层上。
可选的， 还包括： 位于所述钝化层上和再布线层上的第二绝缘层， 第二绝 缘层的表面与柱状电极的本体顶部表面齐平。
可选的， 还包括： 位于所述钝化层上的第二绝缘层， 第二绝缘层的表面低 于柱状电极的本体顶部表面，第二绝缘层和柱状电极的本体之间具有第二环形 刻蚀凹槽， 第二环形刻蚀凹槽暴露再布线层的部分表面。
可选的， 所述焊球还包括位于柱状电极本体的外侧侧壁上的裙带部，裙带 部的上部分与金属凸头连接，裙带部的下部分与柱状电极两侧的部分再布线层 相连接， 并与第二环形刻蚀凹槽的侧壁相接触， 所述裙带部的下部分的宽度大 于上部分的宽度，裙带部的下部分的表面低于第一绝缘层的表面或与第一绝缘 层的表面平齐或者高于第一绝缘层的表面。
可选的， 其特征在于， 所述焊球与本体之间具有金属阻挡层。
为解决上述问题， 本发明还提供了一种半导体器件的形成方法， 包括： 提 供半导体基底， 所述半导体基底具有若干焊盘； 在所述半导体基底上形成钝化 层，所述钝化层具有暴露焊盘表面的第一开口；在所述焊盘上的形成柱状电极， 所述柱状电极包括本体和位于所述本体中的凹槽，凹槽的开口与柱状电极的顶 部表面重合； 在所述柱状电极上形成焊球， 所述焊球包括位于柱状电极顶部的 金属凸头和填充满所述凹槽的填充部。
可选的， 所述凹槽的数量为 1个， 所述凹槽的半径为柱状电极本体半径的 1%~99%。
可选的， 所述凹槽的数量大于 1个， 凹槽在本体中独立分布。
可选的， 所述凹槽在本体中呈直线分布、 矩阵分布、 同心圆分布、 同心圆 环分布、 多边形分布或者不规则分布。
可选的， 其特征在于， 所述柱状电极的形成方法为： 在所述第一开口的侧 壁和底部以及钝化层的表面形成种子层； 在所述种子层表面形成第一光刻胶 层，所述第一光刻胶层具有与第一开口对应的第二开口； 采用电镀工艺在所述 第一开口和第二开口中填充满金属， 形成柱状电极的本体； 去除所述第一光刻 胶层； 以所述柱状电极为掩膜去除钝化层上的部分种子层； 在所述钝化层上形 成第一绝缘层； 在所述第一绝缘层表面形成第二光刻胶层， 所述第二光刻胶层 中具有暴露柱状电极本体表面的至少一个第三开口；沿第三开口刻蚀去除部分 厚度的所述柱状电极的本体，在本体中形成至少一个凹槽， 所述本体和凹槽构 成柱状电极。
可选的， 所述第一绝缘层的表面与柱状电极的本体的顶部表面平齐， 第一 绝缘层与柱状电极的外侧侧壁相接触。
可选的， 在本体中形成至少一个凹槽后， 去除所述第二光刻胶层； 将印刷 网板或不锈钢板置于第一绝缘层表面，所述印刷网板或不锈钢板具有暴露所述 柱状电极的本体和通孔以及环形刻蚀凹槽的第四开口；采用网板印刷工艺在第 四开口和凹槽中填充满焊锡膏； 移除所述印刷网板或不锈钢板，对所述焊锡膏 进行回流工艺，在柱状电极的本体顶部上形成金属凸头，在凹槽中形成填充部， 金属凸头和填充部构成凹槽。
可选的， 所述第一绝缘层的表面低于柱状电极的本体的顶部表面， 第一绝 缘层和本体的外侧侧壁之间具有第一环形刻蚀凹槽，第一环形刻蚀凹槽暴露出 部分钝化层的表面。
可选的， 在本体中形成至少一个凹槽后， 去除所述第二光刻胶层； 将印刷 网板或不锈钢板置于第一绝缘层表面，所述印刷网板或不锈钢板具有暴露柱状 电极本体的顶部表面和本体中的凹槽以及第一环形刻蚀凹槽的第五开口；采用 网板印刷工艺在第五开口、 凹槽和第一环形刻蚀凹槽中填充满焊锡膏； 移除所 述印刷网板或不锈钢板，对所述焊锡膏进行回流工艺，在柱状电极的本体顶部 上形成金属凸头， 在凹槽中形成填充部， 在本体的外侧侧壁上形成裙带部， 裙 带部的上部分与金属凸头连接，裙带部的下部分与柱状电极两侧的部分钝化层 相连接， 并与第一环形刻蚀凹槽的侧壁相接触， 所述裙带部的下部分的宽度大 于上部分的宽度，裙带部的下部分的表面低于第一绝缘层的表面或与第一绝缘 层的表面平齐或者高于第一绝缘层的表面，金属凸头、填充部和裙带部构成凹 槽。
可选的， 其特征在于， 所述焊球和柱状电极的本体之间还形成有金属阻挡 层。
与现有技术相比， 本发明技术方案具有以下优点：
所述半导体器件中的柱状电极包括本体和位于所述本体中的凹槽，凹槽的 开口与柱状电极的顶部表面重合，柱状电极上具有焊球， 所述焊球包括位于柱 状电极顶部的金属凸头和填充满所述凹槽的填充部，焊球与柱状电极构成一种 类似插销的结构，焊球与柱状电极由现有的单平面接触变为多平面接触， 焊球 不但与柱状电极的顶部表面接触， 而且与柱状电极的内部有接触， 焊球与柱状 电极的接触面积增大， 两者的结合力增强， 使得焊球受到的可接受外力（使焊 球与柱状电极脱离的力）大大的增强， 焊球不易从柱状电极上脱落， 并且凹槽 只位于本体中使得本体底部与焊盘结合力不会受到影响。
所述本体中凹槽的数量为 1 个， 所述凹槽的半径为柱状电极本体半径的 1%~99%, 对应的所述填充部的数量为 1个， 所述填充部的半径为柱状电极本 体半径的 1%~99%, 使得填充部与本体接触平面增大、 接触面积较大的同时， 使得本体的侧壁保持一定的机械强度，有利于提高焊球与柱状电极之间的结合 力， 使得焊球受到的可接受外力 （使焊球与柱状电极脱离的力） 大大的增强， 焊球不易从柱状电极上脱落。
所述凹槽的数量大于 1个时， 凹槽在本体中独立分布， 所述凹槽在本体中 呈直线分布、 矩阵分布、 同心圆分布、 同心圆环分布、 多边形分布、 若干射线 或者不规则分布，所述填充部数量和位置与凹槽的数量和位置相对应，使得焊 球与柱状电极的相接触的面的数量进一步增多，接触面积也进一步增大，从而 使得焊球与柱状电极之间的结合力进一步增大， 填充部在本体中呈规则的分 布， 使得焊球与柱状电极在各个当下的结合力分布均匀。
所述焊球还包括位于柱状电极的本体外侧侧壁的裙带部 "L"型的裙带部， 焊球除了与本体的顶部表面和本体中的凹槽的内侧侧壁接触外，还与本体的外 侧侧壁接触，使得焊球与柱状电极的接触面的数量和接触面积进一步增大，在 受到外力的作用时，使得焊球受到的作用力进一步分散，提高了焊球与柱状电 极之间的结合度。
本体中形成的凹槽的深度为本体高度的 0.5%~99.9%, 使得凹槽中的填充 部深入本体中一定的深度， 焊球与柱状电极构成的插销结构的结合力更强。
从凹槽的开口到底部， 所述凹槽的宽度逐渐减小， 在凹槽中填充焊锡时， 在凹槽中不会产生空隙 （气泡）， 提高焊球与柱状电极之间的稳定性。
附图说明
图 1为现有技术圆片级结构的半导体器件的结构示意图；
图 2~图 4为本发明第一实施例半导体器件的结构示意图；
图 5为本发明第一实施例半导体器件形成方法的流程示意图；
图 6~图 14 为本发明第一实施例半导体器件的形成过程的剖面结构示意 图；
图 15为本发明第二实施例半导体器件的结构示意图；
图 16为本发明第二实施例半导体器件的形成方法流程示意图；
图 17~图 24为本发明第二实施例半导体器件的形成过程的剖面结构示意 图；
图 25为本发明第三实施例半导体器件的结构示意图；
图 26为本发明第四实施例半导体器件的结构示意图。
具体实施方式
现有的圆片级 CSP结构的半导体器件中， 由于焊球只与柱状电极上表面 接触， 两者的接触面积较小， 焊球与柱状电极的结合力较差， 在受到外力的作 用时，焊球容易从柱状电极的表面脱落或在焊球与柱状电极的接触面上产生裂 缝， 不利于后续封装工艺的进行， 使得封装器件容易失效。
为解决上述问题，发明人提出一种半导体器件， 所述半导体器件中的柱状 电极包括本体和位于所述本体中的凹槽，凹槽的开口与柱状电极的顶部表面重 合，柱状电极上具有焊球， 所述焊球包括位于柱状电极顶部的金属凸头和填充 满所述凹槽的填充部， 焊球与柱状电极构成一种类似插销的结构， 焊球与柱状 电极由现有的单平面接触变为多平面接触，焊球不但与柱状电极的顶部表面接 触， 而且与柱状电极的内部有接触， 焊球与柱状电极的接触面积增大， 两者的 结合力增强， 使得焊球受到的可接受外力（使焊球与柱状电极脱离的力）大大 的增强， 焊球不易从柱状电极上脱落， 并且凹槽只位于本体中使得本体底部与 焊盘结合力不会受到影响。
为使本发明的上述目的、特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。 在详述本发明实施例时， 为便于说明， 示意图会不依一般比例作局部放大， 而且所述示意图只是示例， 其在此不应限 制本发明的保护范围。 此外， 在实际制作中应包含长度、 宽度及深度的三维空 间尺寸。
第一实施例
图 2~图 4为本发明第一实施例半导体器件的结构示意图，其中图 3和图 4 为图 2沿切割线 AB方面的剖面图的俯视图， 图 3和图 4中所述金属阻挡层未 示出。 参考图 2, 所述半导体器件包括： 半导体基底 200, 位于半导体基底 200上的若干焊盘 201 , 本实施例中以一个焊盘作为示例； 位于所述半导体基 底 200上的钝化层 202, 所述钝化层 202具有暴露焊盘 201全部或部分表面的 第一开口； 位于所述第一开口暴露的焊盘 201上的柱状电极， 所述柱状电极具 有本体 207和位于本体 207中的凹槽， 所述凹槽的开口与柱状电极的本体 207 顶部表面重合； 位于柱状电极上的焊球 217 , 所述焊球 217具有位于柱状电极 本体 207顶部表面上的金属凸头 216和填充满所述凹槽的填充部 215; 位于所 述钝化层 202表面的第一绝缘层 208, 所述第一绝缘层 208的表面与本体 207 的顶部表面平齐或者低于本体 207的顶部表面并与本体 207的外侧侧壁相接 触； 位于焊球 217和柱状电极的本体 207之间的金属阻挡层 212; 位于柱状电 极的本体 207与焊盘 201之间的种子层 203。
本体 207中的凹槽中填充焊锡形成焊球 217的填充部 215 , 本体 207中的 凹槽形状和位置与焊球 217的填充部 215的形状和位置相对应，所述凹槽的深 度为本体高度的 0.5%~99.5%, 使得凹槽中的填充部深入本体 207中一定的深 度， 焊球 217与柱状电极构成的插销结构的结合力更强， 凹槽未贯穿柱状电极 的本体 207, 使得柱状电极的本体 207底部与焊盘 201 (或种子层 203 )接触 面为本体材料和焊盘材料两种材料的接触， 不会影响本体 207底部与焊盘 201 (或种子层 203 )之间的结合力。
从凹槽的开口到底部， 所述凹槽的宽度逐渐减小， 在凹槽中填充焊锡时， 在凹槽中不会产生空隙 （气泡）， 提高焊球 217与柱状电极之间的可靠性， 相 对应的所述填充部 215的宽度也逐渐减小。
在一具体的实施例中， 所述本体 207中凹槽的数量为 1个， 所述凹槽的半 径为柱状电极本体半径的 1%~99%,对应的所述填充部 215的数量为 1个， 所 述填充部 215的半径为柱状电极本体半径的 1%~99%,使得填充部 215与本体 207接触平面增大、 接触面积较大的同时， 使得本体 207的侧壁保持一定的机 械强度，有利于提高焊球 217与柱状电极之间的结合力，使得焊球受到的可接 受外力（使焊球与柱状电极脱离的力）大大的增强， 焊球不易从柱状电极上脱 落， 具体的请参考图 3 , 图 3中金属阻挡层未示出， 所述柱状电极的本体 207 中具有 1个填充部 215 , 所述填充部的中心与柱状电极的中心重合， 使得填充 部 215与柱状电极在各个方向的结合力保持均勾，所述填充部 215的外侧侧壁 的横截面剖面形状为圆、 多边形、 正多边形或者其他规则或不规则的图形， 所 述本体外侧侧壁的也可以为横截面剖面形状为圆、 多边形、正多边形或者其他 规则或不规则的图形。 在另一具体的实施例中， 所述凹槽的数量大于 1 个时， 凹槽在本体 207 中独立分布， 所述凹槽在本体 207中呈直线分布、 矩阵分布、 同心圆分布、 同 心圆环分布、 多边形分布、 若干射线或者不规则分布， 所述填充部 215数量和 位置与凹槽的数量和位置相对应， 所述填充部 215的数量大于 1个时， 填充部 215在本体 207中独立分布，填充部 215在本体 207中呈直线分布、矩阵分布、 同心圆分布、同心圆环分布、多边形分布或者不规则分布。所述直线分布包括： 通过本体 207中心的单直线分布、通过本体中心的多直线分布、通过本体中心 的等角度的多直线分布、平行直线分布； 所述多边形分布包括正多边形分布和 非正多边形分布。 具体的请参考图 4, 图 3中金属阻挡层未示出， 图 4中以四 个填充部 215作为示例， 所述四个填充部 215在本体中呈矩形分布。 当填充部 215的数量大于一个时， 使得焊球 217与柱状电极的相接触的面的数量进一步 增多，接触面积也进一步增大，从而使得焊球 217与柱状电极之间的结合力进 一步增大， 填充部 215在本体中呈规则的分布，使得焊球与柱状电极在各个当 下的结合力分布均匀。 需要说明的是， 前述各种分布方式是指各凹槽（或各填 充部） 中心连线构成的图形。
请参考图 5 , 图 5为形成上述半导体器件形成方法的流程示意图， 包括： 步骤 S20, 提供半导体基底， 所述半导体基底具有若干焊盘；
步骤 S21 , 在所述半导体基底上形成钝化层， 所述钝化层具有暴露焊盘表 面的第一开口；
步骤 S22, 在所述第一开口的侧壁和底部以及钝化层的表面形成种子层； 步骤 S23 , 在所述种子层表面形成第一光刻胶层， 所述第一光刻胶层具有 与第一开口对应的第二开口；
步骤 S24, 采用电镀工艺在所述第一开口和第二开口中填充满金属， 形成 柱状电极的本体；
步骤 S25 , 去除所述第一光刻胶层； 以所述柱状电极为掩膜去除钝化层上 的部分种子层；
步骤 S26,在所述钝化层上形成第一绝缘层，所述第一绝缘层的表面与柱状 电极的本体的顶部表面平齐， 第一绝缘层与柱状电极的外侧侧壁相接触；
步骤 S27 , 在所述第一绝缘层表面形成第二光刻胶层， 所述第二光刻胶层 中具有暴露柱状电极本体表面的至少一个第三开口，沿第三开口刻蚀去除部分 厚度的所述柱状电极的本体，在本体中形成至少一个凹槽， 所述本体和凹槽构 成柱状电极；
步骤 S28 , 去除所述第二光刻胶层； 将印刷网板或不锈钢板置于第一绝缘 层表面，所述印刷网板或不锈钢板具有暴露所述柱状电极的本体和通孔以及环 形刻蚀凹槽的第四开口；
步骤 S29, 采用网板印刷工艺在第四开口和凹槽中填充满焊锡膏； 移除所 述印刷网板或不锈钢板，对所述焊锡膏进行回流工艺，在柱状电极的本体顶部 上形成金属凸头， 在凹槽中形成填充部， 金属凸头和填充部构成焊球。
图 6~图 14 为本发明第一实施例半导体器件的形成过程的剖面结构示意 图， 下面将结合图 6~图 14对上述形成步骤进行详细的描述。
首先， 请参考图 6, 提供半导体基底 200, 所述半导体基底 200具有若干 焊盘 201 ; 在所述半导体基底 200上形成钝化层 202, 所述钝化层 202具有暴 露焊盘 201表面的第一开口 204; 在所述第一开口 204的侧壁和底部以及钝化 层 202的表面形成种子层 203。
所述半导体基底 200上具有若干芯片 （图中未示出）， 焊盘与对应的芯片 相连。
所述焊盘 201由铝、铜、 金或者银等材料构成， 所述焊盘 201既可位于半 导体基底 200的表面，也可以位于半导体基底 200中。本实施例中仅示出一个 焊盘作为示例。
所述钝化层 202用于保护半导体基底 200上形成的芯片， 所述钝化层 202 的材料为氮化硅、 硼硅玻璃、 磷硅玻璃或硼磷硅玻璃或聚酰亚胺（polyimide ) 等。钝化层 202中形成的第一开口 204暴露焊盘 201的全部或部分表面。所述 钝化层 202为一层或多层的堆叠结构。
所述种子层 203作为后续电镀形成柱状电极本体时的供电层。所述种子层
203为铬金属层或钛金属层或钽金属层单层结构、 或者铬金属层或钛金属层或 钽金属层与铜金属层或金金属层或银金属层的多层的堆叠结构， 所述种子层 203通过溅射工艺形成， 所述种子层 203还可以作为扩散阻挡层， 防止后续形 成的柱状电极中的金属向第一绝缘层 202 中的扩散及加强柱状电极金属与第 一绝缘层 202的附着力。
需要说明的是， 后续提到的第一开口均是指形成种子层 203 后剩余的开 口。
接着，请参考图 7和图 8,在所述种子层 203表面形成第一光刻胶层 205 , 所述第一光刻胶层 205具有与第一开口 204对应的第二开口 206; 在所述第一 开口 204和第二开口 206内填充满金属， 形成柱状电极的本体 207。
第二开口 206的形成工艺为曝光和显影工艺，所述二开口 206的宽度等于 第一开口 204的宽度。所述第二开口 206的宽度也可以大于第一开口 204的宽 度，后续采用电镀工艺形成柱状电极的本体时。使得柱状电极的本体部分位于 绝缘层 202上的种子层 203表面。
所述在所述第一开口 204和第二开口 206内填充的金属为铜，填充金属的 工艺为电镀工艺。
然后， 请参考图 9, 去除所述第一光刻胶层 205 (参考图 8 ); 以所述柱状 电极 207为掩膜去除钝化层 202上的部分种子层 203。 部分种子层 203的工艺为干法刻蚀工艺或湿法刻蚀工艺，在去除部分所述种子 层 203时， 所述柱状电极的本体 207表面可以形成掩膜层。
在本发明的其他实施例中， 暴露的种子层还有部分位于所述钝化层表面， 在刻蚀种子层时， 所述本体和部分种子层表面还形成有掩膜层。
接着， 请参考图 10, 在所述钝化层 202表面形成第一绝缘层 208 , 所述第 一绝缘层 208的表面与柱状电极的本体 207的顶部表面平齐， 第一绝缘层 208 与柱状电极的本体 207的外侧侧壁相接触。
所述第一绝缘层 208作为电性隔离层和密封材料层， 所述第一绝缘层 208 的材料为聚苯并恶唑（ polybenzoxazole, PBO )或聚酰亚胺（ polyimide )等有 机树脂。
形成第一绝缘层 208时，还包括： 对形成在钝化层 202表面的第一绝缘层 材料的平坦化工艺， 使得形成的第一绝缘层 208的表面与柱状电极的本体 207 的表面平齐。
本实施例中，所述第一绝缘层 208的形成在柱状电极的本体 207中形成凹 槽之前， 防止在柱状电极的本体 207中形成凹槽后， 在形成第一绝缘层时， 第 一绝缘层材料会填充凹槽，需要额外的刻蚀工艺去除凹槽中填充的第一绝缘层 材料。
然后， 请参考图 11 , 在所述第一绝缘层 208表面形成第二光刻胶层 209, 所述第二光刻胶层 209中具有暴露柱状电极的本体 207表面的至少一个第三开 口 210; 沿第三开口 210刻蚀去除部分厚度的所述柱状电极的本体 207, 在本 体 207中形成至少一个凹槽 211 , 剩余的本体 207和凹槽 211构成柱状电极。
所述第三开口 210通过曝光和显影工艺形成， 第三开口 210的数量、位置 和形状与形成的凹槽 211的数量、位置和形状相对应。 所述第三开口 210的数 量大于等于 1个，第三开口 210的具体分布请参考前述半导体器件中凹槽的排 布。
刻蚀所述本体 207的工艺为反应离子刻蚀工艺或湿法刻蚀工艺，所述等离 子刻蚀工艺采用的气体为氯气，湿法刻蚀采用的溶液为稀释的硫酸溶液或双氧 水与硫酸的混合溶液或其他合适的刻蚀溶液。本体中 207形成的凹槽 211的深 度为本体高度的 0.5%~99.5%, 使得凹槽中的填充部深入本体 207中一定的深 度， 焊球 217与柱状电极构成的插销结构的结合力更强。
从凹槽 211 的开口到底部， 所述凹槽 211 的宽度逐渐减小， 后续在凹槽 211 中填充焊锡时， 在凹槽中不会产生空隙 （气泡）， 提高焊球 217与柱状电 极之间的可靠性。 所述凹槽 211的侧壁的形状可以为阶梯状、斜直线或者斜弧 线等。刻蚀时，通过控制偏置功率的大小或者刻蚀溶液的浓度以形成上部分宽 度大， 下部分宽度较小的凹槽 211。
所述凹槽 211的底部形状为平面、 弧面、 或者不规则的平面。
所述凹槽 211的横截面图形为圆、 多边形、正多边形或者其他规则或不规 则的图形， 本实施例中所述凹槽的横截面图形为圆。
作为一具体的实施例， 所述本体 207中凹槽 211的数量为 1个， 所述凹槽
211的半径为柱状电极本体半径的 1%~99%, 对应的后续形成的填充部的数量 也为 1个， 使得填充部与本体接触平面增大、接触面积较大的同时， 使得本体 的侧壁保持一定的机械强度，有利于提高焊球与柱状电极之间的结合力，使得 焊球受到的可接受外力（使焊球与柱状电极脱离的力）大大的增强， 焊球不易 从柱状电极上脱落。
在另一具体的实施例中， 所述凹槽 211的数量大于 1个时， 凹槽 211在本 体 207中独立分布， 所述凹槽 211在本体 207中呈直线分布、 矩阵分布、 同心 圆分布、 同心圆环分布、 多边形分布、 若干射线或者不规则分布， 后续形成的 填充部数量和位置与凹槽的数量和位置相对应，后续形成的填充部的数量大于 1个， 当填充部的数量大于一个时， 使得焊球与柱状电极的相接触的面的数量 进一步增多，接触面积也进一步增大，从而使得焊球与柱状电极之间的结合力 进一步增大， 填充部在本体中呈规则的分布，使得焊球与柱状电极在各个当下 的结合力分布均匀。 需要说明的是， 前述各种分布方式是指各凹槽（或各填充 部） 中心连线构成的图形。
参考图 12, 去除所述第二光刻胶层 209 (参考图 11 ), 在所述凹槽 211的 侧壁和底部以及本体 207的顶部表面形成金属阻挡层 212。
所述金属阻挡层 212用于防止后续形成的焊球和柱状电极的本体 207直接 接触在接触面形成脆性的铜锡金属间化合物， 而影响焊点的可靠性。现有技术 中的焊球和柱状电极直接接触时，在高温的环境中，柱状电极中的铜会迅速向 焊球的锡中扩散，在柱状电极和焊球接触界面形成铜锡金属间化合物， 由于铜 锡金属间化合物脆性较大，会降低接触界面的机械强度， 引起焊点在金属间化 合物和焊料边界上的损伤或开裂， 影响焊接的可靠性。
所述金属阻挡层 212为镍锡的双层结构、镍银的双层结构、镍金的双层结 构或镍和锡合金的双层结构，锡层、银层、金层或锡合金层形成在镍层的表面， 用于防止镍的氧化， 本实施例中， 所述金属阻挡层 212的为镍锡的双层结构， 镍有利于防止铜向外的扩散， 即使有部分铜和锡向金属阻挡层 212中扩散，在 金属阻挡层 212 和柱状电极的界面形成的镍铜化合物具有较高的强度和良好 的热电性， 在金属阻挡层 212和焊球的界面形成的镍锡化合物的较高的强度、 硬度高、表面均匀， 因此不会带来现有的接触界面的机械强度降低和焊接损伤 等问题。
金属阻挡层 212的厚度小于凹槽 211 的半径， 防止金属阻挡层堵塞凹槽
211。
所述金属阻挡层 212的形成工艺为选择性化学镀工艺，选择性化学镀工艺 可以选择性的在金属的表面形成金属阻挡层 212。
进行选择性化学镀工艺时，可以采用超声波震荡，防止在化学镀的过程中， 化学镀溶液进入通孔 211时，在通孔里形成气泡，影响金属阻挡层 212的形成。 所述超声波的频率大于 20KHz。
在进行选择性化学镀工艺时，所述化学镀腔室中可以施加大于 1标准大气 压的压力， 使得化学镀溶液具有一个压力， 化学镀溶液较易进入通孔 211内， 不会在通孔内形成气泡。
在本发明的其他实施例中， 当所述化学镀不具有选择性时，化学镀后在柱 状电极上形成掩膜层，接着以所述掩膜层为掩膜，去除柱状电极之外的第一绝 缘层上的金属阻挡层。
在本发明的其他实施例中， 所述金属阻挡层可以采用溅射工艺形成。
接着，请参考图 13 ,将印刷网板或不锈钢板 213置于所述第一绝缘层 208 表面，所述印刷网板或不锈钢板 213具有暴露柱状电极的本体 207顶部表面和 本体中的凹槽 211 (参考图 12 )的第四开口； 采用网板印刷工艺在第四开口和 凹槽中填充满焊锡膏 214。
具体的， 所述焊锡膏 214的材料为锡或锡合金。
最后， 请参考图 14, 移除所述印刷网板或不锈钢板 213 (参考图 13 ), 对 所述焊锡膏 214 (参考图 13 )进行回流工艺， 在柱状电极的本体 207的顶部上 形成金属凸头 216, 在凹槽 211 (参考图 12 )中形成填充部 215 , 金属凸头 216 和填充部 215构成焊球 217。
所述回流工艺包括热处理工艺。
第二实施例
参考图 15 , 图 15为本发明第二实施例半导体器件的结构示意图， 包括： 半导体基底 300, 所述半导体基底 300上具有若干焊盘 301 ; 位于所述半导体 基底 300上的钝化层 302, 所述钝化层 302具有暴露所述焊盘 301全部或部分 表面的第一开口；位于所述第一开口内的焊盘 301上的柱状电极， 所述柱状电 极包括本体 307和位于本体 307中的凹槽，所述凹槽的开口与本体 307的顶部 表面平齐； 位于所述钝化层 302上的第一绝缘层 308, 所述第一绝缘层 308的 表面低于柱状电极的本体 307的顶部表面，第一绝缘层 308和柱状电极的本体 外侧侧壁之间具有第一环形刻蚀凹槽；位于所述柱状电极的本体 307顶部的金 属凸头 320、 填充所述凹槽的填充部 319、 位于柱状电极本体 307的外侧侧壁 上的裙带部 318, 裙带部 318的上部分与金属凸头 320连接， 裙带部 318的下 部分与柱状电极两侧的部分钝化层 302相连接，并与第一环形刻蚀凹槽的侧壁 相接触， 所述裙带部的下部分的宽度大于上部分的宽度，裙带部的下部分的表 面低于第一绝缘层 308的表面或与第一绝缘层 308的表面平齐或者高于第一绝 缘层的表面， 所述金属凸头 320、 填充部 319和裙带部 318构成焊球 321 ; 还 包括：位于柱状电极的本体 307与焊盘 301之间的种子层 303 ,所述种子层 303 部分位于第一环形刻蚀凹槽内的钝化层 302表面；位于焊球 321和柱状电极的 本体 307之间的金属阻挡层 313 , 所述金属阻挡层 313部分位于第一环形刻蚀 凹槽中的种子层表面。
本实施例中本体 307中的凹槽的数量、尺寸和排布等请参考本发明第一实 施例的相关描述， 在此不再赘述。
本实施例与第一实施例的区别在于，所述焊球 321还包括位于柱状电极的 本体 307外侧侧壁的裙带部 "L" 型的裙带部 318, 相比于本发明的第一实施 例，焊球 321除了与本体 307的顶部表面和本体 307中的凹槽的内侧侧壁接触 夕卜，还与本体 307的外侧侧壁接触，使得焊球 321与柱状电极的接触面的数量 和接触面积进一步增大，在受到外力的作用时，使得焊球受到的作用力进一步 分散， 提高了焊球与柱状电极之间的结合度。
"L" 型的裙带部 318与第一环形刻蚀凹槽的侧壁、 本体 307的外侧侧壁
(或者本体 307外侧侧壁上部分金属阻挡层 313 )和第一环形刻蚀凹槽内的钝 化层 302 (或者第一环形刻蚀凹槽内的钝化层 302上的部分金属阻挡层 313 ) 三个面相接触， "L" 型的裙带部 318 下部分的宽度大于上部分的宽度， 具有 类似于支撑架的功能， "L"型的裙带部使得焊球受到的可接受的横向外力（使 焊球与柱状电极脱离的力） 大大的增强， 焊球不易从柱状电极上脱落。
请参考图 16,图 16为形成上述半导体器件的形成方法流程示意图，包括： 步骤 S30, 提供半导体基底， 所述半导体基底具有若干焊盘；
步骤 S31 , 在所述半导体基底上形成钝化层， 所述钝化层具有暴露焊盘表 面的第一开口； 步骤 S32, 在所述第一开口的侧壁和底部以及钝化层的表面形成种子层 步骤 S33 , 在所述种子层表面形成第一光刻胶层， 所述第一光刻胶层具有 与第一开口对应的第二开口；
步骤 S34, 采用电镀工艺在所述第一开口和第二开口中填充满金属， 形成 柱状电极的本体；
步骤 S35 , 去除所述第一光刻胶层； 去除钝化层上的部分种子层； 步骤 S36, 在所述钝化层上形成第一绝缘层， 所述第一绝缘层的表面低于 柱状电极的本体的顶部表面，第一绝缘层和本体的外侧侧壁之间具有第一环形 刻蚀凹槽， 第一环形刻蚀凹槽暴露出部分钝化层的表面；
步骤 S37 , 在所述第一绝缘层表面形成第二光刻胶层， 所述第二光刻胶层 中具有暴露柱状电极本体表面的至少一个第三开口，沿第三开口刻蚀去除部分 厚度的所述柱状电极的本体，在本体中形成至少一个凹槽， 所述本体和凹槽构 成柱状电极；
步骤 S38 , 去除所述第二光刻胶层； 将印刷网板或不锈钢板置于第一绝缘 层表面，所述印刷网板或不锈钢板具有暴露柱状电极本体的顶部表面和本体中 的凹槽以及第一环形刻蚀凹槽的第五开口；
步骤 S39, 采用网板印刷工艺在第五开口、 凹槽和第一环形刻蚀凹槽中填 充满焊锡膏； 移除所述印刷网板或不锈钢板， 对所述焊锡膏进行回流工艺， 在 柱状电极的本体顶部上形成金属凸头，在凹槽中形成填充部，在本体的外侧侧 壁上形成裙带部，裙带部的上部分与金属凸头连接，裙带部的下部分与柱状电 极两侧的部分钝化层相连接， 并与第一环形刻蚀凹槽的侧壁相接触， 所述裙带 部的下部分的宽度大于上部分的宽度，裙带部的下部分的表面低于第一绝缘层 的表面或与第一绝缘层的表面平齐， 金属凸头、 填充部和裙带部构成焊球。
图 17~图 24为本发明第二实施例半导体器件的形成过程的剖面结构示意 图， 下面结合图 17~图 24对上述半导体器件的形成步骤进行详细的描述。
首先， 参考图 17, 提供半导体基底 300, 所述半导体基底 300上具有若干 焊盘 301 ; 在所述半导体基底 300上形成钝化层 302, 所述钝化层 302具有暴 露全部或部分焊盘 301表面的第一开口；在第一开口内的焊盘表面形成柱状电 极的本体 307。 所述本体 307和焊盘之间还具有种子层 303 , 种子层 303部分位于靠近本 体 303的钝化层 302表面。 以种子层为导电层， 采用电镀工艺形成柱状电极的 本体 307后， 需要形成覆盖所述柱状电极的本体 307和部分种子层（靠近本体 307的钝化层 302表面的种子层）表面的图形化的光刻胶层， 然后以图形化的 光刻胶层为掩膜，去除钝化层 302表面远离本体 307的部分种子层， 然后去除 图形化的光刻胶层，使得剩余的种子层 303部分位于所述本体 307和焊盘之间， 部分位于靠近本体 303的钝化层 302表面。
上述具体的形成过程及相关描述请参考本发明的第一实施例，在此不再赘 述。 需要说明的是，后续本实施例中与第一实施例的半导体器件中的相似结构 的形成工艺和材料等均不做详细的描述， 具体请参考本发明的第一实施例。
接着， 请参考图 18 , 在所述钝化层 302表面形成第一绝缘层 308 , 所述第 一绝缘层 308的表面低于本体 307的表面，第一绝缘层 308和柱状电极的本体 307外侧侧壁之间具有第一环形刻蚀凹槽 309。 所述第一环形刻蚀凹槽 309通 过光刻和刻蚀工艺或其他合适的工艺形成。
接着， 请参考图 19和 20, 在所述第一绝缘层 308表面形成第二光刻胶层
310, 所述第二光刻胶层 310中具有暴露柱状电极本体 307表面的至少一个第 三开口 311 ; 沿第三开口 311刻蚀去除部分厚度的所述柱状电极的本体 307, 在本体中形成至少一个凹槽 312, 所述本体 307和凹槽 312构成柱状电极。
然后，请参考图 21 ,去除所述第二光刻胶层 310 (参考图 20 );在本体 307 中凹槽 312的侧壁和底部、本体 307顶部表面和外侧侧壁形成金属阻挡层 313 , 所述金属阻挡层 313部分位于第一环形刻蚀凹槽 309内的种子层 303表面。
接着，请参考图 22,将印刷网板或不锈钢板 315置于所述第一绝缘层 308 表面，所述印刷网板或不锈钢板 315具有暴露柱状电极本体 307的顶部表面和 本体中的凹槽 312以及第一环形刻蚀凹槽的第五开口 316。
最后，请参考图 23和图 24,采用网板印刷工艺在第五开口 316、 凹槽 312 和第一环形刻蚀凹槽中填充满焊锡膏 317;移除所述印刷网板或不锈钢板 315 , 对所述焊锡膏 317进行回流工艺，在柱状电极的本体 307顶部上形成金属凸头 320, 在凹槽中形成填充部 319, 在本体 307的外侧侧壁上形成裙带部 318, 裙 带部 318的上部分与金属凸头 320连接，裙带部 318的下部分与柱状电极两侧 的金属阻挡层 313相连接， 并与第一环形刻蚀凹槽的侧壁相接触， 所述裙带部 318的下部分的宽度大于上部分的宽度， 裙带部 318的下部分的表面低于第一 绝缘层 308的表面或与第一绝缘层 308的表面平齐或高于第一绝缘层 308的表 面， 金属凸头 320、 填充部 319和裙带部 318构成焊球 321。
在进行回流工艺时，柱状电极顶部的焊锡膏在表面张力的作用下形成金属 凸头 320, 柱状电极顶部表面高于第一绝缘层 308的表面， 本体 307的外侧侧 壁中间部分的焊锡膏只与本体侧壁一个平面接触，部分焊锡膏也会在表面张力 的作用下向金属凸头 320的方向汇聚，而本体 307外侧侧壁下部的第一环形刻 蚀凹槽内的焊锡膏与第一环形刻蚀凹槽的侧壁、本体 307外侧侧壁部分上金属 阻挡层 313和钝化层 302上的部分金属阻挡层 311三个面均接触， 在回流时， 焊盘 301上的部分金属阻挡层 313与第一环形刻蚀凹槽内的焊锡膏的接触面的 吸附力会氏消部分第一环形刻蚀凹槽内的焊锡膏指向金属凸头 320 方向的部 分张力和指向柱状电极的本体 307 方向的部分表面张力， 从而使得本体 307 外侧侧壁上形成 "L" 型的裙带部 318。
第三实施例
参考图 25 , 图 25为本发明第三实施例半导体器件的结构示意图， 包括： 半导体基底 500, 所述半导体基底 500上具有若干焊盘 501 ; 位于所述半导体 基底 500上的钝化层 503 , 所述钝化层 503具有暴露焊盘 501部分或全部表面 的第一开口； 位于第一开口的侧壁和底部以及部分钝化层 503 表面的种子层 504; 位于所述种子层 504表面的再布线层 505 , 再布线层填充满第一开口， 所述再布线层 505作为焊盘 501 的一部分； 位于第一开口外的再布线层 505 表面的柱状电极， 所述柱状电极具有本体 511和位于本体 511中的凹槽， 所述 凹槽的开口与柱状电极的本体 511顶部表面重合；位于柱状电极上的焊球 510, 所述焊球 510具有位于柱状电极本体 511顶部表面上的金属凸头 509和填充满 所述凹槽的填充部 508; 位于所述钝化层 503和再布线层 505表面的第二绝缘 层 506, 所述第二绝缘层 506的表面与本体 511的表面平齐并与本体 511的外 侧侧壁相接触； 位于焊球 510和柱状电极的本体 511之间的金属阻挡层 507。
本实施例， 相比于第一实施例， 具有再布线层 505 , 再布线层 505作为焊 盘 501的一部分，在再布线层 505上柱状电极，相比于在直接在焊盘上形成柱 状电极，再布线层 505能实现接触点的再分布，有利于提高封装器件的集成度。 所述再布线层 505的形成工艺为电镀，再布线层 505的材料为铜，在布线 层形成的具体过程为：首先在第一开口的侧壁和底部以及钝化层表面形成种子 层； 然后在种子层表面形成光刻胶层， 所述光刻胶层具有暴露种子层表面的开 口， 开口的宽度和位置与待形成的再布线层的宽度和位置相对应； 然后采用电 镀工艺， 在所述开口内填充满金属形成再布线层 505 , 并且所述再布线层 505 填充满第一开口； 然后去除光刻胶层。
在形成再布线层 505后，然后在第一开口外的再布线层表面形成柱状电极 的本体 511 , 接着以所述再布线层 505为掩膜， 去除钝化层 503上多余的种子 层。
关于本体 511中凹槽的形成和排布、 焊球 510的形成以及第二绝缘层 506 的形成等相关的描述， 请参考本发明的第一实施例， 在此不再赘述。
第四实施例
参考图 26, 图 26为本发明第四实施例半导体器件的结构示意图， 包括： 半导体基底 600, 所述半导体基底 600上具有若干焊盘 601 ; 位于所述半导体 基底 600上的钝化层 603 , 所述钝化层 603具有暴露焊盘 601部分或全部表面 的第一开口； 位于第一开口的侧壁和底部以及部分钝化层 603 表面的种子层 604; 位于所述种子层 604表面的再布线层 605 , 再布线层 605填充满第一开 口， 所述再布线层 605作为焊盘 601 的一部分； 位于第一开口外的再布线层 605表面的柱状电极， 所述柱状电极具有本体 612和位于本体 612中的凹槽， 所述凹槽的开口与柱状电极的本体 612顶部表面重合；位于钝化层 603和部分 再布线层 605表面的第二绝缘层 606, 第二绝缘层 606的表面低于本体 612的 顶部表面， 第二绝缘层 606与本体 612的侧壁之间具有第二环形刻蚀凹槽； 位 于所述柱状电极的本体 612顶部的金属凸头 610、 填充本体 612中凹槽的填充 部 609、 位于本体 612的外侧侧壁上的裙带部 608, 裙带部 608的上部分与金 属凸头 610连接， 裙带部 608的下部分与柱状电极两侧的部分再布线层 605 相连接， 并与第二环形刻蚀凹槽的侧壁相接触， 所述裙带部 608的下部分的宽 度大于上部分的宽度，裙带部 608的下部分的表面低于第二绝缘层 606的表面 或与第二绝缘层 606的表面平齐或高于第二绝缘层 606的表面，所述金属凸头 610、 填充部 609和裙带部 608构成焊球 611 ; 还包括： 位于焊球 611和柱状 电极的本体 612之间的金属阻挡层 607, 所述金属阻挡层 607部分位于第二环 形刻蚀凹槽内的再布线层 605表面。
本实施例， 相比于第二实施例， 具有再布线层 605 , 再布线层 605作为焊 盘 601的一部分，在再布线层 605上柱状电极，相比于在直接在焊盘上形成柱 状电极，再布线层 605能实现接触点的再分布，有利于提高封装器件的集成度。
上述各结构的形成过程和相关描述等请参考本发明的第三实施例和第二 实施例， 在此不再赘述。
综上， 本发明实施例的半导体器件，所述半导体器件中的柱状电极包括本 体和位于所述本体中的凹槽， 凹槽的开口与柱状电极的顶部表面重合，柱状电 极上具有焊球，所述焊球包括位于柱状电极顶部的金属凸头和填充满所述凹槽 的填充部， 焊球与柱状电极构成一种类似插销的结构，焊球与柱状电极由现有 的单平面接触变为多平面接触， 焊球不但与柱状电极的顶部表面接触， 而且与 柱状电极的内部有接触，焊球与柱状电极的接触面积增大，两者的结合力增强， 使得焊球受到的可接受外力（使焊球与柱状电极脱离的力）大大的增强， 焊球 不易从柱状电极上脱落，并且凹槽只位于本体中使得本体底部与焊盘结合力不 会受到影响。
所述本体中凹槽的数量为 1 个， 所述凹槽的半径为柱状电极本体半径的 1%~99%, 对应的所述填充部的数量为 1个， 所述填充部的半径为柱状电极本 体半径的 1%~99%, 使得填充部与本体接触平面增大、 接触面积较大的同时， 使得本体的侧壁保持一定的机械强度，有利于提高焊球与柱状电极之间的结合 力， 使得焊球受到的可接受外力 （使焊球与柱状电极脱离的力） 大大的增强， 焊球不易从柱状电极上脱落。
所述凹槽的数量大于 1个时， 凹槽在本体中独立分布， 所述凹槽在本体中 呈直线分布、 矩阵分布、 同心圆分布、 同心圆环分布、 多边形分布、 若干射线 或者不规则分布，所述填充部数量和位置与凹槽的数量和位置相对应，使得焊 球与柱状电极的相接触的面的数量进一步增多，接触面积也进一步增大，从而 使得焊球与柱状电极之间的结合力进一步增大， 填充部在本体中呈规则的分 布， 使得焊球与柱状电极在各个当下的结合力分布均匀。 所述焊球还包括位于柱状电极的本体外侧侧壁的裙带部 "L"型的裙带部， 焊球除了与本体的顶部表面和本体中的凹槽的内侧侧壁接触外，还与本体的外 侧侧壁接触，使得焊球与柱状电极的接触面的数量和接触面积进一步增大，在 受到外力的作用时，使得焊球受到的作用力进一步分散，提高了焊球与柱状电 极之间的结合度。
本发明实施例的半导体器件的形成方法， 形成所述半导体器件的柱状电 极， 所述柱状电极包括本体和位于所述本体中的凹槽， 凹槽的开口与柱状电极 的顶部表面重合，在柱状电极上形成焊球， 所述焊球包括位于柱状电极顶部的 金属凸头和填充满所述凹槽的填充部，焊球与柱状电极构成一种类似插销的结 构， 焊球与柱状电极由现有的单平面接触变为多平面接触， 焊球不但与柱状电 极的顶部表面接触， 而且与柱状电极的内部有接触， 焊球与柱状电极的接触面 积增大， 两者的结合力增强， 使得焊球受到的可接受外力（使焊球与柱状电极 脱离的力）大大的增强， 焊球不易从柱状电极上脱落， 并且凹槽只位于本体中 使得本体底部与焊盘结合力不会受到影响。
本体中形成的凹槽的深度为本体高度的 0.5%~99.9%, 使得凹槽中的填充 部深入本体中一定的深度， 焊球与柱状电极构成的插销结构的结合力更强。
从凹槽的开口到底部， 所述凹槽的宽度逐渐减小， 在凹槽中填充焊锡时， 在凹槽中不会产生空隙 （气泡）， 提高焊球与柱状电极之间的稳定性。
本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何 本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法 和技术内容对本发明技术方案做出可能的变动和修改， 因此， 凡是未脱离本发 改、 等同变化及修饰， 均属于本发明技术方案的保护范围。

Claims

权 利 要 求
1. 一种半导体器件， 其特征在于， 包括：
半导体基底， 所述半导体基底具有若干焊盘；
位于所述焊盘上的柱状电极，所述柱状电极包括本体和位于所述本体中的 凹槽， 凹槽的开口与柱状电极的顶部表面重合；
位于所述柱状电极上的焊球，所述焊球包括位于柱状电极顶部上的金属凸 头和填充满所述凹槽的填充部。
2. 如权利要求 1所述的半导体器件， 其特征在于， 所述凹槽的数量为 1个， 所述凹槽的半径为柱状电极本体半径的 1 %~99%。
3. 如权利要求 1所述的半导体器件， 其特征在于， 所述凹槽的数量大于 1个， 凹槽在本体中独立分布。
4. 如权利要求 3所述的半导体器件， 其特征在于， 所述凹槽在本体中呈直线 分布、 矩阵分布、 同心圆分布、 同心圆环分布、 多边形分布、 若干射线或者不 规则分布。
5. 如权利要求 1所述的半导体器件， 其特征在于， 所述半导体基底上具有钝 化层， 所述钝化层中具有第一开口， 第一开口暴露出焊盘的全部或部分表面， 第一开口的侧壁与柱状电极的外侧侧壁相接触。
6. 如权利要求 5所述的半导体器件， 其特征在于， 所述钝化层上具有第一绝 缘层， 第一绝缘层的表面与柱状电极的顶部表面齐平， 第一绝缘层覆盖柱状电 极的侧壁。
7. 如权利要求 5所述的半导体器件， 其特征在于， 所述钝化层上具有第一绝 缘层， 第一绝缘层的表面低于柱状电极的顶部表面， 第一绝缘层和柱状电极的 外侧侧壁之间具有第一环形刻蚀凹槽，第一环形刻蚀凹槽暴露钝化层的部分表 面。
8. 如权利要求 7所述的半导体器件， 其特征在于， 所述焊球还包括位于柱状 电极本体的外侧侧壁上的裙带部，裙带部的上部分与金属凸头连接，裙带部的 下部分与柱状电极两侧的部分钝化层相接触，并与第一环形刻蚀凹槽的侧壁相 接触， 所述裙带部的下部分的宽度大于上部分的宽度，裙带部的下部分的表面 低于第一绝缘层的表面或与第一绝缘层的表面平齐或者高于第一绝缘层的表 面。
9. 如权利要求 1所述的半导体器件， 其特征在于， 所述半导体基底上具有钝 化层， 所述钝化层具有暴露焊盘全部或部分表面的第一开口，位于部分钝化层 上的再布线层， 所述再布线层填充满所述第一开口，再布线层作为焊盘的一部 分， 柱状电极位于第一开口外的再布线层上。
10.如权利要求 9所述的半导体器件， 其特征在于， 还包括： 位于所述钝化层 上和再布线层上的第二绝缘层，第二绝缘层的表面与柱状电极的本体顶部表面 齐平。
11.如权利要求 9所述的半导体器件， 其特征在于， 还包括： 位于所述钝化层 上的第二绝缘层， 第二绝缘层的表面低于柱状电极的本体顶部表面， 第二绝缘 层和柱状电极的本体之间具有第二环形刻蚀凹槽，第二环形刻蚀凹槽暴露再布 线层的部分表面。
12.如权利要求 11所述的半导体器件， 其特征在于， 所述焊球还包括位于柱状 电极本体的外侧侧壁上的裙带部，裙带部的上部分与金属凸头连接，裙带部的 下部分与柱状电极两侧的部分再布线层相连接，并与第二环形刻蚀凹槽的侧壁 相接触， 所述裙带部的下部分的宽度大于上部分的宽度，裙带部的下部分的表 面低于第一绝缘层的表面或与第一绝缘层的表面平齐或者高于第一绝缘层的 表面。
13.如权利要求 6或 8或 10或 12所述的半导体器件， 其特征在于， 所述焊球 与本体之间具有金属阻挡层。
14.一种半导体器件的形成方法， 其特征在于， 包括：
提供半导体基底， 所述半导体基底具有若干焊盘；
在所述半导体基底上形成钝化层， 所述钝化层具有暴露焊盘表面的第一开 口；
在所述焊盘上的形成柱状电极， 所述柱状电极包括本体和位于所述本体中 的凹槽， 凹槽的开口与柱状电极的顶部表面重合；
在所述柱状电极上形成焊球， 所述焊球包括位于柱状电极顶部的金属凸头 和填充满所述凹槽的填充部。
15.如权利要求 14所述的半导体器件的形成方法， 其特征在于， 所述凹槽的数 量为 1个， 所述凹槽的半径为柱状电极本体半径的 1%~99%。
16.如权利要求 14所述的半导体器件的形成方法， 其特征在于， 所述凹槽的数 量大于 1个， 凹槽在本体中独立分布。
17.如权利要求 16所述的半导体器件的形成方法， 其特征在于， 所述凹槽在本 体中呈直线分布、 矩阵分布、 同心圆分布、 同心圆环分布、 多边形分布或者不 规则分布。
18.如权利要求 15或 16所述的半导体器件的形成方法， 其特征在于， 所述柱 状电极的形成方法为：在所述第一开口的侧壁和底部以及钝化层的表面形成种 子层； 在所述种子层表面形成第一光刻胶层， 所述第一光刻胶层具有与第一开 口对应的第二开口； 采用电镀工艺在所述第一开口和第二开口中填充满金属， 形成柱状电极的本体； 去除所述第一光刻胶层； 以所述柱状电极为掩膜去除钝 化层上的部分种子层； 在所述钝化层上形成第一绝缘层； 在所述第一绝缘层表 面形成第二光刻胶层 ,所述第二光刻胶层中具有暴露柱状电极本体表面的至少 一个第三开口； 沿第三开口刻蚀去除部分厚度的所述柱状电极的本体，在本体 中形成至少一个凹槽， 所述本体和凹槽构成柱状电极。
19.如权利要求 18所述的半导体器件的形成方法， 其特征在于， 所述第一绝缘 层的表面与柱状电极的本体的顶部表面平齐，第一绝缘层与柱状电极的外侧侧 壁相接触。
20.如权利要求 19所述的半导体器件的形成方法，其特征在于，在本体中形成 至少一个凹槽后，去除所述第二光刻胶层； 将印刷网板或不锈钢板置于第一绝 缘层表面，所述印刷网板或不锈钢板具有暴露所述柱状电极的本体和通孔以及 环形刻蚀凹槽的第四开口；采用网板印刷工艺在第四开口和凹槽中填充满焊锡 膏； 移除所述印刷网板或不锈钢板， 对所述焊锡膏进行回流工艺， 在柱状电极 的本体顶部上形成金属凸头，在凹槽中形成填充部，金属凸头和填充部构成凹 槽。
21.如权利要求 18所述的半导体器件的形成方法， 其特征在于， 所述第一绝缘 层的表面低于柱状电极的本体的顶部表面，第一绝缘层和本体的外侧侧壁之间 具有第一环形刻蚀凹槽， 第一环形刻蚀凹槽暴露出部分钝化层的表面。
22.如权利要求 21所述的半导体器件的形成方法， 其特征在于，在本体中形成 至少一个凹槽后，去除所述第二光刻胶层； 将印刷网板或不锈钢板置于第一绝 缘层表面，所述印刷网板或不锈钢板具有暴露柱状电极本体的顶部表面和本体 中的凹槽以及第一环形刻蚀凹槽的第五开口； 采用网板印刷工艺在第五开口、 凹槽和第一环形刻蚀凹槽中填充满焊锡膏； 移除所述印刷网板或不锈钢板，对 所述焊锡膏进行回流工艺，在柱状电极的本体顶部上形成金属凸头，在凹槽中 形成填充部，在本体的外侧侧壁上形成裙带部，裙带部的上部分与金属凸头连 接，裙带部的下部分与柱状电极两侧的部分钝化层相连接， 并与第一环形刻蚀 凹槽的侧壁相接触， 所述裙带部的下部分的宽度大于上部分的宽度，裙带部的 下部分的表面低于第一绝缘层的表面或与第一绝缘层的表面平齐或者高于第 一绝缘层的表面， 金属凸头、 填充部和裙带部构成凹槽。
23.如权利要求 20或 22所述的半导体器件的形成方法， 其特征在于， 所述焊 球和柱状电极的本体之间还形成有金属阻挡层。
PCT/CN2013/086214 2012-11-08 2013-10-30 半导体器件及其形成方法 WO2014071815A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/440,872 US9548282B2 (en) 2012-11-08 2013-10-30 Metal contact for semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201210444471.2 2012-11-08
CN201210444471.2A CN102915982B (zh) 2012-11-08 2012-11-08 半导体器件
CN201210444474.6A CN102931099B (zh) 2012-11-08 2012-11-08 半导体器件的形成方法
CN201210444474.6 2012-11-08

Publications (1)

Publication Number Publication Date
WO2014071815A1 true WO2014071815A1 (zh) 2014-05-15

Family

ID=50684044

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/086214 WO2014071815A1 (zh) 2012-11-08 2013-10-30 半导体器件及其形成方法

Country Status (2)

Country Link
US (1) US9548282B2 (zh)
WO (1) WO2014071815A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210035938A1 (en) * 2011-07-27 2021-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Bump structure having a side recess and semiconductor structure including the same

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343417B2 (en) 2013-09-18 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Hollow metal pillar packaging scheme
US9640683B2 (en) * 2013-11-07 2017-05-02 Xintec Inc. Electrical contact structure with a redistribution layer connected to a stud
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
JP6660687B2 (ja) * 2015-07-30 2020-03-11 シチズン電子株式会社 半導体素子および発光装置
JP6780933B2 (ja) * 2015-12-18 2020-11-04 新光電気工業株式会社 端子構造、端子構造の製造方法、及び配線基板
US9984987B2 (en) * 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
CN107039383B (zh) * 2017-04-26 2023-08-04 东莞市柏尔电子科技有限公司 一种结构改良的串联式二极管
US20190148325A1 (en) * 2017-11-10 2019-05-16 Advanced Semiconductor Engineering, Inc. Electronic device and method for manufacturing the same
KR20210082638A (ko) * 2019-12-26 2021-07-06 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
US11621209B2 (en) * 2021-08-17 2023-04-04 Qualcomm Incorporated Semiconductor device thermal bump

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080048337A1 (en) * 2006-08-25 2008-02-28 Nec Electronics Corporation Semiconductor device including through electrode and method of manufacturing the same
US20090098723A1 (en) * 2007-10-13 2009-04-16 Wan-Ling Yu Method Of Forming Metallic Bump On I/O Pad
CN102270590A (zh) * 2011-09-01 2011-12-07 苏州晶方半导体科技股份有限公司 晶圆级封装结构及封装方法
US20120086124A1 (en) * 2010-10-06 2012-04-12 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
CN102915982A (zh) * 2012-11-08 2013-02-06 南通富士通微电子股份有限公司 半导体器件
CN102931099A (zh) * 2012-11-08 2013-02-13 南通富士通微电子股份有限公司 半导体器件的形成方法
CN202917483U (zh) * 2012-11-08 2013-05-01 南通富士通微电子股份有限公司 半导体器件

Family Cites Families (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW448524B (en) 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
JP4750926B2 (ja) 2000-06-06 2011-08-17 富士通セミコンダクター株式会社 半導体装置
TW490821B (en) 2000-11-16 2002-06-11 Orient Semiconductor Elect Ltd Application of wire bonding technique on manufacture of wafer bump and wafer level chip scale package
CN1185707C (zh) 2002-06-17 2005-01-19 威盛电子股份有限公司 凸块底缓冲金属结构
US6696757B2 (en) * 2002-06-24 2004-02-24 Texas Instruments Incorporated Contact structure for reliable metallic interconnection
JP2004247522A (ja) 2003-02-14 2004-09-02 Seiko Epson Corp 半導体装置及びその製造方法
JP2005136035A (ja) 2003-10-29 2005-05-26 Matsushita Electric Ind Co Ltd バンプ電極構造およびバンプ形成方法
JP3929966B2 (ja) 2003-11-25 2007-06-13 新光電気工業株式会社 半導体装置及びその製造方法
US7068138B2 (en) * 2004-01-29 2006-06-27 International Business Machines Corporation High Q factor integrated circuit inductor
JP2005286087A (ja) 2004-03-30 2005-10-13 Nec Infrontia Corp 半導体装置
JP2006229018A (ja) 2005-02-18 2006-08-31 Matsushita Electric Ind Co Ltd テープキャリア基板およびその製造方法および半導体装置
KR101266335B1 (ko) * 2005-02-24 2013-05-24 에이저 시스템즈 엘엘시 플립 칩 장치를 제조하기 위한 구조 및 방법
DE102005014665A1 (de) * 2005-03-29 2006-11-02 Infineon Technologies Ag Substrat zur Herstellung einer Lötverbindung mit einem zweiten Substrat
US7488680B2 (en) * 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers
JP4738971B2 (ja) 2005-10-14 2011-08-03 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
JP4247690B2 (ja) 2006-06-15 2009-04-02 ソニー株式会社 電子部品及その製造方法
KR101328551B1 (ko) * 2006-10-02 2013-11-13 삼성전자주식회사 반도체 장치
JP4995551B2 (ja) * 2006-12-01 2012-08-08 ローム株式会社 半導体装置及び半導体装置の製造方法
CN101211791B (zh) 2006-12-27 2010-05-12 日月光半导体制造股份有限公司 晶圆级芯片封装制程与芯片封装结构
US8749065B2 (en) * 2007-01-25 2014-06-10 Tera Probe, Inc. Semiconductor device comprising electromigration prevention film and manufacturing method thereof
US7485564B2 (en) * 2007-02-12 2009-02-03 International Business Machines Corporation Undercut-free BLM process for Pb-free and Pb-reduced C4
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US7935408B2 (en) * 2007-10-26 2011-05-03 International Business Machines Corporation Substrate anchor structure and method
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
TW200926379A (en) 2007-12-05 2009-06-16 Phoenix Prec Technology Corp Package substrate having electrical connecting structure and method of fabricating the same
US20090200675A1 (en) * 2008-02-11 2009-08-13 Thomas Goebel Passivated Copper Chip Pads
JP2009224581A (ja) 2008-03-17 2009-10-01 Sanyo Electric Co Ltd 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、電極構造、携帯機器
US7859122B2 (en) * 2008-04-14 2010-12-28 International Business Machines Corporation Final via structures for bond pad-solder ball interconnections
KR100979497B1 (ko) 2008-06-17 2010-09-01 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP2010077456A (ja) 2008-09-24 2010-04-08 Jfe Steel Corp 溶融亜鉛めっき鋼板およびその製造方法
CN101728347B (zh) 2008-10-22 2011-05-04 中芯国际集成电路制造(上海)有限公司 封装结构及其制造方法
JP2010177456A (ja) 2009-01-29 2010-08-12 Toshiba Corp 半導体デバイス
KR101534682B1 (ko) 2009-03-13 2015-07-08 삼성전자주식회사 범프에 스틱을 구비하는 반도체 장치
TWI471977B (zh) * 2009-05-15 2015-02-01 Xintec Inc 功率金氧半場效電晶體封裝體
KR20110017153A (ko) 2009-08-13 2011-02-21 삼성전기주식회사 볼 그리드 어레이 패키지 기판 및 그 제조방법
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8748305B2 (en) * 2009-11-17 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure for semiconductor devices
US8399987B2 (en) * 2009-12-04 2013-03-19 Samsung Electronics Co., Ltd. Microelectronic devices including conductive vias, conductive caps and variable thickness insulating layers
US8232137B2 (en) * 2009-12-10 2012-07-31 Intersil Americas Inc. Heat conduction for chip stacks and 3-D circuits
US8492891B2 (en) 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
US20110266670A1 (en) * 2010-04-30 2011-11-03 Luke England Wafer level chip scale package with annular reinforcement structure
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8410576B2 (en) * 2010-06-16 2013-04-02 National Semiconductor Corporation Inductive structure and method of forming the inductive structure with an attached core structure
JP5502624B2 (ja) * 2010-07-08 2014-05-28 新光電気工業株式会社 配線基板の製造方法及び配線基板
US8755196B2 (en) 2010-07-09 2014-06-17 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
JP2012054297A (ja) 2010-08-31 2012-03-15 Kyocer Slc Technologies Corp 配線基板およびその製造方法
US20120261813A1 (en) * 2011-04-15 2012-10-18 International Business Machines Corporation Reinforced via farm interconnect structure, a method of forming a reinforced via farm interconnect structure and a method of redesigning an integrated circuit chip to include such a reinforced via farm interconnect structure
US8786081B2 (en) * 2011-07-27 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for circuit routing by way of under-bump metallization
US9905524B2 (en) * 2011-07-29 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures in semiconductor device and packaging assembly
US8557684B2 (en) * 2011-08-23 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit (3DIC) formation process
US8871629B2 (en) * 2011-11-08 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of and semiconductor devices with ball strength improvement
US8508043B2 (en) * 2011-11-16 2013-08-13 International Business Machines Corporation Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump
CN102437065A (zh) 2011-12-19 2012-05-02 南通富士通微电子股份有限公司 高可靠芯片级封装方法
CN102496580B (zh) 2011-12-19 2016-02-03 南通富士通微电子股份有限公司 一种焊料凸点的形成方法
CN102437066A (zh) 2011-12-19 2012-05-02 南通富士通微电子股份有限公司 一种高可靠圆片级柱状凸点封装方法
US8963316B2 (en) * 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8629557B2 (en) * 2012-03-08 2014-01-14 International Business Machines Corporation Structures and methods for detecting solder wetting of pedestal sidewalls
CN102664174A (zh) 2012-04-19 2012-09-12 日月光半导体制造股份有限公司 半导体封装构造
US8741691B2 (en) * 2012-04-20 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating three dimensional integrated circuit
US8653662B2 (en) * 2012-05-02 2014-02-18 International Business Machines Corporation Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits
US8865585B2 (en) * 2012-07-11 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming post passivation interconnects
KR101960686B1 (ko) * 2012-08-10 2019-03-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9275924B2 (en) * 2012-08-14 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having a recess filled with a molding compound
US9006101B2 (en) * 2012-08-31 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
US9112007B2 (en) * 2012-09-14 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Through via structure and method
CN102915985B (zh) 2012-10-09 2015-06-03 天津大学 一种功率电子器件双面粘接结构及制备方法
JP6024400B2 (ja) * 2012-11-07 2016-11-16 ソニー株式会社 半導体装置、半導体装置の製造方法、及びアンテナスイッチモジュール
CN102931098B (zh) 2012-11-08 2015-06-03 南通富士通微电子股份有限公司 芯片封装方法
CN202917476U (zh) 2012-11-08 2013-05-01 南通富士通微电子股份有限公司 芯片封装结构
CN203013710U (zh) 2012-11-08 2013-06-19 南通富士通微电子股份有限公司 半导体器件的封装件
CN102931158B (zh) 2012-11-08 2015-12-09 南通富士通微电子股份有限公司 芯片封装结构
CN102931101B (zh) 2012-11-08 2016-03-30 南通富士通微电子股份有限公司 芯片封装方法
CN102931110B (zh) 2012-11-08 2015-07-08 南通富士通微电子股份有限公司 半导体器件的封装方法
CN202917475U (zh) 2012-11-08 2013-05-01 南通富士通微电子股份有限公司 芯片封装结构
CN102931164B (zh) 2012-11-08 2015-12-09 南通富士通微电子股份有限公司 半导体器件的封装件
US9773732B2 (en) * 2013-03-06 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for packaging pad structure
US8969191B2 (en) * 2013-07-16 2015-03-03 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure
US9252110B2 (en) * 2014-01-17 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming same
US9209131B2 (en) * 2014-01-21 2015-12-08 Qualcomm Incorporated Toroid inductor in redistribution layers (RDL) of an integrated device
US20150214127A1 (en) * 2014-01-24 2015-07-30 Qualcomm Incorporated Integrated device comprising a substrate with aligning trench and/or cooling cavity

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080048337A1 (en) * 2006-08-25 2008-02-28 Nec Electronics Corporation Semiconductor device including through electrode and method of manufacturing the same
US20090098723A1 (en) * 2007-10-13 2009-04-16 Wan-Ling Yu Method Of Forming Metallic Bump On I/O Pad
US20120086124A1 (en) * 2010-10-06 2012-04-12 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
CN102270590A (zh) * 2011-09-01 2011-12-07 苏州晶方半导体科技股份有限公司 晶圆级封装结构及封装方法
CN102915982A (zh) * 2012-11-08 2013-02-06 南通富士通微电子股份有限公司 半导体器件
CN102931099A (zh) * 2012-11-08 2013-02-13 南通富士通微电子股份有限公司 半导体器件的形成方法
CN202917483U (zh) * 2012-11-08 2013-05-01 南通富士通微电子股份有限公司 半导体器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210035938A1 (en) * 2011-07-27 2021-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Bump structure having a side recess and semiconductor structure including the same
US11631648B2 (en) * 2011-07-27 2023-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure having a side recess and semiconductor structure including the same

Also Published As

Publication number Publication date
US9548282B2 (en) 2017-01-17
US20150287688A1 (en) 2015-10-08

Similar Documents

Publication Publication Date Title
WO2014071815A1 (zh) 半导体器件及其形成方法
US9397080B2 (en) Package on package devices and methods of packaging semiconductor dies
US8686560B2 (en) Wafer-level chip-scale package device having bump assemblies configured to mitigate failures due to stress
US9761549B2 (en) Semiconductor device and fabrication method
TW201906029A (zh) 半導體封裝及其製造方法
TWI497669B (zh) 形成於半導體基板上之導電凸塊及其製法
CN102915982B (zh) 半导体器件
US9721912B2 (en) Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionality
TW201724357A (zh) 整合扇出結構及其形成方法
CN102931109B (zh) 半导体器件的形成方法
TWI821704B (zh) 偏心接合結構及其製造方法
TW201640590A (zh) 電子封裝件及其製法
CN202917483U (zh) 半导体器件
TWI811752B (zh) 半導體結構及其製造方法
CN115579341A (zh) 半导体器件和形成半导体器件方法
TWI731773B (zh) 半導體封裝體及其形成方法
CN102931099A (zh) 半导体器件的形成方法
TWI455271B (zh) 半導體元件結構及其製法
TWI669793B (zh) 基板結構
WO2021103489A1 (zh) 半导体结构及其制造方法
CN102969344A (zh) 半导体器件
US10804233B1 (en) Wafer-level chip-scale package device having bump assemblies configured to maintain standoff height
TWI807827B (zh) 電子封裝件及其製法
US20230402345A1 (en) Semiconductor Package and Method
TWI501362B (zh) 多形體銅柱凸塊接合結構及其凸塊形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13853990

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14440872

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13853990

Country of ref document: EP

Kind code of ref document: A1