JP3929966B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP3929966B2 JP3929966B2 JP2003393695A JP2003393695A JP3929966B2 JP 3929966 B2 JP3929966 B2 JP 3929966B2 JP 2003393695 A JP2003393695 A JP 2003393695A JP 2003393695 A JP2003393695 A JP 2003393695A JP 3929966 B2 JP3929966 B2 JP 3929966B2
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
11…半導体基板(シリコン基板)、
12…電極パッド(各デバイスの配線層の一部分)、
13…パッシベーション膜(SiN層又はPSG層)、
14…絶縁膜(ポリイミド樹脂層)、
15…金属薄膜(給電層/めっきベース膜)、
16…導体層(再配線層/再配線パターン)、
17…メタルポスト(Cuポスト)、
18…バリヤメタル層、
19…メタル層(W層、Mo層など)、
20…封止樹脂層、
21…外部接続端子(はんだバンプ)、
30…半導体ウエハ(シリコンウエハ)、
BL…ダイサーのブレード、
R1,R2…レジスト層(めっきレジスト)、
VH…開口部(ビアホール)。
Claims (4)
- シリコンからなる半導体ウエハの複数のデバイスが作り込まれている側の表面に、各デバイスの電極パッドが露出する開口部を有するように絶縁膜を形成する工程と、
次いで、該絶縁膜上に、前記電極パッドが露出する開口部を覆うように所要の形状にパターニングされた導体層を形成する工程と、
次いで、該導体層上に、該導体層の端子形成部分が露出する開口部を有するようにレジスト層を形成する工程と、
次いで、該レジスト層をマスクにして前記導体層の端子形成部分にメタルポストを形成する工程と、
次いで、前記半導体ウエハの前記メタルポストが形成されている側と反対側の面を研削して、所定の厚さになるまで薄化する工程と、
次いで、前記レジスト層を除去した後、前記半導体ウエハの薄化された面に、直接、当該半導体ウエハの線膨張係数に近い線膨張係数を有するモリブデンからなるメタル層を形成する工程と、
次いで、前記メタルポストの頂上部を露出させて封止樹脂でウエハ表面を封止する工程と、
次いで、前記メタルポストの頂上部に金属バンプを接合する工程と、
次いで、該金属バンプが接合された半導体ウエハを前記各デバイス単位に分割する工程とを含むことを特徴とする半導体装置の製造方法。 - 前記メタル層をスパッタリング又は蒸着により形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記メタルポストを形成する工程において、該メタルポストを形成した後、更に該メタルポストの頂上部にバリヤメタル層を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 請求項1に記載された半導体装置の製造方法により製造された半導体装置。
Priority Applications (6)
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JP2003393695A JP3929966B2 (ja) | 2003-11-25 | 2003-11-25 | 半導体装置及びその製造方法 |
TW093135090A TWI371061B (en) | 2003-11-25 | 2004-11-16 | Semiconductor device and method of fabricating the same |
US10/988,508 US7417311B2 (en) | 2003-11-25 | 2004-11-16 | Semiconductor device and method of fabricating the same |
KR1020040096894A KR101043313B1 (ko) | 2003-11-25 | 2004-11-24 | 반도체 장치 및 그 제조 방법 |
CNB2004100960178A CN100375232C (zh) | 2003-11-25 | 2004-11-25 | 半导体器件及其制造方法 |
US11/546,285 US7468292B2 (en) | 2003-11-25 | 2006-10-12 | Method of making wafer level package structure by grinding the backside thereof and then forming metal layer on the ground side |
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JP2003393695A JP3929966B2 (ja) | 2003-11-25 | 2003-11-25 | 半導体装置及びその製造方法 |
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JP3929966B2 true JP3929966B2 (ja) | 2007-06-13 |
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US (2) | US7417311B2 (ja) |
JP (1) | JP3929966B2 (ja) |
KR (1) | KR101043313B1 (ja) |
CN (1) | CN100375232C (ja) |
TW (1) | TWI371061B (ja) |
Families Citing this family (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006008795A1 (ja) * | 2004-07-16 | 2006-01-26 | Shinko Electric Industries Co., Ltd. | 半導体装置の製造方法 |
US20060160346A1 (en) * | 2005-01-19 | 2006-07-20 | Intel Corporation | Substrate bump formation |
US7468545B2 (en) * | 2005-05-06 | 2008-12-23 | Megica Corporation | Post passivation structure for a semiconductor device and packaging process for same |
US7582556B2 (en) * | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
US7358616B2 (en) * | 2005-09-14 | 2008-04-15 | Freescale Semiconductor, Inc. | Semiconductor stacked die/wafer configuration and packaging and method thereof |
JP2007123578A (ja) * | 2005-10-28 | 2007-05-17 | Fujikura Ltd | 半導体装置及びその製造方法 |
KR100703012B1 (ko) * | 2006-01-24 | 2007-04-09 | 삼성전자주식회사 | 반도체 패키지, 반도체 스택 패키지, 패키지들을 제조하는방법 |
JP2007250849A (ja) * | 2006-03-16 | 2007-09-27 | Casio Comput Co Ltd | 半導体装置の製造方法 |
JP2007311540A (ja) * | 2006-05-18 | 2007-11-29 | Renesas Technology Corp | 半導体装置の製造方法 |
US20080003780A1 (en) * | 2006-06-30 | 2008-01-03 | Haixiao Sun | Detachable stiffener for ultra-thin die |
JP4219951B2 (ja) * | 2006-10-25 | 2009-02-04 | 新光電気工業株式会社 | はんだボール搭載方法及びはんだボール搭載基板の製造方法 |
JP4121542B1 (ja) * | 2007-06-18 | 2008-07-23 | 新光電気工業株式会社 | 電子装置の製造方法 |
JP4121543B1 (ja) | 2007-06-18 | 2008-07-23 | 新光電気工業株式会社 | 電子装置 |
KR100854221B1 (ko) | 2007-08-27 | 2008-08-25 | 주식회사 동부하이텍 | 반도체 디바이스의 제조 방법 |
US8492263B2 (en) | 2007-11-16 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protected solder ball joints in wafer level chip-scale packaging |
KR100959604B1 (ko) * | 2008-03-10 | 2010-05-27 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 반도체 패키지 및 이의 제조 방법 |
JP2010056266A (ja) * | 2008-08-28 | 2010-03-11 | Casio Comput Co Ltd | 半導体装置の製造方法 |
TW201011830A (en) * | 2008-09-03 | 2010-03-16 | United Test Ct Inc | Self-adhesive semiconductor wafer |
KR101026427B1 (ko) * | 2009-01-12 | 2011-04-07 | 삼성전기주식회사 | 웨이퍼 레벨 패키지 및 그 제조방법 |
US8309396B2 (en) | 2009-01-26 | 2012-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for 3D integrated circuit stacking |
KR20100104377A (ko) * | 2009-03-17 | 2010-09-29 | 삼성전자주식회사 | 내부 스트레스를 줄일 수 있는 반도체 패키지 |
US8592995B2 (en) * | 2009-07-02 | 2013-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump |
US8803319B2 (en) | 2010-02-11 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
US8318596B2 (en) * | 2010-02-11 | 2012-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
JP2011171567A (ja) | 2010-02-19 | 2011-09-01 | Elpida Memory Inc | 基板構造物の製造方法及び半導体装置の製造方法 |
US8264089B2 (en) * | 2010-03-17 | 2012-09-11 | Maxim Integrated Products, Inc. | Enhanced WLP for superior temp cycling, drop test and high current applications |
TWI419284B (zh) * | 2010-05-26 | 2013-12-11 | Chipmos Technologies Inc | 晶片之凸塊結構及凸塊結構之製造方法 |
WO2011156228A2 (en) | 2010-06-08 | 2011-12-15 | Henkel Corporation | Coating adhesives onto dicing before grinding and micro-fabricated wafers |
TWI456012B (zh) | 2010-06-08 | 2014-10-11 | Henkel IP & Holding GmbH | 使用脈衝式uv光源之晶圓背面塗覆方法 |
JP2012069747A (ja) * | 2010-09-24 | 2012-04-05 | Teramikros Inc | 半導体装置およびその製造方法 |
EP2671249A4 (en) | 2011-02-01 | 2015-10-07 | Henkel IP & Holding GmbH | FILLING FILM APPLIED TO A PRE-CUTTING WAFER |
EP2671248A4 (en) | 2011-02-01 | 2015-10-07 | Henkel Corp | ON A PRECUTED WAFER APPLIED FILM ON A DICING TAPE |
JP2012256679A (ja) | 2011-06-08 | 2012-12-27 | Elpida Memory Inc | 半導体装置及びその製造方法 |
CN102244021B (zh) * | 2011-07-18 | 2013-05-01 | 江阴长电先进封装有限公司 | Low-k芯片封装方法 |
TWI509678B (zh) * | 2011-07-27 | 2015-11-21 | Inpaq Technology Co Ltd | 平面式半導體元件及其製作方法 |
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US9230932B2 (en) | 2012-02-09 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect crack arrestor structure and methods |
JP5128712B1 (ja) * | 2012-04-13 | 2013-01-23 | ラピスセミコンダクタ株式会社 | 半導体装置 |
US9515036B2 (en) | 2012-04-20 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for solder connections |
CN102818516B (zh) * | 2012-08-30 | 2015-03-11 | 无锡永阳电子科技有限公司 | 耐高温硅应变计传感器芯片及其制作方法 |
WO2014071815A1 (zh) | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | 半导体器件及其形成方法 |
US9761549B2 (en) | 2012-11-08 | 2017-09-12 | Tongfu Microelectronics Co., Ltd. | Semiconductor device and fabrication method |
CN102915982B (zh) * | 2012-11-08 | 2015-03-11 | 南通富士通微电子股份有限公司 | 半导体器件 |
CN102969344B (zh) * | 2012-11-08 | 2016-09-28 | 南通富士通微电子股份有限公司 | 半导体器件 |
WO2014071813A1 (zh) | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | 半导体器件的封装件和封装方法 |
CN102915986B (zh) | 2012-11-08 | 2015-04-01 | 南通富士通微电子股份有限公司 | 芯片封装结构 |
US9000587B1 (en) * | 2013-03-12 | 2015-04-07 | Maxim Integrated Products, Inc. | Wafer-level thin chip integration |
US9704769B2 (en) | 2014-02-27 | 2017-07-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP) |
JP6509602B2 (ja) * | 2014-04-09 | 2019-05-08 | ローム株式会社 | 半導体装置 |
CN104952743A (zh) * | 2015-05-19 | 2015-09-30 | 南通富士通微电子股份有限公司 | 晶圆级芯片封装方法 |
CN107492528A (zh) * | 2016-06-13 | 2017-12-19 | 恩智浦美国有限公司 | 具有石墨烯条带的柔性半导体装置 |
JP6885701B2 (ja) * | 2016-10-17 | 2021-06-16 | ローム株式会社 | 半導体装置 |
JP2018170333A (ja) | 2017-03-29 | 2018-11-01 | 株式会社東芝 | 半導体装置及びその製造方法 |
US10510634B2 (en) * | 2017-11-30 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method |
US10991660B2 (en) * | 2017-12-20 | 2021-04-27 | Alpha Anc Omega Semiconductor (Cayman) Ltd. | Semiconductor package having high mechanical strength |
CN112447532B (zh) * | 2019-08-29 | 2022-08-19 | 珠海格力电器股份有限公司 | 一种封装方法 |
CN112951755B (zh) * | 2021-01-25 | 2023-06-13 | 北京航天微电科技有限公司 | 用于声表面波滤波器中磁控溅射的剥离方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5990545A (en) * | 1996-12-02 | 1999-11-23 | 3M Innovative Properties Company | Chip scale ball grid array for integrated circuit package |
JPH10177974A (ja) | 1996-12-18 | 1998-06-30 | Nippon Steel Corp | ヘテロエピタキシャルウェハ上のデバイスチップ製造方法 |
US6479900B1 (en) * | 1998-12-22 | 2002-11-12 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP3439144B2 (ja) | 1998-12-22 | 2003-08-25 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
US6329288B1 (en) * | 1999-01-25 | 2001-12-11 | Sanyo Eelctric Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2000228412A (ja) | 1999-02-05 | 2000-08-15 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2001053041A (ja) * | 1999-08-11 | 2001-02-23 | Nippon Sheet Glass Co Ltd | 半導体ウェハ裏面加工時の表面保護方法および半導体ウェハの保持方法 |
JP3770007B2 (ja) | 1999-11-01 | 2006-04-26 | 凸版印刷株式会社 | 半導体装置の製造方法 |
JP4376388B2 (ja) | 1999-12-13 | 2009-12-02 | パナソニック株式会社 | 半導体装置 |
JP2001210761A (ja) * | 2000-01-24 | 2001-08-03 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6392290B1 (en) * | 2000-04-07 | 2002-05-21 | Siliconix Incorporated | Vertical structure for semiconductor wafer-level chip scale packages |
JP3459234B2 (ja) | 2001-02-01 | 2003-10-20 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP2002270720A (ja) | 2001-03-09 | 2002-09-20 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
TWI249828B (en) * | 2001-08-07 | 2006-02-21 | Advanced Semiconductor Eng | Packaging structure for semiconductor chip and the manufacturing method thereof |
US6794273B2 (en) * | 2002-05-24 | 2004-09-21 | Fujitsu Limited | Semiconductor device and manufacturing method thereof |
US7358618B2 (en) * | 2002-07-15 | 2008-04-15 | Rohm Co., Ltd. | Semiconductor device and manufacturing method thereof |
-
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TWI371061B (en) | 2012-08-21 |
US20070032066A1 (en) | 2007-02-08 |
CN100375232C (zh) | 2008-03-12 |
CN1630029A (zh) | 2005-06-22 |
KR101043313B1 (ko) | 2011-06-22 |
US7417311B2 (en) | 2008-08-26 |
US20050112800A1 (en) | 2005-05-26 |
KR20050050570A (ko) | 2005-05-31 |
TW200524025A (en) | 2005-07-16 |
JP2005158929A (ja) | 2005-06-16 |
US7468292B2 (en) | 2008-12-23 |
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