WO2014071813A1 - 半导体器件的封装件和封装方法 - Google Patents

半导体器件的封装件和封装方法 Download PDF

Info

Publication number
WO2014071813A1
WO2014071813A1 PCT/CN2013/086210 CN2013086210W WO2014071813A1 WO 2014071813 A1 WO2014071813 A1 WO 2014071813A1 CN 2013086210 W CN2013086210 W CN 2013086210W WO 2014071813 A1 WO2014071813 A1 WO 2014071813A1
Authority
WO
WIPO (PCT)
Prior art keywords
bump
semiconductor device
pad
layer
solder ball
Prior art date
Application number
PCT/CN2013/086210
Other languages
English (en)
French (fr)
Inventor
林仲珉
石磊
王洪辉
Original Assignee
南通富士通微电子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201210445562.8A external-priority patent/CN102931164B/zh
Priority claimed from CN201210444454.9A external-priority patent/CN102931110B/zh
Application filed by 南通富士通微电子股份有限公司 filed Critical 南通富士通微电子股份有限公司
Priority to US14/440,876 priority Critical patent/US9379077B2/en
Publication of WO2014071813A1 publication Critical patent/WO2014071813A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1161—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H01L2224/11903—Multiple masking steps using different masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H01L2224/78302—Shape
    • H01L2224/78303—Shape of the pressing surface, e.g. tip or head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Definitions

  • the present invention relates to the field of semiconductor manufacturing technology, and in particular, to a package and a package method for a semiconductor device.
  • a package is a process in which a device or circuit is loaded into a protective case.
  • the package is critical to the semiconductor chip because the semiconductor chip must be isolated from the outside to prevent the impurities in the air from corroding the circuit of the semiconductor chip, resulting in a decrease in electrical performance.
  • the packaged semiconductor chip is also advantageous for installation and transportation.
  • a chip 100 is provided, and an integrated circuit and a pad 101 electrically connected to the integrated circuit are formed on the surface of the chip 100;
  • a passivation layer 103 is formed on the surface of the chip 100, and the passivation layer 103 has an opening 105 exposing the pad 101;
  • solder balls 107 are formed on the surface of the pad 101 through the opening 105 (shown in FIG. 2).
  • the performance of the package of the semiconductor device formed by the prior art is unstable, and a short circuit phenomenon is apt to occur.
  • the problem to be solved by the present invention is to provide a package of a semiconductor device in which the package of the formed semiconductor device has stable performance and is not easily short-circuited.
  • the present invention provides a packaging method of a semiconductor device, comprising: providing a chip having a pad on a surface; forming a passivation layer and a bump on a surface of the chip, the passivation layer having an exposed portion An opening of the pad, the bump being located within the opening and having a size smaller than the opening Dimensions; forming a solder ball covering the surface of the bump and covering the surface of the bottom pad of the opening.
  • the method further includes: forming a diffusion prevention layer covering the surface of the bump before forming the solder ball.
  • the anti-diffusion layer further covers the pad at the bottom of the opening.
  • the method further includes: forming a wetting layer covering the anti-diffusion layer.
  • the forming process of the wetting layer is an electroless plating process, and the material of the wetting layer includes at least a tin element, a gold element or a silver element.
  • the forming process of the bumps is a wire bonding process.
  • the formed bump comprises a plurality of stacked sub-bumps, and each of the formed sub-bumps is flattened after each wire bonding process.
  • the formed bump comprises a plurality of stacked sub-bumps
  • the sub-bump at the top comprises a sub-bump body and a sub-bump tail located on the surface of the sub-bump body.
  • the material of the bump is copper, gold, silver, copper alloy, gold alloy or silver alloy
  • the material of the solder ball is tin or tin alloy
  • the present invention further provides a package for a semiconductor device formed by the above method, comprising: a chip having a pad on a surface thereof; a passivation layer on a surface of the chip, the passivation layer having An opening, the opening exposing a portion of the pad; a bump on the surface of the pad, the size of the bump being smaller than a size of the opening; and a surface covering the surface of the bump and covering the surface of the bottom pad of the opening ball.
  • the method further includes: a diffusion prevention layer covering the top and the sidewall of the bump, the solder ball being located on the surface of the diffusion prevention layer.
  • the anti-diffusion layer further covers the pad at the bottom of the opening.
  • the material of the anti-diffusion layer is nickel.
  • the method further includes: a wetting layer covering the diffusion prevention layer, the solder ball being located on the surface of the wetting layer.
  • the material of the wetting layer includes at least a tin element, a gold element or a silver element.
  • the bump comprises a single or a plurality of stacked sub-bumps.
  • the bump comprises a plurality of stacked sub-bumps, and the sub-bumps at the top comprise a sub-bump body and a sub-bump tail located on the surface of the sub-bump body.
  • the material of the bump is copper, gold, silver, a copper alloy, a gold alloy or a silver alloy, and the material of the solder ball is tin or a tin alloy.
  • the technical solution of the present invention has the following advantages:
  • solder balls are formed on the bumps, which are affected by gravity, wetting force and surface tension, and the gap between adjacent solder balls is increased, and the package of the subsequently formed semiconductor device is less prone to short circuit, and the device performance is stable.
  • the size of the formed bump is smaller than the size of the opening, and when the solder ball is subsequently formed, the solder ball covers not only the top of the bump but also the sidewall of the bump and the bottom of the opening.
  • the bottom of the solder ball forms a skirt-like structure, which effectively increases the contact area between the solder ball and the bump, thereby increasing the bonding force of the two, increasing the bonding strength of the solder ball, and improving the packaging of the semiconductor device. Performance and yield.
  • the method further includes: forming an anti-diffusion layer covering the top of the bump, the sidewall and the bottom of the opening, and a wetting layer covering the anti-diffusion layer.
  • the anti-diffusion layer effectively prevents the formation of the interface alloy compound
  • the wetting layer effectively prevents oxidation of the anti-diffusion layer, and improves the bonding strength between the solder ball and the anti-diffusion layer, thereby further improving the package of the semiconductor device. Performance and yield.
  • FIGS. 5 to 7 are first embodiments of the present invention.
  • FIGS. 9 to 12 are schematic cross-sectional views showing a packaging process of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 13 is a flow chart showing a method of packaging a semiconductor device according to a third embodiment of the present invention.
  • FIGS. 14 to 16 are schematic cross-sectional views showing a packaging process of a semiconductor device according to a third embodiment of the present invention.
  • Fig. 17 is a flow chart showing a method of packaging a semiconductor device according to a fourth embodiment of the present invention.
  • Figs. 18 to 20 are schematic cross-sectional views showing a packaging process of a semiconductor device according to a fourth embodiment of the present invention.
  • the performance of the package of the semiconductor device formed by the prior art is unstable, and the phenomenon of short circuit is apt to occur. It has been found that the prior art directly forms solder balls on the surface of the pad, and the solder balls formed are generally hemispherical, and the diameter of the solder balls is large, resulting in a small gap between adjacent solder balls, and the gap is relatively small. Small solder balls are prone to short circuits, which affect the stability of the package of the semiconductor device.
  • a bump is formed on the surface of the pad, and then a solder ball is formed on the surface of the bump, which is affected by gravity, wettability and surface tension, and tin forming the solder ball is along the sidewall of the bump.
  • the solder ball transitions from a hemispherical shape to a spherical shape, and the solder balls formed of the same quality of solder have a smaller diameter than the prior art, which helps to increase the gap between adjacent solder balls.
  • the solder ball covers only the top of the bump, the bonding force of the two may not be sufficient, and the solder ball is easily kicked off during subsequent kicking experiments, affecting the yield of the package of the semiconductor device.
  • solder ball covers the top and the sidewall of the bump and covers a part of the pad
  • the contact area between the solder ball and the bump increases, and the bonding force of the two increases
  • the solder ball Covering part of the pad further increases the bonding force between the solder ball and the bump and the pad, and can effectively improve the yield of the package of the semiconductor device.
  • a method for packaging a semiconductor device includes: Step S201: providing a chip having a pad on a surface thereof, a surface of the chip is formed with a passivation layer, and the passivation layer has an exposed portion An opening in the surface of the pad;
  • Step S202 forming a bump on the surface of the pad in the opening, the size of the bump being smaller than the size of the opening;
  • Step S203 forming a solder ball covering the surface of the bump and covering the surface of the bottom pad of the opening.
  • FIG. 5 to FIG. 8 and FIG. 5 to FIG. 8 are schematic cross-sectional structural views showing a packaging process of the semiconductor device according to the first embodiment of the present invention.
  • a chip 300 having a pad 301 having a passivation layer 303 having an opening 305 exposing a portion of the pad 301 is formed on the surface of the chip 300.
  • the chip 300 is used to provide a working platform for subsequent packaging processes.
  • the surface of the chip 300 also has an integrated circuit electrically connected to the pad 301, which is designed to meet different functional requirements, and the integrated circuit transmits an electrical signal to the outside through a pad 301 electrically connected thereto.
  • the circuit and pad 301 are formed by etching a wiring metal layer deposited on the surface of the chip 300.
  • the integrated circuit and the pad 301 are formed in the same process step, and the material of the integrated circuit and the pad 301 is made of metal such as gold, silver or copper. Since the process of forming the integrated circuit and the pad 301 is well known to those skilled in the art, no further details are provided herein.
  • the three materials of gold, silver and copper have better wettability with tin or tin alloy parts, and when the material of the pad 301 is gold, silver or copper, In the subsequent process, the solder ball is more likely to cover the surface of the pad 301, and the solder ball has better infiltration and bonding performance.
  • the material of the passivation layer 303 is silicon oxide, silicon nitride or the like for isolating the integrated circuit and protecting the pad 301 from being damaged or oxidized in a subsequent process.
  • the formation process of the passivation layer 303 is a deposition process such as a chemical vapor deposition process. Since the process of forming the passivation layer 303 is well known to those skilled in the art, it will not be described again.
  • the passivation layer 303 has an opening 305 therein that exposes the surface of the pad 301 for providing a process window for subsequently forming bumps on the surface of the pad 301.
  • the formation process of the opening 305 is an etching process, such as an anisotropic dry etching process.
  • the size of the pad 301 is larger than the size of the opening 305.
  • a bump 307 on the surface of the pad 301 is formed through the opening 305, and the size of the bump 307 is smaller than the size of the opening 305.
  • solder balls 107 shown in FIG. 3
  • the surface of the pad 101 shown in FIG. 3
  • the gap is small, and a short circuit between the solder balls 107 having a small gap is likely to occur, which affects the stability of the semiconductor device.
  • a bump 307 is formed on the surface of the pad 301, and then a solder ball is formed on the surface of the bump 307 when the solder ball is formed on the surface of the bump 307. Helps increase the gap between adjacent solder balls.
  • the material of the bump 307 is copper, gold, silver, copper alloy, silver alloy or gold alloy with good thermal conductivity, and the surface of the bump 307 is used to form a solder ball having a smaller diameter.
  • the material of the bump 307 is copper, the cost is lower, and the conductivity is better, and the quality of the bump 307 formed is better.
  • the formation process of the bumps 307 is a wire bonding process such as thermocompression bonding, ultrasonic bonding or thermosonic bonding. Due to the original interface between the bumps 307 formed by the wire bonding process and the pads 301 Almost close to the range of atomic forces, the two metal atoms diffuse and the two combine more firmly.
  • the thermal kinetic bonding process is used to form the bumps 307, which enhances the interdiffusion and molecular (atomic) interaction between the original interfaces between the metals, and the diffusion of the metal is performed on the entire interface to realize the bumps. With the high quality soldering of 307, the formed bumps 307 are more firmly bonded to the pads 301 and form a process cartridge.
  • the wire bonding process further includes: introducing a nitrogen gas having a volume fraction of 95% and a hydrogen gas having a volume fraction of 5%. .
  • the file used in the wire bonding process is wedge-shaped or spherical.
  • the boring tool is spherical, which is advantageous for forming the columnar bumps 307.
  • the bumps 307 may also be formed by an electroplating process or by a deposition process and an etching process to form a dimensionally accurate bump 307, which will not be described herein.
  • the size W1 of the bump 307 is smaller than the dimension W2 of the opening 305 for subsequently forming a solder ball that covers the top and sidewall of the bump 307 and the bottom pad 301 of the opening 305 to increase the solder ball and the bump.
  • the cross-sectional shape of the bump 307 along the surface of the chip is circular, elliptical, square or triangular.
  • the dimension W1 of the bump 307 and the dimension W2 of the opening 305 refer to in the embodiment. It is the length shown in FIG. 7 parallel to the surface direction of the chip 300.
  • solder ball 311 covering the surface of the bump 307 and covering the surface of the bottom pad 301 of the opening 305 is formed.
  • the material of the solder ball 311 is tin or a tin alloy.
  • the forming process of the solder ball 311 is a ball bonding process and a reflow soldering process, or a printing process and a reflow soldering process. Since the dimension W1 of the bump 307 is smaller than the dimension W2 of the opening 305, the molten tin is contracted into a spherical structure by the surface tension during the reflow process, and is distributed on the surface of the metal material, that is, the pad 301 covering the bottom of the opening 305. The bottom of the opening 305 forms a skirt structure (ankor shape).
  • the solder ball 311 covers the surface of the bump 307 (including the top surface and the side surface), and covers the surface of the pad 301 at the bottom of the opening 305, the solder ball 311 and the bump 307, and the opening 305 bottom pad.
  • the contact surface of 301 is increased, and the lateral and longitudinal tensile forces are larger, which increases the bonding strength of the solder balls 311.
  • the diameter of the formed solder balls 311 is further reduced, increasing the gap between adjacent solder balls 311, The stability of the package of the semiconductor device is further improved.
  • the bumps 307 are formed by a wire bonding process to form a process cartridge, and the bonding between the bumps 307 and the pads 301 is stronger. Moreover, since the size W1 of the bump 307 is smaller than the dimension W2 of the opening 305, when the solder ball 311 is subsequently formed, the solder ball 311 covers the top of the bump 307, the sidewall, and the bottom of the opening 305 due to gravity and surface tension. The contact surface of the pad 301 and the solder ball 311 with the bump 307 and the pad 301 is increased, the bonding strength of the solder ball 311 is increased, and the diameter of the formed solder ball 311 is small, and the adjacent solder ball 311 is increased. The gap further improves the stability of the package of the semiconductor device.
  • the package of the semiconductor device formed in the first embodiment of the present invention includes: a chip 300 having a pad 301 on the surface of the chip; and a passivation layer 303 located on the surface of the chip.
  • the passivation layer 303 has an opening 305 exposing a portion of the pad 301; a bump 307 on the surface of the pad 301, the bump 307 having a size smaller than the size of the opening 305;
  • the surface of the bump 307 covers the surface of the solder ball 311 at the bottom of the opening 305.
  • the size of the pad 301 is the same as the size of the opening 305.
  • the material of the pad 301 is gold, silver or copper.
  • the material of the bump 307 is copper, gold and silver with good thermal conductivity. In the embodiment of the present invention, the material of the bump 307 is copper, the cost is low, and the quality is good; the material of the solder ball 311 is tin or tin alloy, adjacent The gap between the solder balls 311 is small.
  • the material of the bump 307 is copper, the cost is low, and the conductivity of the copper is better, and the quality of the bump layer 307 is good.
  • the solder ball 311 covers not only the surface of the top of the bump 307 but also the side surface of the bump 307 and the surface of the bottom pad 301 of the opening 305.
  • the diameter of the solder ball 311 is small, which increases the gap between the adjacent solder balls 311.
  • the contact area of the solder ball 311 is larger, and the lateral and longitudinal tensile forces are larger, the bonding strength of the solder ball 311 is improved, and the solder ball 311 is less likely to peel off, further increasing the stability of the package of the semiconductor device.
  • a method for packaging a semiconductor device includes: Step S401, providing a surface having a pad chip, a surface of the chip is formed with a passivation layer, and the passivation layer is exposed Opening an opening on a portion of the pad surface;
  • Step S402 forming a bump on the surface of the pad in the opening, the size of the bump being smaller than the size of the opening;
  • Step S403 forming an anti-diffusion layer covering the surface of the bump
  • Step S404 forming a wetting layer covering the anti-diffusion layer
  • Step S405 forming a solder ball covering the wetting layer and covering the surface of the bottom pad of the opening.
  • FIG. 9 to FIG. 12 are schematic cross-sectional structural views showing a packaging process of a semiconductor device according to a second embodiment of the present invention.
  • a chip 500 having a surface having a pad 501 is formed.
  • the surface of the chip 500 is formed with a passivation layer 503 having an opening 505 exposing a surface of a portion of the pad 501.
  • a bump 507 is formed on the surface of the pad 501, and the size of the bump 507 is smaller than the size of the opening 505.
  • the material of the bump 507 is copper to reduce the cost and improve the quality of the bump 507.
  • a diffusion prevention layer 513 covering the top and side walls of the bumps 507 is formed.
  • the method further includes: forming a diffusion prevention layer 513 covering the top and sidewalls of the bump 507 for preventing interdiffusion of copper atoms and tin atoms.
  • the material of the diffusion prevention layer 513 is nickel for preventing mutual diffusion of copper atoms in the bumps 507 and tin atoms in the solder balls. Further, in order to effectively prevent mutual diffusion of copper atoms in the bumps 507 and tin atoms in the solder balls, the anti-diffusion layer 513 has a thickness of 0.05 ⁇ m to 10 ⁇ m, preferably 0.5 ⁇ m to 5 ⁇ m. In the embodiment of the present invention, the material of the anti-diffusion layer 513 is nickel tin, and the anti-diffusion layer 513 has a thickness of 1 micrometer to 3 micrometers, for example, 3 micrometers, which preferably prevents copper atoms and tin atoms. The mutual diffusion also meets the requirements of highly integrated.
  • the forming step of the anti-diffusion layer 513 includes: forming a cover blunt a diffusion preventing film (not shown) of the top layer and the sidewall of the pad 501, the pad 501, and the bump 507; forming a first mask layer (not shown), the first mask layer only covering the bump a diffusion-proof film on the top and side walls of 507; etching the anti-diffusion film with the first mask layer as a mask until the pad 501 and the passivation layer 503 are exposed; After the film, the first mask layer is removed.
  • the anti-diffusion layer 513 may be formed by using other deposition and etching processes, as long as the anti-diffusion layer 513 can cover the top and sidewalls of the bump 407. No longer.
  • a wetting layer 515 covering the diffusion prevention layer 513 is formed.
  • the inventors have found that the nickel in the anti-diffusion layer 513 is easily oxidized, and the bonding force between the anti-diffusion layer 513 and the solder ball is limited, and the strength of the subsequently formed solder ball is limited, which is difficult to pass the kicking experiment. Detection. Therefore, the inventors have found that the surface of the diffusion prevention layer 513 can be used as a transition by covering the surface of the diffusion prevention layer 513 with the adhesion layer 515 having good adhesion to the diffusion prevention layer 513 and the solder ball, thereby effectively increasing the space between the solder ball and the bump 507. Combine performance.
  • the wetting layer 515 is formed immediately, and the time interval between the formation of the diffusion preventing layer 513 and the formation of the wetting layer 515 is less than 3 minutes, and the oxidation of the diffusion preventing layer 513 can be more effectively prevented.
  • the performance of the package of the semiconductor device is further improved.
  • the material of the wetting layer 515 includes at least a tin element, a gold element or a silver element, and the thickness of the wetting layer 515 is 0.05 micrometer to 3 micrometers to improve the bonding force with the diffusion preventing layer 513 and the solder ball.
  • the material of the wetting layer 515 is tin, and the thickness thereof is 1 micrometer, and the wetting layer 515 can be better combined with the solder ball of the same material for better infiltration.
  • the forming step of the wetting layer 515 includes: forming a seed film (not shown) covering the diffusion preventing layer 513, the passivation layer 503, and the pad 501; forming a second mask layer (not shown), The second mask layer covers only the seed film on the surface of the diffusion prevention layer 513; the seed film is etched by using the second mask layer as a mask until the pad 501 and the passivation layer 503 are exposed; After the seed film, the second mask layer is removed.
  • the first mask layer and the second mask are the same mask layer, and the anti-diffusion film and the seed film are etched in the same process step, which effectively saves the process steps.
  • the deposition layer 515 may be formed by other deposition and etching processes, as long as the anti-diffusion layer 513 is covered by the wetting layer 515, and no longer Narration.
  • solder layer may be formed directly on the surface of the diffusion prevention layer 513 and the bottom of the opening 505 without forming the wetting layer 515, and details are not described herein.
  • solder ball 511 covering the wetting layer 515 and covering the bottom of the opening 505 is formed.
  • the solder ball 511 covers the surface of the bump 507 and covers the surface of the pad 501 to form a structure in which the bottom portion is a skirt.
  • the solder ball 511 is in contact with the pad 501, the contact area of the solder ball 511 with the bump 507 and the pad 501 is increased, and the bonding force between the solder ball 511 and the pad 501 is increased, which is advantageous for improving the strength of the solder ball 511. .
  • solder ball 511 For the formation process of the solder ball 511, refer to the related description of the first embodiment of the present invention, and details are not described herein again.
  • the fabrication of the semiconductor device of the second embodiment of the present invention is completed.
  • the diffusion preventing layer 513 and the wetting layer 515 are formed on the surface of the bump 507 before the formation of the solder ball 511, the tin and the bump in the solder ball 511 are effectively prevented.
  • the copper in 507 is mutually diffused, the strength of the solder ball 511 is increased, and the stability of the formed package of the semiconductor device is further improved.
  • the inventors further provide a package for a semiconductor device, including: a chip 500 having a pad 501 on the surface of the chip; a passivation layer 503 on a surface of the chip 500,
  • the passivation layer 503 has an opening 505 exposing a portion of the pad 501; a bump 507 located on a surface of the pad 501, the bump 507 having a size smaller than a size of the opening 505; covering the protrusion a diffusion preventing layer 513 on the surface of the dot 507; a wetting layer 515 covering the diffusion preventing layer 513; and a solder ball 511 covering the wetting layer 515 and the bottom of the opening 505.
  • the material of the anti-diffusion layer 513 is nickel for preventing mutual diffusion of copper atoms in the bumps 507 and tin atoms in the solder balls; the anti-diffusion layer 513 has a thickness of 0.05 micrometers to 10 micrometers. Preferably, it is from 0.5 microns to 5 microns. In the second embodiment of the present invention, the material of the diffusion prevention layer 513 is nickel and has a thickness of 1 micrometer to 3 micrometers.
  • the material of the wetting layer 515 includes at least a tin element, a gold element or a silver element for preventing oxidation of the diffusion preventing layer 513 and improving its bonding force with the diffusion preventing layer 513 and the solder ball.
  • the thickness of the wetting layer 515 is from 0.05 micrometers to 3 micrometers.
  • the material of the wetting layer 515 For tin the wetting layer 515 has a thickness of 1 micron.
  • the anti-diffusion layer not only covers the surface of the bump but also covers the surface of the pad in the opening to form a skirt structure, so that the solder ball is more easily covered to the pad surface when the solder ball is formed. , further improve the strength of the solder ball.
  • a method for packaging a semiconductor device includes: Step S601: providing a chip having a pad on a surface thereof, a surface of the chip is formed with a passivation layer, and the passivation layer has an exposed portion An opening in the surface of the pad;
  • Step S602 forming a bump on the surface of the pad in the opening, the size of the bump being smaller than the size of the opening;
  • Step S603 forming an anti-diffusion layer covering the surface of the bump and covering the surface of the bottom pad of the opening;
  • Step S604 forming a wetting layer covering the anti-diffusion layer
  • Step S605 forming a solder ball covering the wetting layer.
  • FIG. 14 to FIG. 16 are schematic cross-sectional structural views showing a packaging process of a semiconductor device according to a third embodiment of the present invention.
  • a chip 700 having a surface having a pad 701 having a passivation layer 703 having an opening 705 exposing a surface of a portion of the pad 701 is provided, and the opening 705 is formed at the surface of the chip 700.
  • a bump 707 is formed on the surface of the pad 701, and the size of the bump 707 is smaller than the size of the opening 705.
  • the material of the pad 701 is aluminum, gold, silver or copper.
  • the wettability between the metal and the nickel is good.
  • the anti-diffusion layer 713 of the nickel alloy is formed subsequently, the anti-diffusion layer 713 is more easily covered. Pad 701 surface.
  • the anti-diffusion layer 713 covering the surface of the bump 707 and covering the surface of the pad 701 at the bottom of the opening 705 is formed.
  • the inventors have found that metal atoms between the tin in the subsequent solder balls and the pads 701 are also diffused. Therefore, unlike the second embodiment, the anti-diffusion layer 713 covers the top and side walls of the bump 707. Further, the surface of the pad 701 is also covered to prevent the tin in the solder ball from diffusing with the metal atoms in the pad 701 to form an interface alloy complex. The strength of the solder ball is further improved.
  • the material of the anti-diffusion layer 713 is nickel, and the forming process is preferably an electroless plating process (when electroless plating forms the anti-diffusion layer 713, the nickel film covers both the surface of the bump 707 and the pad 701), and the chemical process tube Single, and not easy to short circuit, the stability of the formed package of the semiconductor device is good.
  • a wetting layer 715 covering the diffusion prevention layer 713 is formed.
  • the material of the wetting layer 715 includes at least a tin element, a gold element or a silver element, and the thickness of the wetting layer 715 is 0.05 micrometer to 3 micrometers to improve the bonding force with the diffusion preventing layer 713 and the solder ball.
  • the material of the wetting layer 715 is tin and has a thickness of 1 micron.
  • the wetting layer in order to save process steps and prevent short circuits between the bumps 707, the wetting layer
  • the forming process of 715 is the same as the forming process of the diffusion layer 713, and is an electroless plating process.
  • solder ball 711 covering the wetting layer 715 is formed.
  • the solder ball 711 covers the wetting layer 715. Since the wetting layer 715 covers the surface of the bump 707 (top surface and side surface), the solder ball 711 covers the surface of the bump 707 to form a bottom shape. It is a skirt. In the embodiment of the present invention, due to the presence of the wetting layer 715, the formed solder ball 711 more easily covers the surface of the pad 701, and the contact area of the solder ball 711 with the wetting layer 715 and the pad 701 is increased, effectively increasing the solder ball 711 and The bonding force between the wetting layer 715 and the pad 701 improves the strength of the solder ball 711.
  • the fabrication of the semiconductor device of the third embodiment of the present invention is completed.
  • the top and side walls of the bump 707 and the diffusion prevention layer 713 of the pad 701 are formed by a chemical plating process, and the formed semiconductor device is not easily short-circuited, has good stability, and forms a process cartridge.
  • a wetting layer 715 covering the diffusion preventing layer 713 is sequentially formed to cover the solder ball 711 of the wetting layer 715. The diffusion between the tin in the solder ball 711 and the metal atoms in the pad 701 is avoided, further increasing the strength of the solder ball 711.
  • the inventors also provide a package for a semiconductor device.
  • the chip includes: a chip 700 having a pad 701; a passivation layer 703 on a surface of the chip 700, the passivation layer 703 having an opening 705, the opening 705 exposing a portion of the pad 701; a bump 707 on the surface of the pad 701, the size of the bump 707 is smaller than the size of the opening 705; a diffusion prevention layer 713 covering the surface of the bump 707 and covering the surface of the pad 701 at the bottom of the opening 705; A wetting layer 715 of the diffusion preventing layer 713; a solder ball 711 covering the surface of the wetting layer 715.
  • the anti-diffusion layer 713 covers not only the top and sidewalls of the bump 707 but also the surface of the pad 701. Therefore, the anti-diffusion layer 713 can effectively prevent tin atoms and bumps 707 in the solder balls 711.
  • the copper atoms and the metal atoms in the pad 701 are mutually diffused, and the strength of the solder balls 701 is further enhanced.
  • the wetting layer 715 covers the surface of the diffusion preventing layer 713, that is, the wetting layer 715 covers the top and side walls of the bump 707, and the surface of the pad 701, effectively preventing oxidation of the diffusion preventing layer 713, and enhancing the solder ball 711 Strength of.
  • the solder balls 711 cover the surface of the wetting layer 715, i.e., cover the top and side walls of the bumps 707, and the surface of the pads 701.
  • the solder ball 711 is spherical due to the action of gravity and surface tension, and the bottom of the solder ball 711 is skirt-shaped, and the strength thereof is high, and the stability of the package of the corresponding semiconductor device is good.
  • the anti-diffusion layer of the semiconductor device also covers the surface of the pad, effectively preventing tin in the solder ball and metal in the pad The atoms are mutually diffused, the bonding between the solder balls and the pads is good, the strength of the solder balls is large, and the performance of the semiconductor device is stable.
  • the bumps are formed by a plurality of bonding processes, and the bumps formed are a multi-layer stacked structure, and the final formation is ensured.
  • the plurality of bumps have the same height and good coplanarity, and need to be flattened after each bonding process.
  • a method for packaging a semiconductor device includes: Step S801, providing a chip having a pad on a surface thereof, wherein a surface of the chip is formed with a passivation layer.
  • the passivation layer has an opening exposing a portion of the pad surface;
  • Step S802 forming a bump on the surface of the pad in the opening, the size of the bump is smaller than the size of the opening, and the bump is a multi-layer stacked structure;
  • Step S803 forming a diffusion prevention layer covering the surface of the bump and covering the surface of the bottom pad of the opening;
  • Step S804 forming a wetting layer covering the anti-diffusion layer
  • Step S805 forming a solder ball covering the wetting layer.
  • FIG. 18 to FIG. 20 are cross-sectional structural views showing a packaging process of a semiconductor device according to a fourth embodiment of the present invention.
  • a chip 900 having a pad 901 and an integrated circuit on the surface is provided.
  • the 901 is electrically connected to an integrated circuit, and a surface of the chip 900 is formed with a passivation layer 903 having an opening 905 exposing a portion of the pad 901.
  • the chip 900 is used to provide a working platform for a subsequent process; the pad 901 and the integrated circuit are made of aluminum, copper, gold or silver.
  • a bump 907 on the surface of the pad 901 is formed in the opening 905 (shown in FIG. 18), the size of the bump 907 is smaller than the size of the opening 905, and the bump 907 It is a multi-layer stack structure.
  • the bump 907 can be a multi-layer stack structure in addition to a single-layer structure to meet different process and product design requirements, for example, to meet the needs of high-density products, industrial requirements.
  • the bump of the formed semiconductor device has a bump height of 6 ⁇ m, and the sub-bump formed by the one-time wire bonding process has a sub-bump of 3 ⁇ m, requiring a wire bonding process twice.
  • the bump 907 includes a plurality of sub-bumps, for example, 2 to 5.
  • the formation process of the bumps 907 is a deposition process and an etching process or the formation process of the bumps 907 is a wire bonding process.
  • the bump 907 includes a first sub-bump 9071 on the surface of the pad 901, and a second sub-bump 9072 covering the surface of the first sub-burl 9071.
  • the materials of the first sub-bump 9071 and the second sub-blot 9072 are the same, both are copper, and the first sub-bump 9071 and the second sub-bench 9072 are formed in the same process. Wire bonding process. In order to ensure that the finally formed bumps 907 are highly uniform and have good coplanarity, Each of the bumps 907 formed after the wire bonding process is flattened.
  • a process step of flattening is performed after each wire bonding process. That is, after the first sub-bumps 9071 are formed by the wire bonding process, the first sub-bumps 9071 are flattened so that the heights of the first sub-bumps 9071 are uniform; and then the wire bonding process is used after the flattening.
  • the second sub-bumps 9072 are formed on the surface of the first sub-bumps 9071, and the second sub-brexs 9072 are flattened, so that the heights of the finally formed bumps 907 are more uniform and the coplanarity is better. The performance of the subsequently formed semiconductor device is superior.
  • the bump 907 is further annealed to better combine the sub-bumps of the stack, and details are not described herein.
  • the bump includes a plurality of stacked sub-bumps, and the sub-bump at the top includes a sub-bump body and a sub-convex located on the surface of the sub-bump body a dot tail portion (not shown), wherein the sub-bump tail portion is formed after the arcing in the wire bonding process, and the height of the sub-bump tail portion is 0.005 to 1.5 times the height of the sub-bump body, It is beneficial to further increase the contact area between the solder ball and the bottom layer to further enhance the bonding of the solder ball.
  • a diffusion prevention layer 913 covering the surface of the bump 907 and covering the bottom pad 901 of the opening 905 is formed; a wetting layer 915 covering the diffusion prevention layer 913 is formed; and a soldering covering the wetting layer 915 is formed.
  • the material of the diffusion prevention layer 913 is nickel for preventing mutual diffusion of copper atoms in the bumps 907 and tin atoms in the solder balls; the anti-diffusion layer 913 has a thickness of 0.05 ⁇ m to 10 ⁇ m, preferably , which is 0.5 ⁇ m to 5 ⁇ m, and most preferably 1 ⁇ m to 3 ⁇ m; the material of the wetting layer 915 includes at least a tin element, a gold element or a silver element for preventing oxidation of the diffusion prevention layer 913 and improving
  • the adhesion layer 913 and the solder ball have a thickness of 0.05 ⁇ m to 3 ⁇ m; the solder ball 911 is made of tin or tin alloy, and the solder ball 911 is spherical, and The bottom is skirted.
  • the fabrication of the package of the semiconductor device of the fourth embodiment of the present invention is completed. Due to the formation of bumps in a multi-layer stack structure, different process and product design requirements are met. Moreover, when the bumps are formed by the wire bonding process, each time a sub-bump is formed, the flattening is performed once, and the height of the bumps finally formed is uniform, the coplanarity is good, and the performance of the package of the formed semiconductor device is good. Correspondingly, referring to FIG.
  • the inventors further provide a package of a semiconductor device, comprising: a chip 900 having a pad 901 on the surface of the chip; a surface passivation layer 903 having an opening 905 (shown in FIG. 18), the opening 905 exposing a portion of the pad 901; a bump 907 on the surface of the pad 901, the protrusion
  • the size of the point 907 is smaller than the size of the opening 905, and the bump 907 is a multi-layer stack structure; a diffusion prevention layer 913 covering the surface of the bump 907 and covering the surface of the pad 901 at the bottom of the opening 905; A wetting layer 915 of the diffusion prevention layer 913; a solder ball 911 covering the wetting layer 915.
  • the bump 907 includes a plurality of stacked sub-bumps to meet different process and product design requirements.
  • the bump 907 includes: a first sub-bump 9071 located on a surface of the pad 901; and a second sub-blot 9072 covering the first sub-blot 9071.
  • the materials of the first sub-bump 9071 and the second sub-bump 9072 are the same, both of which are copper, to save cost.
  • the first sub-bumps 9071 and the second sub-breasts 9072 may each have the same size or different sizes.
  • the anti-diffusion layer 913 covers the top and sidewalls of the second sub-bump 9072, the sidewalls of the first sub-brex 9071, and the surface of the pad 901.
  • the anti-diffusion layer 913 is made of nickel and has a thickness of 1 £ m to 3 mm.
  • the wetting layer 915 covers the anti-diffusion layer 913, that is, covers the top and side walls of the second sub-bump 9072, the sidewalls of the first sub-brex 9071, and the surface of the pad 901.
  • the material of the wetting layer 915 includes at least a tin element, a gold element or a silver element, and the thickness of the wetting layer 915 is 0.05 mm to 3 m.
  • the solder ball 911 covers the wetting layer 915, that is, the top and side walls of the second sub-bump 9072, the sidewalls of the first sub-bump 9071, and the surface of the pad 901.
  • the shape of the solder ball 911 is spherical due to the influence of gravity, wettability, and surface tension, and the bottom thereof is in the shape of a skirt.
  • the bump may further include a plurality of stacked sub-bumps, and the sub-bump at the top includes a sub-bump body and a sub-surface of the sub-bump body Bump tail.
  • the solder ball has a larger contact area with the bump having the top of the sub-bump at the top, and the formed solder ball has a higher strength.
  • the semiconductor device further includes: the bumps are multi-layer stacked structures to meet different process and product design requirements.
  • the technical solution of the present invention has the following advantages:
  • a solder ball is formed on the bump, and a gap between adjacent solder balls is increased, and a semiconductor device formed later is less likely to be short-circuited, and the device performance is stable; on the other hand, the formed bump is smaller in size than the opening Dimensions, when the solder ball is subsequently formed, the solder ball covers not only the top of the bump but also the sidewall of the bump and the bottom of the opening.
  • the bottom of the solder ball forms a skirt-like structure, which effectively increases the contact area between the solder ball and the bump, thereby increasing the bonding force of the two, increasing the bonding strength of the solder ball, and improving the packaging of the semiconductor device. Piece performance and yield.
  • the method further includes: forming an anti-diffusion layer covering the top of the bump, the sidewall and the bottom of the opening, and a wetting layer covering the anti-diffusion layer.
  • the anti-diffusion layer effectively prevents the formation of a tin-copper interface alloy compound
  • the wetting layer effectively prevents oxidation of the anti-diffusion layer, and improves the bonding strength between the solder ball and the anti-diffusion layer, thereby further improving the semiconductor device.
  • Package performance and yield is forming an anti-diffusion layer covering the top of the bump, the sidewall and the bottom of the opening, and a wetting layer covering the anti-diffusion layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种半导体器件的封装件和封装方法，所述半导体器件的封装方法包括：提供表面具有焊盘的芯片；形成位于所述芯片表面的钝化层和凸点，所述钝化层具有暴露出焊盘的开口，所述凸点位于所述开口内、且其尺寸小于所述开口的尺寸；形成覆盖所述凸点的顶部、侧壁以及开口底部的焊球。形成的半导体器件的封装件不易短路，且焊球与凸点间的结合强度高，半导体器件的性能稳定。

Description

半导体器件的封装件和封装方法
本申请要求 2012年 11月 8日提交中国专利局、申请号为 201210445562.8、 发明名称为"半导体器件的封装件"的中国专利申请的优先权和 2012年 11月 8 日提交中国专利局、 申请号为 201210444454.9、 发明名称为"半导体器件的封 装方法"的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体器件的封装件和封 装方法。
背景技术
封装是指将器件或电路装入保护外壳的工艺过程。封装对于半导体芯片来 说是至关重要的， 因为半导体芯片必须与外界隔离， 以防止空气中的杂质对半 导体芯片的电路腐蚀， 造成电气性能下降。 并且， 封装后的半导体芯片也利于 安装和运送。
现有技术的半导体器件的封装方法， 包括：
请参考图 1 , 提供芯片 100, 所述芯片 100表面形成有集成电路和电连接 集成电路的焊盘 101;
请参考图 2, 形成位于所述芯片 100表面的钝化层 103, 所述钝化层 103 具有暴露出焊盘 101的开口 105;
请参考图 3,通过所述开口 105(图 2所示）在焊盘 101表面形成焊球 107。 然而，现有技术形成的半导体器件的封装件的性能不稳定， 容易出现短路 现象。
更多关于半导体器件的封装方法请参考公开号为 "CN101154640A"的中国 专利。
发明内容
本发明解决的问题是提供一种半导体器件的封装件，形成的半导体器件的 封装件性能稳定， 不易短路。
为解决上述问题， 本发明提供了一种半导体器件的封装方法， 包括： 提供 表面具有焊盘的芯片； 形成位于所述芯片表面的钝化层和凸点， 所述钝化层具 有暴露出部分焊盘的开口， 所述凸点位于所述开口内、且其尺寸小于所述开口 的尺寸； 形成覆盖所述凸点表面、 且覆盖开口底部焊盘表面的焊球。 可选的， 还包括： 在形成焊球前， 形成覆盖所述凸点表面的防扩散层。 可选的， 所述防扩散层还覆盖开口底部的焊盘。
可选的， 还包括： 形成覆盖所述防扩散层的浸润层。
可选的， 所述浸润层的形成工艺为化学镀工艺， 所述浸润层的材料中至少 包括锡元素、 金元素或银元素。
可选的， 所述凸点的形成工艺为引线键合工艺。
可选的， 形成的凸点包括多个堆叠的子凸点，且每进行一次引线键合工艺 后， 对形成的多个子凸点进行压平。
可选的， 形成的凸点包括多个堆叠的子凸点，位于顶部的子凸点包括子凸 点本体和位于所述子凸点本体表面的子凸点尾部。
可选的， 所述凸点的材料为铜、 金、 银、 铜合金、 金合金或银合金， 所述 焊球的材料为锡或锡合金。
为解决上述问题，本发明还提供一种采用上述方法形成的半导体器件的封 装件， 包括： 芯片， 所述芯片表面具有焊盘； 位于所述芯片表面的钝化层， 所 述钝化层具有开口， 所述开口暴露出部分焊盘； 位于所述焊盘表面的凸点， 所 述凸点的尺寸小于所述开口的尺寸； 覆盖所述凸点表面、且覆盖开口底部焊盘 表面的焊球。
可选的， 还包括： 覆盖所述凸点的顶部和侧壁的防扩散层， 所述焊球位于 防扩散层表面。
可选的， 所述防扩散层还覆盖开口底部的焊盘。
可选的， 所述防扩散层的材料为镍。
可选的，还包括：覆盖所述防扩散层的浸润层，所述焊球位于浸润层表面。 可选的， 所述浸润层的材料中至少包括锡元素、 金元素或银元素。
可选的， 所述凸点包括单个或多个堆叠的子凸点。
可选的， 所述凸点包括多个堆叠的子凸点，位于顶部的子凸点包括子凸点 本体和位于所述子凸点本体表面的子凸点尾部。
可选的， 所述凸点的材料为铜、 金、 银、 铜合金、 金合金或银合金， 所述 焊球的材料为锡或锡合金。 与现有技术相比， 本发明的技术方案具有以下优点：
一方面， 在所述凸点上形成焊球， 受到重力、 浸润力与表面张力的影响， 相邻焊球间的间隙增大， 后续形成的半导体器件的封装件不易出现短路现象， 器件性能稳定； 另一方面， 形成的凸点的尺寸小于开口的尺寸， 后续形成焊球 时， 所述焊球不仅覆盖凸点的顶部， 还覆盖凸点的侧壁， 以及开口底部。 所述 焊球的底部形成裙摆状的结构，有效增大了焊球与凸点间的接触面积，从而增 加了两者的结合力，使得焊球的结合强度增加，提高了半导体器件的封装件性 能和良率。
进一步的， 还包括： 形成覆盖所述凸点的顶部、 侧壁以及开口底部的防扩 散层， 以及覆盖所述防扩散层的浸润层。所述防扩散层有效阻止了界面合金共 化物的产生， 所述浸润层有效阻止了防扩散层的氧化， 并提高了焊球与防扩散 层间的结合强度， 进一步提高了半导体器件的封装件的性能和良率。
附图说明
图 1至图 3是现有技术的半导体器件的封装过程的剖面结构示意图； 图 4是本发明第一实施例的半导体器件的封装方法的流程示意图； 图 5至图 7是本发明第一实施例的半导体器件的封装过程的剖面结构示意 图；
图 8是本发明第二实施例的半导体器件的封装方法的流程示意图； 图 9至图 12是本发明第二实施例的半导体器件的封装过程的剖面结构示 意图；
图 13是本发明第三实施例的半导体器件的封装方法的流程示意图； 图 14至图 16是本发明第三实施例的半导体器件的封装过程的剖面结构示 意图；
图 17是本发明第四实施例的半导体器件的封装方法的流程示意图； 图 18至图 20是本发明第四实施例的半导体器件的封装过程的剖面结构示 意图。
具体实施方式
正如背景技术所述， 现有技术形成的半导体器件的封装件的性能不稳定， 容易出现短路的现象。 经过研究发现，现有技术直接在焊盘表面形成焊球，通常形成的焊球为半 球形， 所述焊球的直径较大， 导致相邻焊球之间的间隙较小， 所述间隙较小的 焊球之间极易出现短路， 影响半导体器件的封装件的稳定性。
经过进一步研究发现， 首先在所述焊盘表面形成凸点， 然后在所述凸点表 面形成焊球时， 受到重力、 浸润力与表面张力的影响， 形成焊球的锡沿凸点侧 壁向下流动， 所述焊球由半球形向球形过渡，相同质量的焊锡形成的焊球的直 径较现有技术的小， 有助于增大相邻焊球之间的间隙。 然而， 如果所述焊球仅 覆盖所述凸点的顶部， 两者的结合力可能不够， 焊球极易在后续进行踢球实验 时被踢掉， 影响半导体器件的封装件的良率。
更进一步的， 当所述焊球覆盖凸点的顶部和侧壁， 并覆盖部分焊盘时， 焊 球与凸点间的接触面积增大，两者的结合力增大；并且还有焊球覆盖部分焊盘， 进一步增大了焊球与凸点、焊盘间的结合力， 可以有效提高半导体器件的封装 件的良率。
为使本发明的上述目的、特征和优点能够更加明显易懂， 下面结合附图对 本发明的各具体实施方式做详细的说明。
第一实施例
请参考图 4, 本发明第一实施例的半导体器件的封装方法， 包括： 步骤 S201 , 提供表面具有焊盘的芯片， 所述芯片表面形成有钝化层， 所 述钝化层具有暴露出部分焊盘表面的开口；
步骤 S202, 在所述开口内形成位于焊盘表面的凸点， 所述凸点的尺寸小 于所述开口的尺寸；
步骤 S203 , 形成覆盖所述凸点表面、 且覆盖开口底部焊盘表面的焊球。 具体的， 请参考图 5至图 8, 图 5至图 8示出了本发明第一实施例的半导 体器件的封装过程的剖面结构示意图。
请参考图 5 , 提供表面具有焊盘 301的芯片 300, 所述芯片 300表面形成 有钝化层 303 , 所述钝化层 303具有暴露出部分焊盘 301的开口 305。
所述芯片 300用于为后续封装工艺提供工作平台。所述芯片 300表面还具 有与焊盘 301 电连接的集成电路， 所述集成电路为满足不同的功能需求而设 计， 所述集成电路通过与其电连接的焊盘 301将电信号传输至外界。所述集成 电路与焊盘 301由沉积于芯片 300表面的布线金属层刻蚀后形成。在本发明的 实施例中， 所述集成电路与焊盘 301在同一工艺步骤中形成， 所述集成电路和 焊盘 301的材料为金、 银、铜等金属材质。 由于形成集成电路和焊盘 301的工 艺已为本领域技术人员所熟知， 在此不再赘述。
需要说明的是， 在本发明的实施例中， 金、 银和铜这三种材质与锡或锡合 金件的浸润性更好， 当所述焊盘 301的材料为金、 银或铜时， 后续工艺中焊球 更易覆盖焊盘 301表面， 焊球的浸润结合性能更好。
所述钝化层 303的材料为氧化硅、 氮化硅等， 用于隔离集成电路， 并保护 焊盘 301在后续工艺中受损或被氧化。所述钝化层 303的形成工艺为沉积工艺， 例如化学气相沉积工艺。由于形成钝化层 303的工艺已为本领域技术人员所熟 知， 在此不再赘述。
所述钝化层 303内具有开口 305 , 所述开口 305暴露出焊盘 301表面， 用 于为后续在焊盘 301表面形成凸点提供工艺窗口。所述开口 305的形成工艺为 刻蚀工艺， 例如各向异性的干法刻蚀工艺。 在本发明的实施例中， 所述焊盘 301的尺寸大于所述开口 305的尺寸。
请参考图 6, 通过所述开口 305形成位于所述焊盘 301表面的凸点 307, 所述凸点 307的尺寸小于所述开口 305的尺寸。
发明人发现，现有技术直接在焊盘 101 (图 3所示）表面形成焊球 107 (图 3所示）， 通常形成的焊球 107的直径较大， 导致相邻焊球 107之间的间隙较 小， 所述间隙较小的焊球 107之间极易出现短路， 影响半导体器件的稳定性。
经过进一步研究， 发明人发现， 首先在所述焊盘 301表面形成凸点 307 , 然后在所述凸点 307表面形成焊球时，位于所述凸点 307表面的焊球的体积较 小， 有助于增大相邻焊球之间的间隙。
所述凸点 307的材料为导热性能好的铜、 金、 银、 铜合金、 银合金或金合 金等，后续所述凸点 307表面用于形成直径较小的焊球。在本发明的实施例中， 所述凸点 307的材料为铜， 成本更低， 且导电性更佳， 形成的凸点 307的质量 更好。
所述凸点 307的形成工艺为引线键合工艺， 例如热压键合、超声波键合或 热超声键合。由于引线键合工艺形成的凸点 307与焊盘 301间的原始交界面处 几乎接近原子力的范围， 两种金属原子发生扩散， 两者结合的更加牢固。 本发 明的实施例中， 采用热超声键合的工艺形成凸点 307, 增强了金属间原始交界 面的相互扩散和分子（原子）间作用力， 金属的扩散在整个界面上进行， 实现 凸点 307的高质量焊接， 形成的凸点 307与焊盘 301结合的更牢固，且形成工 艺筒单。 并且， 为防止用作形成凸点 307的铜丝在引线键合工艺中被氧化， 所 述引线键合工艺时， 还包括： 通入体积分数为 95%的氮气和体积分数为 5%的 氢气。
所述引线键合工艺中采用的劈刀为楔形或球形。 考虑到形成的凸点 307 为柱状，在本发明的实施例中，所述劈刀为球形， 更利于形成柱状的凸点 307。
需要说明的是，在本发明的而其他实例中， 所述凸点 307还可以采用电镀 工艺， 或者采用沉积工艺和刻蚀工艺形成， 以形成尺寸精确的凸点 307 , 在此 不再赘述。
所述凸点 307的尺寸 W1小于所述开口 305的尺寸 W2, 用于后续形成覆 盖所述凸点 307的顶部和侧壁， 以及开口 305底部焊盘 301的焊球， 以增加焊 球与凸点 307、 焊盘 301的结合力， 提高焊球的强度。
需要说明的是， 所述凸点 307的沿芯片表面方向的截面形状为圆形、椭圆 形、 方形或三角形， 本实施例中所说的凸点 307的尺寸 W1以及开口 305的尺 寸 W2指的是图 7中示出的平行于芯片 300表面方向的长度。
请参考图 7, 形成覆盖所述凸点 307表面、 且覆盖开口 305底部焊盘 301 表面的焊球 311。
所述焊球 311的材料为锡或锡合金。所述焊球 311的形成工艺为植球工艺 和回流焊接工艺， 或者为印刷工艺和回流焊接工艺。 由于凸点 307的尺寸 W1 小于开口 305的尺寸 W2, 回流工艺时， 熔融的锡受表面张力的作用， 收缩成 球状结构， 并且分布于金属材料表面， 即覆盖开口 305底部的焊盘 301 , 在所 述开口 305底部形成裙摆结构 （ ankor状）。
本发明的实施例中， 所述焊球 311覆盖凸点 307表面（包括顶部表面和侧 表面）、 且覆盖开口 305底部的焊盘 301表面， 焊球 311与凸点 307、 开口 305 底部焊盘 301的接触面增大， 其横向和纵向抗拉力更大， 增加了焊球 311的结 合强度。形成的焊球 311的直径进一步减小，增大了相邻焊球 311之间的间隙， 进一步提高了半导体器件的封装件的稳定性。
本发明的第一实施例中，采用引线键合工艺形成凸点 307 ,形成工艺筒单， 且凸点 307与焊盘 301之间结合的更牢固。 并且， 由于凸点 307的尺寸 W1小 于开口 305的尺寸 W2, 后续形成焊球 311时， 受重力和表面张力的作用， 所 述焊球 311覆盖凸点 307的顶部、侧壁以及开口 305底部的焊盘 301 ,焊球 311 与凸点 307、 焊盘 301的接触面增大， 增加了焊球 311的结合强度， 并且， 形 成的焊球 311的直径小， 增大了相邻焊球 311间的间隙， 更进一步提高了半导 体器件的封装件的稳定性。
相应的， 请继续参考图 7, 本发明第一实施例中形成的半导体器件的封装 件， 包括： 芯片 300, 所述芯片表面具有焊盘 301 ; 位于所述芯片表面的钝化 层 303 , 所述钝化层 303具有开口 305 , 所述开口 305暴露出部分焊盘 301 ; 位于所述焊盘 301表面的凸点 307 , 所述凸点 307的尺寸小于所述开口 305的 尺寸； 覆盖所述凸点 307表面、 且覆盖开口 305底部的焊球 311表面。
其中， 所述焊盘 301 的尺寸与所述开口 305 的尺寸相同， 所述焊盘 301 的材料为金、 银或铜等； 所述凸点 307的材料为导热性能好的铜、 金、 银、 铜 合金、 金合金或银合金等， 本发明的实施例中， 所述凸点 307的材料为铜， 成 本低， 且质量好； 所述焊球 311的材料为锡或锡合金， 相邻焊球 311间的间隙 小。
本发明第一实施例中， 所述凸点 307的材料为铜， 成本低， 且铜的导电性 更佳， 凸点 307层的质量好。 焊球 311不仅覆盖凸点 307的顶部的表面， 还覆 盖凸点 307的侧表面、 以及开口 305底部焊盘 301表面， 焊球 311的直径小， 增大了相邻焊球 311间的间隙。 并且， 焊球 311的接触面积更大， 其横向和纵 向抗拉力更大， 提高了焊球 311的结合强度， 焊球 311不易剥落， 更进一步增 加了半导体器件的封装件的稳定性。
第二实施例
与本发明的第一实施例不同，在本发明的第二实施例中， 所述凸点的顶部 表面和侧表面还形成有防扩散层，以防止凸点中的铜原子和焊球中的锡原子发 生相互扩散，影响焊球的结合强度。并且，所述防扩散层表面还覆盖有浸润层， 以提高防扩散层与焊球间的结合力。 请参考图 8, 本发明第二实施例中， 所述半导体器件的封装方法， 包括： 步骤 S401 , 提供表面具有焊盘芯片， 所述芯片表面形成有钝化层， 所述 钝化层具有暴露出部分焊盘表面的开口；
步骤 S402, 在所述开口内形成位于焊盘表面的凸点， 所述凸点的尺寸小 于所述开口的尺寸；
步骤 S403 , 形成覆盖所述凸点表面的防扩散层；
步骤 S404, 形成覆盖所述防扩散层的浸润层；
步骤 S405 , 形成覆盖所述浸润层、 且覆盖所述开口底部焊盘表面的焊球。 具体的， 请参考图 9至图 12, 图 9至图 12示出了本发明第二实施例的半 导体器件的封装过程的剖面结构示意图。
请参考图 9, 提供表面具有焊盘 501的芯片 500, 所述芯片 500表面形成 有钝化层 503 , 所述钝化层 503具有暴露出部分焊盘 501表面的开口 505; 在 所述开口 505内形成位于焊盘 501表面的凸点 507, 所述凸点 507的尺寸小于 所述开口 505的尺寸。
其中， 所述凸点 507的材料为铜， 以降低成本， 提高凸点 507的质量。 请参考图 10, 形成覆盖所述凸点 507的顶部、 侧壁的防扩散层 513。
发明人发现， 当所述凸点 507的材料为铜， 所述焊球的材料为锡或锡合金 时，如果直接在凸点 507表面形成焊球， 凸点 507中的铜原子和焊球中的锡原 子之间容易发生扩散， 形成锡铜界面合金共化物和空洞， 所述锡铜界面合金共 化物具有脆性， 降低了焊球与凸点 507之间的结合强度。 因此， 本发明的实施 例中， 还包括： 形成覆盖所述凸点 507的顶部和侧壁的防扩散层 513 , 用于阻 止铜原子和锡原子的相互扩散。
所述防扩散层 513的材料为镍，用于防止凸点 507中的铜原子和焊球中的 锡原子发生相互扩散。 并且， 为有效阻止凸点 507中的铜原子和焊球中的锡原 子发生相互扩散， 所述防扩散层 513的厚度为 0.05微米 ~10微米， 较好的， 为 0.5微米 ~5微米。 在本发明的实施例中， 所述防扩散层 513的材料为镍锡， 所 述防扩散层 513的厚度为 1微米 ~3微米， 例如 3微米， 既较好的防止了铜原 子和锡原子的相互扩散， 又满足高度集成化的要求。
本发明的实施例中， 所述防扩散层 513的形成步骤包括： 形成覆盖所述钝 化层 503、 焊盘 501、 以及凸点 507的顶部和侧壁的防扩散薄膜（未图示）； 形 成第一掩膜层（未图示）， 所述第一掩膜层仅覆盖凸点 507的顶部和侧壁的防 扩散薄膜； 以所述第一掩膜层为掩膜， 刻蚀所述防扩散薄膜， 直至暴露出焊盘 501和钝化层 503; 在刻蚀所述防扩散薄膜后， 去除所述第一掩膜层。
需要说明的是， 在本发明的其他实例中， 还可以采用其他的沉积、 刻蚀工 艺形成防扩散层 513 , 只要能达到防扩散层 513覆盖凸点 407的顶部和侧壁即 可， 在此不再赘述。
请参考图 11 , 形成覆盖所述防扩散层 513的浸润层 515。
发明人发现， 上述防扩散层 513 中的镍极易被氧化， 而且防扩散层 513 与焊球之间的结合力较为有限，后续形成的焊球的强度也较为有限， 不易通过 踢球实验的检测。 因此， 发明人发现， 可以通过在所述防扩散层 513表面覆盖 与防扩散层 513和焊球的结合性均较好的浸润层 515作为过渡，有效增大了焊 球与凸点 507间的结合性能。 并且， 在形成防扩散层 513后， 立即形成所述浸 润层 515 ,形成防扩散层 513后到形成浸润层 515之间的时间间隔小于 3分钟， 还可以更有效防止防扩散层 513的氧化，进一步提高了半导体器件的封装件的 性能。
所述浸润层 515的材料中至少包括锡元素、金元素或银元素， 所述浸润层 515的厚度为 0.05微米 ~3微米， 以提高其与防扩散层 513、 焊球的结合力。 在 本发明的实施例中， 所述浸润层 515的材料为锡， 其厚度为 1微米， 所述浸润 层 515后续与同材质的焊球间可更好的结合浸润。
所述浸润层 515的形成步骤包括：形成覆盖所述防扩散层 513、钝化层 503 和焊盘 501的种子薄膜（未图示）； 形成第二掩膜层（未图示）， 所述第二掩膜 层仅覆盖防扩散层 513表面的种子薄膜； 以所述第二掩膜层为掩膜， 刻蚀所述 种子薄膜， 直至暴露出焊盘 501和钝化层 503; 在刻蚀所述种子薄膜后， 去除 所述第二掩膜层。
在本发明的实施例中， 所述第一掩膜层和第二掩膜为同一掩膜层， 刻蚀所 述防扩散薄膜和种子薄膜在同一工艺步骤中形成， 有效节省了工艺步骤。
需要说明的是， 在本发明的其他实例中， 还可以采用其他的沉积、 刻蚀工 艺形成浸润层 515 , 只要能达到浸润层 515覆盖防扩散层 513即可， 在此不再 赘述。
需要说明的是， 在本发明的其他实施例中， 还可以不形成浸润层 515 , 直 接在防扩散层 513表面和开口 505底部形成焊球， 在此不再赘述。
请参考图 12, 形成覆盖所述浸润层 515、且覆盖所述开口 505底部的焊球 511。
本发明的第二实施例中， 所述焊球 511覆盖凸点 507表面、 且覆盖焊盘 501表面，形成底部为裙摆状的结构。所述焊球 511与焊盘 501接触，焊球 511 与凸点 507、焊盘 501的接触面积增大，焊球 511与焊盘 501间的结合力变强， 有利于提高焊球 511的强度。
所述焊球 511的形成工艺请参考本发明第一实施例的相关描述，在此不再 赘述。
上述步骤完成之后， 本发明第二实施例的半导体器件的制作完成。 除了具 有本发明第一实施例中的优点外， 由于在形成焊球 511前， 在所述凸点 507表 面形成防扩散层 513和浸润层 515 , 有效防止了焊球 511中的锡和凸点 507中 的铜相互扩散， 提高了焊球 511的强度， 形成的半导体器件的封装件的稳定性 进一步得到提高。
相应的， 请继续参考图 12, 发明人还提供了一种半导体器件的封装件， 包括： 芯片 500, 所述芯片表面具有焊盘 501 ; 位于所述芯片 500表面的钝化 层 503 , 所述钝化层 503具有开口 505 , 所述开口 505暴露出部分焊盘 501 ; 位于所述焊盘 501表面的凸点 507 , 所述凸点 507的尺寸小于所述开口 505的 尺寸； 覆盖所述凸点 507表面的防扩散层 513; 覆盖所述防扩散层 513的浸润 层 515; 覆盖所述浸润层 515和开口 505底部的焊球 511。
其中， 所述防扩散层 513的材料为镍， 用于防止凸点 507中的铜原子和焊 球中的锡原子发生相互扩散； 所述防扩散层 513的厚度为 0.05微米 ~10微米， 较佳的， 为 0.5微米 ~5微米。 本发明第二实施例中， 所述防扩散层 513的材料 为镍， 其厚度为 1微米 ~3微米。
所述浸润层 515的材料中至少包括锡元素、金元素或银元素， 用于防止防 扩散层 513的氧化，并提高其与防扩散层 513、焊球的结合力。所述浸润层 515 的厚度为 0.05微米 ~3微米。 本发明的第二实施例中， 所述浸润层 515的材料 为锡， 所述浸润层 515的厚度为 1微米。
更多关于本发明第二实施例中半导体器件的封装件的相关描述，请参考本 发明第一实施例和第二实施例中方法部分的描述， 在此不再赘述。
第三实施例
与本发明的第二实施例略有不同， 防扩散层不仅覆盖凸点的表面，还覆盖 开口内的焊盘表面， 形成裙摆结构， 以使得形成焊球时焊球更易覆盖到焊盘表 面， 进一步提高焊球的强度。
请参考图 13 , 本发明第三实施例的半导体器件的封装方法， 包括： 步骤 S601 , 提供表面具有焊盘的芯片， 所述芯片表面形成有钝化层， 所 述钝化层具有暴露出部分焊盘表面的开口；
步骤 S602, 在所述开口内形成位于焊盘表面的凸点， 所述凸点的尺寸小 于所述开口的尺寸；
步骤 S603 , 形成覆盖所述凸点表面、 且覆盖开口底部焊盘表面的防扩散 层；
步骤 S604, 形成覆盖所述防扩散层的浸润层；
步骤 S605 , 形成覆盖所述浸润层的焊球。
具体的， 请参考图 14至图 16, 图 14至图 16示出了本发明第三实施例的 半导体器件的封装过程的剖面结构示意图。
请参考图 14,提供表面具有焊盘 701的芯片 700, 所述芯片 700表面形成 有钝化层 703 , 所述钝化层 703具有暴露出部分焊盘 701表面的开口 705; 在 所述开口 705内形成位于所述焊盘 701表面的凸点 707 , 所述凸点 707的尺寸 小于所述开口 705的尺寸。
所述焊盘 701的材料为铝、 金、 银或铜， 这几种金属与镍之间的浸润结合 性好，后续形成镍合金的防扩散层 713时， 所述防扩散层 713更易覆盖整个焊 盘 701表面。
请继续参考图 14, 形成覆盖所述凸点 707表面、 且覆盖开口 705底部焊 盘 701表面的防扩散层 713。
发明人发现， 后续焊球中的锡与焊盘 701间的金属原子也存在扩散现象。 因此， 与第二实施例不同， 所述防扩散层 713除了覆盖凸点 707的顶部和侧壁 夕卜， 还覆盖焊盘 701表面， 以防止焊球中的锡与焊盘 701中的金属原子扩散， 形成界面合金共化物。 进一步提高了焊球的强度。
所述防扩散层 713的材料为镍， 其形成工艺较佳的为化学镀工艺（化学镀 形成防扩散层 713时， 镍薄膜既覆盖凸点 707表面， 又覆盖焊盘 701 ), 化学 工艺筒单， 且不易短路， 形成的半导体器件的封装件的稳定性好。
请参考图 15, 形成覆盖所述防扩散层 713的浸润层 715。
所述浸润层 715的材料中至少包括锡元素、金元素或银元素， 所述浸润层 715的厚度为 0.05微米 ~3微米， 以提高其与防扩散层 713、 焊球的结合力。 在 本发明的实施例中， 所述浸润层 715的材料为锡， 其厚度为 1微米。
同样地， 为节省工艺步骤， 并防止各凸点 707 间发生短路， 所述浸润层
715的形成工艺与所述扩散层 713的形成工艺相同， 为化学镀工艺。
需要说明的是， 在本发明的其他实施例中， 在形成浸润层 715前， 还可以 在所述防扩散层 713表面形成其他功能层， 在此不再赘述。
请参考图 16, 形成覆盖所述浸润层 715的焊球 711。
所述焊球 711覆盖所述浸润层 715, 由于所述浸润层 715覆盖凸点 707表 面 （顶部表面和侧表面）， 因此， 所述焊球 711覆盖所述凸点 707的表面， 形 成底部形状为裙摆状。 本发明的实施例中， 由于浸润层 715的存在， 形成的焊 球 711更易覆盖焊盘 701表面， 焊球 711与浸润层 715、 焊盘 701的接触面积 增大， 有效增加了焊球 711与浸润层 715、 焊盘 701间的结合力， 提高了焊球 711的强度。
更多所述焊球 711的封装方法和步骤，请参考本发明第二实施例中的相关 描述， 在此不再赘述。
上述步骤完成后， 本发明第三实施例的半导体器件的制作完成。采用化学 镀的工艺形成覆盖凸点 707的顶部和侧壁、 以及焊盘 701的防扩散层 713, , 形成的半导体器件不易短路， 稳定性好， 且形成工艺筒单。 在形成防扩散层 713后， 依次形成覆盖防扩散层 713的浸润层 715, 覆盖所述浸润层 715的焊 球 711。 避免了焊球 711中的锡与焊盘 701中金属原子间的扩散， 进一步提高 了焊球 711的强度。
相应的， 请继续参考图 16, 发明人还提供了一种半导体器件的封装件， 包括： 芯片 700, 所述芯片表面具有焊盘 701 ; 位于所述芯片 700表面的钝化 层 703 , 所述钝化层 703具有开口 705 , 所述开口 705暴露出部分焊盘 701 ; 位于所述焊盘 701表面的凸点 707, 所述凸点 707的尺寸小于所述开口 705的 尺寸； 覆盖所述凸点 707表面、且覆盖开口 705底部的焊盘 701表面的防扩散 层 713; 覆盖所述防扩散层 713的浸润层 715; 覆盖所述浸润层 715表面的焊 球 711。
其中， 所述防扩散层 713不仅覆盖凸点 707的顶部和侧壁， 还覆盖焊盘 701表面， 因此， 所述防扩散层 713可以有效防止焊球 711中的锡原子与凸点 707中的铜原子、 以及焊盘 701中的金属原子相互扩散， 焊球 701的强度进一 步增强。
所述浸润层 715覆盖所述防扩散层 713表面，即所述浸润层 715覆盖凸点 707的顶部和侧壁、 以及焊盘 701表面， 有效阻止防扩散层 713的氧化， 并增 强焊球 711的强度。
所述焊球 711覆盖浸润层 715表面， 即覆盖所述凸点 707的顶部和侧壁、 以及焊盘 701表面。 受重力和表面张力的作用， 所述焊球 711为球状， 且所述 焊球 711底部为裙摆状， 其强度高， 对应的半导体器件的封装件的稳定性好。
更多关于本发明第三实施例中的相关描述，请参考本发明第一或第二实施 例， 在此不再赘述。
与第二实施例的半导体器件不同， 除了具有本发明第一、第二实施例的优 点外， 半导体器件的防扩散层还覆盖焊盘表面，有效阻止焊球中的锡与焊盘中 的金属原子相互扩散， 焊球与焊盘的结合度好， 焊球的强度大， 半导体器件的 性能稳定。
第四实施例
与前述实施例不同， 出于高密度产品的需求考虑，在本发明的第四实施例 中， 凸点通过多次键合工艺形成， 形成的凸点为多层堆叠结构， 且为保证最终 形成的多个凸点高度一致， 具有较好的共面性，每次键合工艺后需要进行压平 处理。
请参考图 17, 本发明第四实施例中， 半导体器件的封装方法， 包括： 步骤 S801 , 提供表面具有焊盘的芯片， 所述芯片表面形成有钝化层， 所 述钝化层具有暴露出部分焊盘表面的开口；
步骤 S802, 在所述开口内形成位于焊盘表面的凸点， 所述凸点的尺寸小 于所述开口的尺寸， 且所述凸点为多层堆叠结构；
步骤 S803 , 形成覆盖所述凸点表面、 且覆盖开口底部焊盘表面的防扩散 层；
步骤 S804, 形成覆盖所述防扩散层的浸润层；
步骤 S805 , 形成覆盖所述浸润层的焊球。
具体的， 请参考图 18至图 20, 图 18至图 20示出了本发明第四实施例的 半导体器件的封装过程的剖面结构示意图。
请参考图 18, 提供表面具有焊盘 901和集成电路的芯片 900, 所述焊盘
901与集成电路电连接，所述芯片 900表面形成有钝化层 903 ,所述钝化层 903 具有暴露出部分焊盘 901的开口 905。
所述芯片 900用于为后续工艺提供工作平台；所述焊盘 901和集成电路的 材料为铝、 铜、 金或银。
请参考图 19, 在所述开口 905 (如图 18所示） 内形成位于焊盘 901表面 的凸点 907, 所述凸点 907的尺寸小于所述开口 905的尺寸， 且所述凸点 907 为多层堆叠结构。
经过研究， 发明人发现， 所述凸点 907除了可以为单层结构外， 还可以为 多层堆叠结构， 以满足不同的工艺和产品设计需求， 例如， 为满足高密度产品 的需求， 工业要求形成的半导体器件的封装件的凸点高 6微米， 而一次引线键 合工艺形成的子凸点为 3微米， 则需要 2次引线键合工艺。
所述凸点 907包括多个子凸点，例如 2~5个。所述凸点 907的形成工艺为 沉积工艺和刻蚀工艺或者所述凸点 907的形成工艺为引线键合工艺。
在本发明的实施例中，所述凸点 907包括位于所述焊盘 901表面的第一子 凸点 9071 , 以及覆盖所述第一子凸点 9071表面的第二子凸点 9072, 以满足不 同的工艺和产品设计需求。
为节省工艺步骤， 所述第一子凸点 9071、 第二子凸点 9072的材料相同， 均为铜， 且所述第一子凸点 9071、 第二子凸点 9072形成工艺相同， 均为引线 键合工艺。 为保证最终形成的凸点 907高度一致， 具有较好的共面性， 还包括 对引线键合工艺后形成的各个凸点 907进行压平。
在本发明的实施例中，在每次引线键合工艺后， 均进行一次压平的工艺步 骤。 即采用引线键合工艺形成第一子凸点 9071 后， 对各个第一子凸点 9071 进行压平， 使各第一子凸点 9071的高度一致； 然后采用引线键合工艺在压平 后的第一子凸点 9071表面形成第二子凸点 9072,再对形成的第二子凸点 9072 进行压平， 使最终形成的各凸点 907的高度更趋于一致， 共面性更好， 后续形 成的半导体器件的性能优越。
需要说明的是，在本发明的第四实施例中，还包括对形成的凸点 907进行 退火， 使堆叠的子凸点间结合的更好， 在此不再赘述。 需要说明的是， 在本发 明的其他实施例中， 所述凸点包括多层堆叠的子凸点，位于顶部的子凸点包括 子凸点本体和位于所述子凸点本体表面的子凸点尾部 （未图示）， 其中， 所述 子凸点尾部为弓 )线键合工艺中起弧后形成，所述子凸点尾部的高度为子凸点本 体高度的 0.005~1.5倍， 以利于后续进一步增大焊球与底部各层的接触面积， 进一步增强焊球的结合性。
请参考图 20, 形成覆盖所述凸点 907表面、且覆盖开口 905底部焊盘 901 的防扩散层 913; 形成覆盖所述防扩散层 913的浸润层 915; 形成覆盖所述浸 润层 915的焊球 911。
所述防扩散层 913的材料为镍，用于防止凸点 907中的铜原子和焊球中的 锡原子发生相互扩散；所述防扩散层 913的厚度为 0.05微米 ~10微米，较佳的， 为 0.5微米 ~5微米， 最佳的， 为 1微米 ~3微米； 所述浸润层 915的材料中至 少包括锡元素、 金元素或银元素， 用于防止防扩散层 913的氧化， 并提高其与 防扩散层 913、 焊球的结合力， 所述浸润层 915的厚度为 0.05微米 ~3微米； 所述焊球 911的材料为锡或锡合金，所述焊球 911为球状，且其底部为裙摆状。
更多关于本发明第四实施例的相关描述， 请结合参考本发明第一、 二、 三 实施例， 在此不再赞述。
上述步骤完成后 , 本发明第四实施例的半导体器件的封装件的制作完成。 由于形成了多层堆叠结构的凸点， 满足不同的工艺和产品设计需求。 并且， 采 用引线键合工艺形成凸点时， 每形成一子凸点， 即进行一次压平， 最终形成的 凸点的高度一致， 共面性好， 形成的半导体器件的封装件的性能好。 相应的， 请参考图 20, 在本发明的第四实施例中， 发明人还提供了一种 半导体器件的封装件， 包括： 芯片 900, 所述芯片表面具有焊盘 901 ; 位于所 述芯片 900表面的钝化层 903 ,所述钝化层 903具有开口 905 (如图 18所示）， 所述开口 905暴露出部分焊盘 901 ; 位于所述焊盘 901表面的凸点 907, 所述 凸点 907的尺寸小于所述开口 905的尺寸、 且所述凸点 907为多层堆叠结构； 覆盖所述凸点 907表面、且覆盖开口 905底部的焊盘 901表面的防扩散层 913; 覆盖所述防扩散层 913的浸润层 915; 覆盖所述浸润层 915的焊球 911。
其中， 所述凸点 907包括多个堆叠的子凸点， 以满足不同的工艺和产品设 计需求。 在本发明的第四实施例中， 所述凸点 907 包括： 位于所述焊盘 901 表面的第一子凸点 9071 ; 以及覆盖所述第一子凸点 9071的第二子凸点 9072。 在本发明的实施例中， 所述第一子凸点 9071和第二子凸点 9072的材料相同， 均为铜，以节省成本。需要说明的是，所述第一子凸点 9071和第二子凸点 9072 各自的尺寸也可以相同或不同。
所述防扩散层 913覆盖所述第二子凸点 9072的顶部和侧壁、 第一子凸点 9071的侧壁、 以及焊盘 901表面。 所述防扩散层 913的材料为镍， 厚度为 1 £米~3 鼓米。
所述浸润层 915覆盖所述防扩散层 913 , 即覆盖所述第二子凸点 9072的 顶部和侧壁、 第一子凸点 9071的侧壁、 以及焊盘 901表面。 所述浸润层 915 的材料中至少包括锡元素、 金元素或银元素， 所述浸润层 915 的厚度为 0.05 鼓米 ~3 敖米。
所述焊球 911覆盖所述浸润层 915 , 即覆盖所述第二子凸点 9072的顶部 和侧壁、 第一子凸点 9071的侧壁、 以及焊盘 901表面。 受重力、 浸润力和表 面张力的影响， 所述焊球 911的形状为球状， 且其底部为裙摆状。
需要说明的是，在本发明的其他实例中， 所述凸点还可以包括多个堆叠的 子凸点，位于顶部的子凸点包括子凸点本体和位于所述子凸点本体表面的子凸 点尾部。焊球与此种顶部具有子凸点尾部的凸点间接触面积更大， 形成的焊球 的强度更高。
本发明的第四实施例中， 半导体器件除了具有前述实施例的优点外，还包 括： 凸点为多层堆叠结构， 满足不同的工艺和产品设计需求。 综合上述实施例， 本发明的技术方案具有以下优点：
一方面， 在所述凸点上形成焊球， 相邻焊球间的间隙增大， 后续形成的半 导体器件不易出现短路现象， 器件性能稳定； 另一方面， 形成的凸点的尺寸小 于开口的尺寸， 后续形成焊球时， 所述焊球不仅覆盖凸点的顶部， 还覆盖凸点 的侧壁， 以及开口底部。 所述焊球的底部形成裙摆状的结构， 有效增大了焊球 与凸点间的接触面积， 从而增加了两者的结合力， 使得焊球的结合强度增加， 提高了半导体器件的封装件的性能和良率。
进一步的， 还包括： 形成覆盖所述凸点的顶部、 侧壁以及开口底部的防扩 散层， 以及覆盖所述防扩散层的浸润层。所述防扩散层有效阻止了锡铜界面合 金共化物的产生，所述浸润层有效阻止了防扩散层的氧化， 并提高了焊球与防 扩散层间的结合强度， 进一步提高了半导体器件的封装件的性能和良率。
本发明虽然以较佳实施例公开如上，但其并不是用来限定权利要求，任何 本领域技术人员在不脱离本发明的精神和范围内，都可以做出可能的变动和修 改， 因此本发明的保护范围应当以本发明权利要求所界定的范围为准。

Claims

权 利 要 求
1. 一种半导体器件的封装方法， 其特征在于， 包括：
提供表面具有焊盘的芯片；
形成位于所述芯片表面的钝化层和凸点，所述钝化层具有暴露出部分焊盘 的开口， 所述凸点位于所述开口内、 且其尺寸小于所述开口的尺寸；
形成覆盖所述凸点表面、 且覆盖开口底部焊盘表面的焊球。
2. 如权利要求 1所述的半导体器件的封装方法， 其特征在于， 还包括： 在形 成焊球前， 形成覆盖所述凸点表面的防扩散层。
3. 如权利要求 2所述的半导体器件的封装方法， 其特征在于， 所述防扩散层 还覆盖开口底部的焊盘。
4. 如权利要求 2或 3所述的半导体器件的封装方法， 其特征在于， 还包括： 形成覆盖所述防扩散层的浸润层。
5. 如权利要求 4所述的半导体器件的封装方法， 其特征在于， 所述浸润层的 形成工艺为化学镀工艺， 所述浸润层的材料中至少包括锡元素、 金元素或 银元素。
6. 如权利要求 1所述的半导体器件的封装方法， 其特征在于， 所述凸点的形 成工艺为引线键合工艺。
7. 如权利要求 6所述的半导体器件的封装方法， 其特征在于， 形成的凸点包 括多个堆叠的子凸点， 且每进行一次引线键合工艺后， 对形成的多个子凸 点进行压平。
8. 如权利要求 7所述的半导体器件的封装方法， 其特征在于， 形成的凸点包 括多个堆叠的子凸点， 位于顶部的子凸点包括子凸点本体和位于所述子凸 点本体表面的子凸点尾部。
9. 如权利要求 1所述的半导体器件的封装方法， 其特征在于， 所述凸点的材 料为铜、 金、 银、 铜合金、 金合金或银合金， 所述焊球的材料为锡或锡合 金。
10.—种半导体器件的封装件， 其特征在于， 包括：
芯片， 所述芯片表面具有焊盘； 位于所述芯片表面的钝化层， 所述钝化层具有开口， 所述开口暴露出部分 焊盘；
位于所述焊盘表面的凸点， 所述凸点的尺寸小于所述开口的尺寸； 覆盖所述凸点表面、 且覆盖开口底部焊盘表面的焊球。
11.如权利要求 10所述的半导体器件的封装件， 其特征在于， 还包括： 覆盖所 述凸点的顶部和侧壁的防扩散层， 所述焊球位于防扩散层表面。
12.如权利要求 11所述的半导体器件的封装件， 其特征在于， 所述防扩散层还 覆盖开口底部的焊盘。
13.如权利要求 11所述的半导体器件的封装件， 其特征在于， 所述防扩散层的 材料为镍。
14.如权利要求 11或 12所述的半导体器件的封装件， 其特征在于， 还包括： 覆盖所述防扩散层的浸润层， 所述焊球位于浸润层表面。
15.如权利要求 14所述的半导体器件的封装件， 其特征在于，所述浸润层的材 料中至少包括锡元素、 金元素或银元素。
16.如权利要求 10所述的半导体器件的封装件， 其特征在于，所述凸点包括单 个或多个堆叠的子凸点。
17.如权利要求 10所述的半导体器件的封装件， 其特征在于，所述凸点包括多 个堆叠的子凸点， 位于顶部的子凸点包括子凸点本体和位于所述子凸点本 体表面的子凸点尾部。
18.如权利要求 10所述的半导体器件的封装件， 其特征在于，所述凸点的材料 为铜、 金、 银、 铜合金、 金合金或银合金， 所述焊球的材料为锡或锡合金。
PCT/CN2013/086210 2012-11-08 2013-10-30 半导体器件的封装件和封装方法 WO2014071813A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/440,876 US9379077B2 (en) 2012-11-08 2013-10-30 Metal contact for semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201210445562.8A CN102931164B (zh) 2012-11-08 2012-11-08 半导体器件的封装件
CN201210444454.9 2012-11-08
CN201210445562.8 2012-11-08
CN201210444454.9A CN102931110B (zh) 2012-11-08 2012-11-08 半导体器件的封装方法

Publications (1)

Publication Number Publication Date
WO2014071813A1 true WO2014071813A1 (zh) 2014-05-15

Family

ID=50684042

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/086210 WO2014071813A1 (zh) 2012-11-08 2013-10-30 半导体器件的封装件和封装方法

Country Status (2)

Country Link
US (1) US9379077B2 (zh)
WO (1) WO2014071813A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10833033B2 (en) 2011-07-27 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Bump structure having a side recess and semiconductor structure including the same
US9564409B2 (en) * 2015-01-27 2017-02-07 Semiconductor Components Industries, Llc Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel
WO2019079937A1 (en) 2017-10-23 2019-05-02 Boe Technology Group Co., Ltd. INTEGRATED CIRCUIT CHIP, DISPLAY APPARATUS, AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT CHIP
US10699948B2 (en) * 2017-11-13 2020-06-30 Analog Devices Global Unlimited Company Plated metallization structures
KR20190085590A (ko) * 2018-01-11 2019-07-19 삼성전자주식회사 반도체 장치, 이를 포함하는 반도체 패키지 및 이의 제조 방법
KR20210012557A (ko) * 2019-07-25 2021-02-03 삼성전자주식회사 반도체 패키지 및 이를 포함하는 반도체 모듈
US11621209B2 (en) * 2021-08-17 2023-04-04 Qualcomm Incorporated Semiconductor device thermal bump

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110017153A (ko) * 2009-08-13 2011-02-21 삼성전기주식회사 볼 그리드 어레이 패키지 기판 및 그 제조방법
US8022530B2 (en) * 2007-12-05 2011-09-20 Unimicron Technology Corp. Package substrate having electrically connecting structure
CN102931110A (zh) * 2012-11-08 2013-02-13 南通富士通微电子股份有限公司 半导体器件的封装方法
CN102931164A (zh) * 2012-11-08 2013-02-13 南通富士通微电子股份有限公司 半导体器件的封装件

Family Cites Families (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW448524B (en) 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
JP4750926B2 (ja) 2000-06-06 2011-08-17 富士通セミコンダクター株式会社 半導体装置
TW490821B (en) 2000-11-16 2002-06-11 Orient Semiconductor Elect Ltd Application of wire bonding technique on manufacture of wafer bump and wafer level chip scale package
CN1185707C (zh) 2002-06-17 2005-01-19 威盛电子股份有限公司 凸块底缓冲金属结构
US6696757B2 (en) * 2002-06-24 2004-02-24 Texas Instruments Incorporated Contact structure for reliable metallic interconnection
JP2004247522A (ja) 2003-02-14 2004-09-02 Seiko Epson Corp 半導体装置及びその製造方法
JP2005136035A (ja) 2003-10-29 2005-05-26 Matsushita Electric Ind Co Ltd バンプ電極構造およびバンプ形成方法
JP3929966B2 (ja) 2003-11-25 2007-06-13 新光電気工業株式会社 半導体装置及びその製造方法
US7068138B2 (en) 2004-01-29 2006-06-27 International Business Machines Corporation High Q factor integrated circuit inductor
JP2005286087A (ja) 2004-03-30 2005-10-13 Nec Infrontia Corp 半導体装置
JP2006229018A (ja) 2005-02-18 2006-08-31 Matsushita Electric Ind Co Ltd テープキャリア基板およびその製造方法および半導体装置
GB2438788B (en) 2005-02-24 2009-03-11 Agere Systems Inc Structure and method for fabricating flip chip devices
DE102005014665A1 (de) * 2005-03-29 2006-11-02 Infineon Technologies Ag Substrat zur Herstellung einer Lötverbindung mit einem zweiten Substrat
US7488680B2 (en) 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers
JP4738971B2 (ja) 2005-10-14 2011-08-03 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
JP4247690B2 (ja) 2006-06-15 2009-04-02 ソニー株式会社 電子部品及その製造方法
JP2008053568A (ja) 2006-08-25 2008-03-06 Nec Electronics Corp 半導体装置および半導体装置の製造方法
KR101328551B1 (ko) 2006-10-02 2013-11-13 삼성전자주식회사 반도체 장치
JP4995551B2 (ja) 2006-12-01 2012-08-08 ローム株式会社 半導体装置及び半導体装置の製造方法
CN101211791B (zh) 2006-12-27 2010-05-12 日月光半导体制造股份有限公司 晶圆级芯片封装制程与芯片封装结构
US8749065B2 (en) * 2007-01-25 2014-06-10 Tera Probe, Inc. Semiconductor device comprising electromigration prevention film and manufacturing method thereof
US7485564B2 (en) 2007-02-12 2009-02-03 International Business Machines Corporation Undercut-free BLM process for Pb-free and Pb-reduced C4
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US7713860B2 (en) 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump on I/O pad
US7935408B2 (en) 2007-10-26 2011-05-03 International Business Machines Corporation Substrate anchor structure and method
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US20090200675A1 (en) 2008-02-11 2009-08-13 Thomas Goebel Passivated Copper Chip Pads
JP2009224581A (ja) 2008-03-17 2009-10-01 Sanyo Electric Co Ltd 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、電極構造、携帯機器
US7859122B2 (en) * 2008-04-14 2010-12-28 International Business Machines Corporation Final via structures for bond pad-solder ball interconnections
KR100979497B1 (ko) * 2008-06-17 2010-09-01 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP2010077456A (ja) 2008-09-24 2010-04-08 Jfe Steel Corp 溶融亜鉛めっき鋼板およびその製造方法
CN101728347B (zh) 2008-10-22 2011-05-04 中芯国际集成电路制造(上海)有限公司 封装结构及其制造方法
JP2010177456A (ja) 2009-01-29 2010-08-12 Toshiba Corp 半導体デバイス
KR101534682B1 (ko) 2009-03-13 2015-07-08 삼성전자주식회사 범프에 스틱을 구비하는 반도체 장치
TWI471977B (zh) 2009-05-15 2015-02-01 Xintec Inc 功率金氧半場效電晶體封裝體
US8659155B2 (en) 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8748305B2 (en) 2009-11-17 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure for semiconductor devices
US8399987B2 (en) 2009-12-04 2013-03-19 Samsung Electronics Co., Ltd. Microelectronic devices including conductive vias, conductive caps and variable thickness insulating layers
US8232137B2 (en) 2009-12-10 2012-07-31 Intersil Americas Inc. Heat conduction for chip stacks and 3-D circuits
US8492891B2 (en) 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
US20110266670A1 (en) * 2010-04-30 2011-11-03 Luke England Wafer level chip scale package with annular reinforcement structure
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8410576B2 (en) 2010-06-16 2013-04-02 National Semiconductor Corporation Inductive structure and method of forming the inductive structure with an attached core structure
JP5502624B2 (ja) 2010-07-08 2014-05-28 新光電気工業株式会社 配線基板の製造方法及び配線基板
US8755196B2 (en) * 2010-07-09 2014-06-17 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
JP2012054297A (ja) 2010-08-31 2012-03-15 Kyocer Slc Technologies Corp 配線基板およびその製造方法
JP2012080043A (ja) 2010-10-06 2012-04-19 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US20120261813A1 (en) 2011-04-15 2012-10-18 International Business Machines Corporation Reinforced via farm interconnect structure, a method of forming a reinforced via farm interconnect structure and a method of redesigning an integrated circuit chip to include such a reinforced via farm interconnect structure
US8786081B2 (en) 2011-07-27 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for circuit routing by way of under-bump metallization
US9905524B2 (en) 2011-07-29 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures in semiconductor device and packaging assembly
US8557684B2 (en) 2011-08-23 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit (3DIC) formation process
CN102270590A (zh) 2011-09-01 2011-12-07 苏州晶方半导体科技股份有限公司 晶圆级封装结构及封装方法
US8871629B2 (en) 2011-11-08 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of and semiconductor devices with ball strength improvement
US8508043B2 (en) 2011-11-16 2013-08-13 International Business Machines Corporation Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump
CN102437066A (zh) 2011-12-19 2012-05-02 南通富士通微电子股份有限公司 一种高可靠圆片级柱状凸点封装方法
CN102496580B (zh) 2011-12-19 2016-02-03 南通富士通微电子股份有限公司 一种焊料凸点的形成方法
CN102437065A (zh) 2011-12-19 2012-05-02 南通富士通微电子股份有限公司 高可靠芯片级封装方法
US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8629557B2 (en) * 2012-03-08 2014-01-14 International Business Machines Corporation Structures and methods for detecting solder wetting of pedestal sidewalls
CN102664174A (zh) 2012-04-19 2012-09-12 日月光半导体制造股份有限公司 半导体封装构造
US8741691B2 (en) 2012-04-20 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating three dimensional integrated circuit
US8653662B2 (en) 2012-05-02 2014-02-18 International Business Machines Corporation Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits
US8865585B2 (en) 2012-07-11 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming post passivation interconnects
KR101960686B1 (ko) 2012-08-10 2019-03-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9275924B2 (en) 2012-08-14 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having a recess filled with a molding compound
US9006101B2 (en) 2012-08-31 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
US9112007B2 (en) 2012-09-14 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Through via structure and method
CN102915985B (zh) 2012-10-09 2015-06-03 天津大学 一种功率电子器件双面粘接结构及制备方法
JP6024400B2 (ja) 2012-11-07 2016-11-16 ソニー株式会社 半導体装置、半導体装置の製造方法、及びアンテナスイッチモジュール
CN202917476U (zh) 2012-11-08 2013-05-01 南通富士通微电子股份有限公司 芯片封装结构
CN102931101B (zh) 2012-11-08 2016-03-30 南通富士通微电子股份有限公司 芯片封装方法
CN203013710U (zh) 2012-11-08 2013-06-19 南通富士通微电子股份有限公司 半导体器件的封装件
CN102931099B (zh) 2012-11-08 2016-05-18 南通富士通微电子股份有限公司 半导体器件的形成方法
CN202917483U (zh) 2012-11-08 2013-05-01 南通富士通微电子股份有限公司 半导体器件
CN102931158B (zh) 2012-11-08 2015-12-09 南通富士通微电子股份有限公司 芯片封装结构
CN102931098B (zh) 2012-11-08 2015-06-03 南通富士通微电子股份有限公司 芯片封装方法
CN102915982B (zh) 2012-11-08 2015-03-11 南通富士通微电子股份有限公司 半导体器件
CN202917475U (zh) 2012-11-08 2013-05-01 南通富士通微电子股份有限公司 芯片封装结构
US9773732B2 (en) 2013-03-06 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for packaging pad structure
US8969191B2 (en) 2013-07-16 2015-03-03 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure
US9252110B2 (en) 2014-01-17 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming same
US9209131B2 (en) 2014-01-21 2015-12-08 Qualcomm Incorporated Toroid inductor in redistribution layers (RDL) of an integrated device
US20150214127A1 (en) 2014-01-24 2015-07-30 Qualcomm Incorporated Integrated device comprising a substrate with aligning trench and/or cooling cavity

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8022530B2 (en) * 2007-12-05 2011-09-20 Unimicron Technology Corp. Package substrate having electrically connecting structure
KR20110017153A (ko) * 2009-08-13 2011-02-21 삼성전기주식회사 볼 그리드 어레이 패키지 기판 및 그 제조방법
CN102931110A (zh) * 2012-11-08 2013-02-13 南通富士通微电子股份有限公司 半导体器件的封装方法
CN102931164A (zh) * 2012-11-08 2013-02-13 南通富士通微电子股份有限公司 半导体器件的封装件

Also Published As

Publication number Publication date
US9379077B2 (en) 2016-06-28
US20150303159A1 (en) 2015-10-22

Similar Documents

Publication Publication Date Title
WO2014071813A1 (zh) 半导体器件的封装件和封装方法
TWI453840B (zh) 半導體元件的製造方法
US9773755B2 (en) Substrate interconnections having different sizes
US9165888B2 (en) Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
US8405199B2 (en) Conductive pillar for semiconductor substrate and method of manufacture
JP4850392B2 (ja) 半導体装置の製造方法
TWI527170B (zh) 半導體封裝件及其製法
US20110291267A1 (en) Semiconductor wafer structure and multi-chip stack structure
US9349673B2 (en) Substrate, method of manufacturing substrate, semiconductor device, and electronic apparatus
JP2005303258A (ja) デバイス及びその製造方法
US9293432B2 (en) Metal contact for chip packaging structure
CN102931164B (zh) 半导体器件的封装件
US8742584B2 (en) Semiconductor device
TW201023330A (en) Integrated circuit
JP5663607B2 (ja) 半導体装置
CN102931110B (zh) 半导体器件的封装方法
US20120153460A1 (en) Bump structure and manufacturing method thereof
KR100959606B1 (ko) 스택 패키지 및 그의 제조 방법
JP2007258438A (ja) 半導体装置及びその製造方法
CN203013710U (zh) 半导体器件的封装件
JP2003068779A (ja) 半導体装置及びその製造方法
US9589815B2 (en) Semiconductor IC packaging methods and structures
JP2007103953A (ja) 導電性粒子を含むバンプを備える半導体チップ及びこれを製造する方法
JP2009016830A (ja) チップ積層構造物及びその製造方法
TWI479617B (zh) 半導體結構及其製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13852629

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14440876

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13852629

Country of ref document: EP

Kind code of ref document: A1