JP4738971B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4738971B2 JP4738971B2 JP2005300576A JP2005300576A JP4738971B2 JP 4738971 B2 JP4738971 B2 JP 4738971B2 JP 2005300576 A JP2005300576 A JP 2005300576A JP 2005300576 A JP2005300576 A JP 2005300576A JP 4738971 B2 JP4738971 B2 JP 4738971B2
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Description
1.半導体装置の構成例
以下、図1及び図2を参照して、この発明の半導体装置10の構成例につき説明する。
次に、図1及び図2を参照して説明した半導体装置10の製造方法について、図3及び図4を参照して説明する。
次に、図5及び図6を参照して、この発明の第2の実施の形態について説明する。
まず、この実施の形態の半導体装置の構成例につき、図5を参照して説明する。なお、この例の半導体装置10にかかる平面図は、既に説明した図1(A)と何ら変わるところがないため図示を省略する。
次に、図5を参照して説明した半導体装置10の製造方法について、図6を参照して説明する。
次に、図7及び図8を参照して、この発明の第3の実施の形態について説明する。
まず、この実施の形態の半導体装置の構成例につき、図7を参照して説明する。なお、この例の半導体装置10にかかる平面図は、既に説明した図1(A)と何ら変わるところがないため図示を省略する。
次に、図7を参照して説明した半導体装置10の製造方法について、図8を参照して説明する。
11:第1部分領域
12:第2部分領域
20:半導体基板(半導体ウェハ)
20a:第1の主表面
20b:第2の主表面
30:半導体チップ
31:チップ形成領域
34:電極パッド
40:絶縁膜
40a:上面
42:再配線パターン(配線パターン)
42a:配線
44:封止部(封止樹脂)
44’:前駆封止部
44a,44’a:上面
44b:平坦面
44c:島状部分
46:柱状電極
46’:前駆柱状電極
46a,46’a:頂面
46P:突起部
46Q:本体部
46R:側面
46S(溝部の)底面又は(本体部の)上面
46b:露出面
46c:側面(側壁面)
46X:突起部
46Y:本体部
47:半田ボール
50:溝部
52:縦溝部
52a:第1縦溝部
52b:第2縦溝部
52c:第3縦溝部
52d:第4縦溝部
52e:第5縦溝部
52f:第6縦溝部
54:横溝部
54a:第1横溝部
54b:第2横溝部
54c:第3横溝部
54d:第4横溝部
54e:第5横溝部
54f:第6横溝部
56:幅広縦溝部
56a:第1幅広縦溝部
56b:第2幅広縦溝部
56c:第3幅広縦溝部
56d:第4幅広縦溝部
57:幅広横溝部
57a:第1幅広横溝部
57b:第2幅広横溝部
57c:第3幅広横溝部
57d:第4幅広横溝部
58:縦断溝部
58a:第1縦断溝部
58b:第2縦断溝部
58c:第3縦断溝部
58d:第4縦断溝部
59:横断溝部
59a:第1横断溝部
59b:第2横断溝部
59c:第3横断溝部
59d:第4横断溝部
Claims (4)
- 一方の主表面に形成された複数の電極パッドを有する半導体基板と、
前記電極パッドの各々の上面を露出させて前記一方の主表面上に形成されている絶縁膜と、
前記電極パッドの各々にそれぞれ接続されていて、該電極パッドから導出されて前記絶縁膜上を延在している複数の配線からなる再配線パターンと、
前記配線のいずれかにそれぞれ接続されて前記一方の主表面に対して垂直な方向に設けられている複数の柱状電極であって、前記配線側の本体部と該本体部と一体的に連続して設けられている突起部とからなる当該柱状電極と、
前記再配線パターン及び前記絶縁膜上に設けられていて、前記柱状電極の周囲を埋め込んでいるとともに、該柱状電極の前記突起部の頂面と同一の高さの上面を有する封止部と、
前記突起部に設けられていて前記柱状電極との電気的な接続を形成している半田ボールとを具えており、
前記突起部は、該突起部の頂面から該突起部と前記本体部との境界に至る深さで該突起部中に形成されている溝部に露出する露出面を有し、及び
前記半田ボールは、前記突起部の頂角と前記露出面とに接合して前記柱状電極に電気的に接続されており、
複数の前記柱状電極はマトリクス状に配置されており、
前記溝部はマトリクス状に配列されている複数の前記柱状電極の行方向又は列方向に互いに平行にかつ互いに隣接する前記柱状電極間の前記封止部を貫いて延在していることを特徴とする半導体装置。 - 一方の主表面に形成された複数の電極パッドを有する半導体基板と、
前記電極パッドの各々の上面を露出させて前記一方の主表面上に形成されている絶縁膜と、
前記電極パッドの各々にそれぞれ接続されていて、該電極パッドから導出されて前記絶縁膜上を延在している複数の配線からなる再配線パターンと、
前記配線のいずれかにそれぞれ接続されて前記一方の主表面に対して垂直な方向に設けられている複数の柱状電極であって、前記配線側の本体部と該本体部と一体的に連続して設けられている突起部とからなる当該柱状電極と、
前記再配線パターン及び前記絶縁膜上に設けられていて、前記柱状電極の周囲を埋め込んでいるとともに、該柱状電極の前記突起部の頂面と同一の高さの上面を有する封止部と、
前記突起部に設けられていて前記柱状電極との電気的な接続を形成している半田ボールとを具えており、
前記突起部は、該突起部の頂面から該突起部と前記本体部との境界に至る深さで該突起部中に形成されている溝部に露出する露出面を有し、及び
前記半田ボールは、前記突起部の頂角と前記露出面とに接合して前記柱状電極に電気的に接続されており、
複数の前記柱状電極はマトリクス状に配置されており、
前記溝部はマトリクス状に配列されている複数の前記柱状電極の行方向及び列方向の両方向に沿って互いに交差してかつ互いに隣接する前記柱状電極間の前記封止部を貫いて延在していることを特徴とする半導体装置。 - 個々の半導体チップ形成領域に回路素子が設けられていて、一方の主表面に該回路素子に接続された複数の電極パッドを有する半導体基板を準備する工程と、
一方の前記主表面上に、前記電極パッドの一部分を露出させる絶縁膜を形成する工程と、
前記絶縁膜上に、前記電極パッドに接続して延在する複数の配線からなる再配線パターンを形成する工程と、
複数の前記配線のいずれかにそれぞれ接続して一方の前記主表面に対して垂直な複数の前駆柱状電極を形成する工程と、
前記絶縁膜上に、前記再配線パターンと前記前駆柱状電極とを埋め込んでいて、前記前駆柱状電極の頂面と同一の高さの上面を有する封止部を形成する工程と、
前記前駆柱状電極の頭部の側を頂面から該前駆柱状電極の長さの一部分にわたる深さで該前駆柱状電極の一部分を除去して、前記頭部を一方の前記主表面と平行な方向に貫く溝部を形成することによって、該溝部の下側に存在する本体部と、該本体部と一体的にそれぞれ連続し、側面が前記溝部に面している複数の突起部とからなる柱状電極を形成する工程と、
それぞれの前記突起部を覆って該突起部の頂面及び前記溝部に露出する該突起部の側面と電気的に接続される半田ボールを形成する工程と、
前記半導体基板に前記半田ボールが形成されている構造体を半導体チップ単位で個片化する工程と
を含み、
前記前駆柱状電極を形成する工程は、複数の前記前駆柱状電極をマトリクス状に配列して形成する工程であり、
前記溝部を形成する工程は、該溝部をマトリクス状に配列されている複数の前記前駆柱状電極の行方向又は列方向に互いに平行にかつ互いに隣接する前記前駆柱状電極間の前記封止部を貫いて直線状に延在させて、及び前記前駆柱状電極の径よりも狭く形成する工程であることを特徴とする半導体装置の製造方法。 - 個々の半導体チップ形成領域に回路素子が設けられていて、一方の主表面に該回路素子に接続された複数の電極パッドを有する半導体基板を準備する工程と、
一方の前記主表面上に、前記電極パッドの一部分を露出させる絶縁膜を形成する工程と、
前記絶縁膜上に、前記電極パッドに接続して延在する複数の配線からなる再配線パターンを形成する工程と、
複数の前記配線のいずれかにそれぞれ接続して一方の前記主表面に対して垂直な複数の前駆柱状電極を形成する工程と、
前記絶縁膜上に、前記再配線パターンと前記前駆柱状電極とを埋め込んでいて、前記前駆柱状電極の頂面と同一の高さの上面を有する封止部を形成する工程と、
前記前駆柱状電極の頭部の側を頂面から該前駆柱状電極の長さの一部分にわたる深さで該前駆柱状電極の一部分を除去して、前記頭部を一方の前記主表面と平行な方向に貫く溝部を形成することによって、該溝部の下側に存在する本体部と、該本体部と一体的にそれぞれ連続し、側面が前記溝部に面している複数の突起部とからなる柱状電極を形成する工程と、
それぞれの前記突起部を覆って該突起部の頂面及び前記溝部に露出する該突起部の側面と電気的に接続される半田ボールを形成する工程と、
前記半導体基板に前記半田ボールが形成されている構造体を半導体チップ単位で個片化する工程と
を含み、
前記前駆柱状電極を形成する工程は、複数の前記前駆柱状電極をマトリクス状に配列して形成する工程であり、
前記溝部を形成する工程は、該溝部をマトリクス状に配列されている複数の前記前駆柱状電極の行方向及び列方向の両方向に沿って互いに交差してかつ互いに隣接する前記前駆柱状電極間の前記封止部を貫いて直線状に延在させて、及び前記前駆柱状電極の径よりも狭く形成する工程であることを特徴とする半導体装置の製造方法。
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CN102931099B (zh) * | 2012-11-08 | 2016-05-18 | 南通富士通微电子股份有限公司 | 半导体器件的形成方法 |
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CN102915986B (zh) | 2012-11-08 | 2015-04-01 | 南通富士通微电子股份有限公司 | 芯片封装结构 |
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