JP4903014B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4903014B2 JP4903014B2 JP2006139622A JP2006139622A JP4903014B2 JP 4903014 B2 JP4903014 B2 JP 4903014B2 JP 2006139622 A JP2006139622 A JP 2006139622A JP 2006139622 A JP2006139622 A JP 2006139622A JP 4903014 B2 JP4903014 B2 JP 4903014B2
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- 239000004065 semiconductor Substances 0.000 title claims description 78
- 239000011347 resin Substances 0.000 claims description 86
- 229920005989 resin Polymers 0.000 claims description 86
- 239000000463 material Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 16
- 230000002093 peripheral effect Effects 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
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- H—ELECTRICITY
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
(1)樹脂層には半田端子がそれぞれ接続される金属製のポストを複数設け、溝は樹脂層の外側縁に沿って外側縁とポストとの間に設けたこと。
(2)半導体チップ及び樹脂層は平面視矩形形状とし、溝は矩形形状の樹脂層の4つの外周縁のうち、隣り合った2つの外周縁に沿って設けたこと。
(3)溝は装着面に対して所定の角度に傾斜させたこと。
(4)溝は幅方向に沿って深さの異ならせた段差を有すること。
10 半導体チップ
11 電極
12 電極配設面
20 樹脂層
21 ポスト
22 再配線
23 溝
24 外側縁
30 半田端子
Claims (5)
- 一側面に複数の電極を設けた半導体チップと、前記電極が形成されている前記半導体チップの電極配設面に重ね合わせて設けた樹脂層を備え、この樹脂層の表面を装着面としてアンダーフィル材を介して実装基板に装着される半導体装置において、
前記樹脂層の装着面の外側縁に沿ってのみ溝を設け、当該溝により前記装着面を複数の面に分断したことを特徴とする半導体装置。 - 前記樹脂層には、半田端子がそれぞれ接続される金属製のポストを複数設け、
前記溝は、前記樹脂層の外側縁に沿って、外側縁と前記ポストとの間に設けたことを特徴とする請求項1記載の半導体装置。 - 前記半導体チップ及び前記樹脂層は平面視矩形形状とし、前記溝は、矩形形状の前記樹脂層の4つの外周縁のうち、隣り合った2つの外周縁に沿って設けたことを特徴とする請求項2記載の半導体装置。
- 前記溝は、前記装着面に対して所定の角度に傾斜させたことを特徴とする請求項1〜3のいずれか1項に記載の半導体装置。
- 前記溝は、幅方向に沿って深さの異ならせた段差を有することを特徴とする請求項1〜
3のいずれか1項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006139622A JP4903014B2 (ja) | 2006-05-18 | 2006-05-18 | 半導体装置 |
US11/798,938 US20070267757A1 (en) | 2006-05-18 | 2007-05-17 | Semiconductor device |
US12/457,816 US20090261467A1 (en) | 2006-05-18 | 2009-06-23 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006139622A JP4903014B2 (ja) | 2006-05-18 | 2006-05-18 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007311575A JP2007311575A (ja) | 2007-11-29 |
JP4903014B2 true JP4903014B2 (ja) | 2012-03-21 |
Family
ID=38711280
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006139622A Active JP4903014B2 (ja) | 2006-05-18 | 2006-05-18 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (2) | US20070267757A1 (ja) |
JP (1) | JP4903014B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007044620A1 (de) * | 2007-09-19 | 2009-04-16 | Semikron Elektronik Gmbh & Co. Kg | Anordnung mit einer Verbindungseinrichtung und mindestens einem Halbleiterbauelement |
JP2010171107A (ja) * | 2009-01-21 | 2010-08-05 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
IT201700103511A1 (it) * | 2017-09-15 | 2019-03-15 | St Microelectronics Srl | Dispositivo microelettronico dotato di connessioni protette e relativo processo di fabbricazione |
US12035475B2 (en) * | 2021-05-07 | 2024-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package with stress reduction design and method for forming the same |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100205321B1 (ko) * | 1996-12-30 | 1999-07-01 | 구본준 | 크랙방지 패턴을 갖는 반도체소자의 제조방법 |
US6011301A (en) * | 1998-06-09 | 2000-01-04 | Stmicroelectronics, Inc. | Stress reduction for flip chip package |
JP3446825B2 (ja) * | 1999-04-06 | 2003-09-16 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
US6710446B2 (en) * | 1999-12-30 | 2004-03-23 | Renesas Technology Corporation | Semiconductor device comprising stress relaxation layers and method for manufacturing the same |
JP3866073B2 (ja) * | 2001-10-10 | 2007-01-10 | 株式会社フジクラ | 半導体パッケージ |
JP2003347471A (ja) * | 2002-05-24 | 2003-12-05 | Fujikura Ltd | 半導体装置及びその製造方法 |
US7064452B2 (en) * | 2003-11-04 | 2006-06-20 | Tai-Saw Technology Co., Ltd. | Package structure with a retarding structure and method of making same |
US7084011B2 (en) * | 2003-12-30 | 2006-08-01 | Texas Instruments Incorporated | Forming a chip package having a no-flow underfill |
CN100411155C (zh) * | 2004-01-27 | 2008-08-13 | 株式会社村田制作所 | 层叠型电子元器件及其制造方法 |
SG139753A1 (en) * | 2004-03-15 | 2008-02-29 | Yamaha Corp | Semiconductor device |
JP2006100534A (ja) * | 2004-09-29 | 2006-04-13 | Casio Micronics Co Ltd | 半導体装置 |
DE102005003390B4 (de) * | 2005-01-24 | 2007-09-13 | Qimonda Ag | Substrat für ein FBGA-Halbleiterbauelement |
JP4738971B2 (ja) * | 2005-10-14 | 2011-08-03 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
-
2006
- 2006-05-18 JP JP2006139622A patent/JP4903014B2/ja active Active
-
2007
- 2007-05-17 US US11/798,938 patent/US20070267757A1/en not_active Abandoned
-
2009
- 2009-06-23 US US12/457,816 patent/US20090261467A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20070267757A1 (en) | 2007-11-22 |
US20090261467A1 (en) | 2009-10-22 |
JP2007311575A (ja) | 2007-11-29 |
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