JP2010171107A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】半導体チップ2と、半導体チップ2を被覆し封止する封止樹脂3と、を備える半導体装置1である。半導体チップ2の表層部には凹部4が形成されている。凹部4には、その所定部位よりも深い位置に、該所定部位よりも大径の部分が形成されている。凹部4内に封止樹脂3が入り込むことにより、封止樹脂3と半導体チップ2とが相互に係合している。これにより、半導体チップ2と封止樹脂3との密着性を向上することができる。
【選択図】図1
Description
図1は本実施形態に係る半導体装置1の構成を示す正面断面図、図2は半導体装置1の平面図、図3は図1の要部拡大図である。なお、図2においては、封止樹脂3の輪郭を仮想線で示し、実際には封止樹脂3により覆われて視認できない内部構造を見せている。
上記の第1の実施形態では、逆テーパー形状の凹部4を例示したが、第2の実施形態では、凹部4の形状のその他の例を説明する。図10乃至図15の各々は、第2の実施形態で説明する凹部4の形状を示す図であり、それぞれ切断端面の構造を示す。以下、それぞれの凹部4の形状の特徴を説明する。
2 半導体チップ
3 封止樹脂
4 凹部
22 表面電極
Claims (10)
- 半導体チップと、
前記半導体チップを被覆し封止する封止樹脂と、
を備え、
前記半導体チップの表層部には凹部が形成され、
前記凹部には、その所定部位よりも深い位置に、前記所定部位よりも大径の部分が形成され、
前記凹部内に前記封止樹脂が入り込んでいることを特徴とする半導体装置。 - 前記凹部は、その開口端よりも大径の部分を、該開口端よりも深い位置に有することを特徴とする請求項1に記載の半導体装置。
- 前記凹部の少なくとも一部分は、深くなるにつれて拡径する形状であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記凹部の全体が、深くなるにつれて拡径する形状であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記深くなるにつれて拡径する前記形状の部分は、逆テーパー形状であることを特徴とする請求項3又は4に記載の半導体装置。
- 前記所定部位は、深さにかかわらず一定の径であることを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。
- 前記大径の部分は、深さにかかわらず一定の径であることを特徴とする請求項1、2、3、6のいずれか一項に記載の半導体装置。
- 前記半導体チップは、その表層にメタル層を備え、
前記メタル層に前記凹部が形成されていることを特徴とする請求項1乃至7のいずれか一項に記載の半導体装置。 - 前記メタル層は、表面電極であることを特徴とする請求項8に記載の半導体装置。
- 半導体チップの表層部に凹部を形成する凹部形成工程と、
前記半導体チップを封止樹脂により被覆し封止する樹脂封止工程と、
を備え、
前記凹部形成工程では、前記凹部の所定部位よりも深い位置に前記所定部位よりも大径の部分がある形状の凹部を形成し、
前記樹脂封止工程では、前記凹部内に前記封止樹脂を入り込ませて前記封止樹脂と前記半導体チップとを相互に係合させることを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009010659A JP2010171107A (ja) | 2009-01-21 | 2009-01-21 | 半導体装置及びその製造方法 |
US12/689,680 US8350392B2 (en) | 2009-01-21 | 2010-01-19 | Semiconductor device having recess with varying width and method of manufacturing the same |
Applications Claiming Priority (1)
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JP2009010659A JP2010171107A (ja) | 2009-01-21 | 2009-01-21 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2010171107A true JP2010171107A (ja) | 2010-08-05 |
JP2010171107A5 JP2010171107A5 (ja) | 2012-02-16 |
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JP2009010659A Pending JP2010171107A (ja) | 2009-01-21 | 2009-01-21 | 半導体装置及びその製造方法 |
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US (1) | US8350392B2 (ja) |
JP (1) | JP2010171107A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014181766A1 (ja) * | 2013-05-07 | 2014-11-13 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及び半導体装置の製造方法 |
JP2019149466A (ja) * | 2018-02-27 | 2019-09-05 | Tdk株式会社 | 回路モジュール |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2514547A (en) * | 2013-05-23 | 2014-12-03 | Melexis Technologies Nv | Packaging of semiconductor devices |
JP6210818B2 (ja) * | 2013-09-30 | 2017-10-11 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US9230809B2 (en) * | 2013-10-17 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned double patterning |
TWI613768B (zh) * | 2017-03-20 | 2018-02-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
JP2022043997A (ja) * | 2020-09-04 | 2022-03-16 | エスティーマイクロエレクトロニクス エス.アール.エル. | 信頼性を改善した電子装置の要素の製造方法、及び関連要素、電子装置、及び電子機器 |
US20220139793A1 (en) * | 2020-11-04 | 2022-05-05 | Cree, Inc. | Power semiconductor devices with improved overcoat adhesion and/or protection |
EP4280273A1 (en) * | 2022-05-19 | 2023-11-22 | Mitsubishi Electric R&D Centre Europe B.V. | Semiconductor chip comprising structured metallization with increased reliability, and manufacturing method |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63106133U (ja) * | 1986-12-26 | 1988-07-08 | ||
JPH0357249A (ja) * | 1989-07-25 | 1991-03-12 | Mitsubishi Electric Corp | 半導体装置 |
JPH03153049A (ja) * | 1989-11-10 | 1991-07-01 | Fujitsu Ltd | 半導体装置 |
JPH0653271A (ja) * | 1992-07-30 | 1994-02-25 | Matsushita Electron Corp | 半導体装置のワイヤーボンディング方法 |
JPH06163755A (ja) * | 1992-11-24 | 1994-06-10 | Mitsubishi Electric Corp | 樹脂封止型半導体装置 |
JPH07201906A (ja) * | 1993-12-29 | 1995-08-04 | Sony Corp | パッド電極を有する半導体装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3810204B2 (ja) * | 1998-03-19 | 2006-08-16 | 三菱電機株式会社 | 半導体装置の製造方法および半導体装置 |
JP2000124235A (ja) * | 1998-10-16 | 2000-04-28 | Oki Electric Ind Co Ltd | 樹脂封止半導体装置 |
JP4903014B2 (ja) * | 2006-05-18 | 2012-03-21 | ローム株式会社 | 半導体装置 |
-
2009
- 2009-01-21 JP JP2009010659A patent/JP2010171107A/ja active Pending
-
2010
- 2010-01-19 US US12/689,680 patent/US8350392B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63106133U (ja) * | 1986-12-26 | 1988-07-08 | ||
JPH0357249A (ja) * | 1989-07-25 | 1991-03-12 | Mitsubishi Electric Corp | 半導体装置 |
JPH03153049A (ja) * | 1989-11-10 | 1991-07-01 | Fujitsu Ltd | 半導体装置 |
JPH0653271A (ja) * | 1992-07-30 | 1994-02-25 | Matsushita Electron Corp | 半導体装置のワイヤーボンディング方法 |
JPH06163755A (ja) * | 1992-11-24 | 1994-06-10 | Mitsubishi Electric Corp | 樹脂封止型半導体装置 |
JPH07201906A (ja) * | 1993-12-29 | 1995-08-04 | Sony Corp | パッド電極を有する半導体装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014181766A1 (ja) * | 2013-05-07 | 2014-11-13 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及び半導体装置の製造方法 |
JP2019149466A (ja) * | 2018-02-27 | 2019-09-05 | Tdk株式会社 | 回路モジュール |
JP7056226B2 (ja) | 2018-02-27 | 2022-04-19 | Tdk株式会社 | 回路モジュール |
US11606888B2 (en) | 2018-02-27 | 2023-03-14 | Tdk Corporation | Circuit module |
US11812542B2 (en) | 2018-02-27 | 2023-11-07 | Tdk Corporation | Circuit module |
Also Published As
Publication number | Publication date |
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US20100181688A1 (en) | 2010-07-22 |
US8350392B2 (en) | 2013-01-08 |
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