TWI404184B - 多晶片引線架封裝 - Google Patents

多晶片引線架封裝 Download PDF

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Publication number
TWI404184B
TWI404184B TW094136371A TW94136371A TWI404184B TW I404184 B TWI404184 B TW I404184B TW 094136371 A TW094136371 A TW 094136371A TW 94136371 A TW94136371 A TW 94136371A TW I404184 B TWI404184 B TW I404184B
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TW
Taiwan
Prior art keywords
die
lead frame
package
face
lead
Prior art date
Application number
TW094136371A
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English (en)
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TW200629516A (en
Inventor
Jongwoo Ha
Taebok Jung
Original Assignee
Chippac Inc
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Publication date
Application filed by Chippac Inc filed Critical Chippac Inc
Publication of TW200629516A publication Critical patent/TW200629516A/zh
Application granted granted Critical
Publication of TWI404184B publication Critical patent/TWI404184B/zh

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Description

多晶片引線架封裝
本發明係關於一種半導體晶片封裝及，特定言之，係關於一種具有附著至一引線架之兩個或兩個以上半導體晶粒的引線架封裝。
一習知之引線架由一大體上平坦的金屬件組成，其具有排列於一位於中心的晶粒腳座周圍的周邊引線。在一習知之引線架封裝中，藉由使用一黏接劑將晶粒之背面附著至晶粒腳座，並藉由通過該晶粒上之焊線墊片與引線上之焊線部位之間的線結合將該晶粒電連接至該等引線來將一晶粒黏附於該晶粒腳座。建構具有兩個或兩個以上附著於一引線架並藉由線結合互連之半導體晶粒的引線架封裝是已知的。
舉例而言，美國專利第6,265,763號描述多種多晶片封裝構型，其具有黏附於一引線架晶粒腳座之一第一(下)晶粒，及堆疊於該第一晶粒上之一第二(上)晶粒，兩晶粒藉由線結合與該引線架互連。在某些構型中，該第一晶粒具有周邊焊線墊片，且該第二晶粒比該第一晶粒具有一較小的佔據面積，且相應地，該第二晶粒直接堆疊於該第一晶粒之上(活性)面上。在其他構型中，該第一晶粒具有周邊焊線墊片，且該第二晶粒之佔據面積太大，而不能在不妨礙該第一晶粒上之焊線墊片的情況下將其安裝於該第一晶粒之活性面上；在此等構型中，在該第一晶粒之活性面上有具有 一適當小之佔據面積的一間隔片，且將該第二晶粒黏附於該第一晶粒之上。
U.S.6,285,763指出，以此方式堆疊線結合之晶粒對於具有周邊焊線墊片之晶粒是有效的，但不適宜於具有位於該晶粒中心線附近的結合墊片之晶粒。U.S.6,285,763提出一種具有至少一周邊墊片晶粒及至少一中心墊片晶粒之多晶片封裝，其中該引線架具有一中心晶粒腳座及引線，該等引線經由一間隙與該晶粒腳座分開。一周邊墊片晶粒以一習知之方式附著於該引線架之一面(該"頂"面)上的晶粒腳座上，且一中心墊片晶粒部分附著於該晶粒腳座上，並部分附著於該引線架之另一面(該"底"面)上之引線上，該晶粒之活性面朝向該引線架，且該等中心墊片位於晶粒橫跨該間隙之部分。以習知之方式附著之頂晶粒，藉由在該頂晶粒上之周邊結合墊片與該底晶粒上之中心結合墊片之間穿過的焊線，直接與該中心墊片底晶粒互連；且以習知之方式附著之頂晶粒與底晶粒兩者線結合至該等引線。接著密封完全線結合之組件以密封並保護所有晶粒及焊線。
密封劑必須完全覆蓋該晶粒上之焊線環的事實限制線結合封裝所能達到的薄的程度。意即，除該引線架之厚度及該晶粒之厚度之外，該焊線環高度影響一厚度尺寸(環高度加上該等環上之密封劑厚度)。在製造更薄封裝的驅動下，已進行各種努力以減少線焊線環高度。
本發明提供引線架封裝，在該封裝中兩個或兩個以上半 導體晶粒附著於一引線架之相對面上。該引線架具有排列於一位於中心之晶粒腳座周圍之周邊引線。一第一("上")晶粒附著於該引線架晶粒腳座之一第一("頂")面上，該面可為大體上平坦的。該引線架之第二("底")面被部分切除(諸如藉由部分蝕刻)，以使該晶粒腳座之外部更薄，並使該等引線之內部更薄。該引線架之第二("底")面中之該等部分切除部分提供一空穴，在該空穴中一第二("下")晶粒活性面向上附著。該下晶粒可具有位於該活性表面中心附近之結合墊片，且該下晶粒之電互連可藉由穿過該晶粒腳座與該等引線之間的間隙的焊線來完成；或該下晶粒可藉由覆晶與引線架中之空穴的晶粒附著面互連來附著及電互連。
在一通用態樣中，本發明之特徵為具有一第一("頂")面及一第二("底")面之引線架，該引線架包括一位於中心之晶粒腳座，該晶粒腳座具有一邊界及一邊緣，並包括排列於周邊之引線，每一引線包含一內結合指狀物部分及一外槽脊(land)，在該晶粒腳座之邊緣與該等結合指狀物部分之內末端之間有一間隙。該晶粒腳座之頂面之一表面包括一第一晶粒附著區域。在該晶粒腳座邊界之至少一部分之底面中提供一階梯，且在至少一個引線之結合指狀物部分之至少一部分的底面中提供一階梯，該等階梯共同形成一孔穴，跨越該間隙，且該等階梯具有大體上共平面之下晶粒附著表面，該晶粒附著表面在一大體上平行於該引線架之底面的表面之一平面中。該空穴經尺寸化以容納一第二晶粒之佔據面積，該第二晶粒待在該等階梯之第二晶粒附著區域 附著於該空穴內。一下晶粒附著表面之平面與該引線架底表面之間的距離構成該空穴深度，該深度為至少與該第二晶粒之厚度加第二晶粒附著構件之厚度一樣大。
該引線架可包括兩個或兩個以上該等空穴，每一空穴經尺寸化以容納一額外晶粒之佔據面積，且每一空穴具有至少與該第二晶粒之厚度加額外晶粒附著構件之厚度一樣大的深度。額外晶粒之每一個可具有與第二晶粒相同的佔據面積及厚度，或可具有與其不同的佔據面積及/或厚度。
在某些實施例中，該晶粒腳座為大體上矩形，具有四個大體上直的邊緣部分。在某些實施例中，該等引線經排列以使結合指狀物臨近該等直邊緣部分之至少一個成一列，在該晶粒腳座之直邊緣部分與該結合指狀物部分之內末端之間有一間隙。在該等實施例中，在該等直邊緣部分中的一個之一邊界中形成晶粒腳座階梯，並在相鄰列中之結合指狀物中形成引線階梯，以使該空穴跨越該間隙。某些該等實施例進一步包括一或多個額外空穴，每一空穴包括在該晶粒腳座之直邊緣部分之另一個的邊界中的一晶粒腳座階梯，及在該相鄰列中之結合指狀物中形成的一引線階梯，並跨越該間隙。在某些實施例中，在該晶粒腳座為大體上矩形情況下，可在相反直邊緣部分之邊界中形成兩個空穴；或，可形成四個空穴，在四個邊界之每一個中形成一個。
在另一通用態樣中，本發明之特徵為一半導體封裝，其具有上述之引線架，並具有黏附於該晶粒腳座之頂面之第 一晶粒附著區域的一第一上晶粒，並具有黏附於一空穴中之下晶粒附著區域的一第一下晶粒。在某些實施例中，有兩個或兩個以上空穴，諸如四個空穴，每一空穴具有黏附於該等空穴中的晶粒附著區域之一下晶粒。在某些實施例中，將至少一個額外上晶粒堆疊於該第一晶粒之上並將其黏附其上。一密封劑覆蓋該晶粒及該等相應焊線，及該引線架之表面之除該等晶粒附著區域以外的部分，及，在某些實施例中，使該引線架之底面之下表面保持曝露，且，在某些實施例中，使該等引線之槽脊部分之一區域保持曝露。
在某些實施例中，使用一晶粒附著環氧樹脂或一薄膜黏接劑，將該第一上晶粒活性面向上黏附於該晶粒腳座之頂面上。可使用一晶粒附著環氧樹脂或一薄膜黏接劑，將額外上晶粒黏附於該第一上晶粒上，在必需之處，在經堆疊之晶粒之間使用一間隔片，以容納結合環。第一上晶粒經焊線與引線互連。
在某些實施例中，下晶粒具有位於該活性面之中心線附近之結合墊片，且該下晶粒經定位以使該等結合墊片位於該間隙之下，且該下晶粒使用一晶粒環氧樹脂或一薄膜黏接劑黏附於該空穴之下晶粒附著表面上。藉由穿過晶粒上之結合墊片與引線上之結合部位之間及/或晶粒上之結合墊片與一上晶粒上之結合墊片之間的間隙的焊線，將該下晶粒電互連。
在其他實施例中，該下晶粒黏附於該空穴中之下晶粒附 著表面上，且藉由使用例如焊球或焊料凸塊或金凸塊之晶粒墊片與該空穴中之階梯上之互連部位之間的覆晶互連來電互連。
在另一通用態樣中，本發明之特徵為一多封裝模組，其包括如上述所建構之至少一個封裝，藉由相應引線架上之第二層互連部位之間的焊球或焊線使該等封裝電互連。
現參考圖式更詳細地描述本發明，該等圖式說明本發明之替代實施例。該等圖式係示意性的，展示本發明之特徵及其與其他特徵及結構之間的關係，且未按比例繪製。為改良呈現之清晰度，在說明本發明之實施例之圖中，與其他圖式中所展示之元件一致的元件並未完全特別地重新編號，雖然所有圖中可容易地將其全部識別。
現參看圖1A，其展示一習知之引線架封裝，該封裝具有包括一晶粒腳座12及多個引線11之一引線架，其經排列以使腳座邊緣與引線之間有一間隙。一第一晶粒14安裝於該晶粒腳座12之一第一("頂")表面上，並使用一晶粒附著黏接劑15黏附。晶粒14藉由將晶粒14上之結合墊片與引線11上之結合部位連接之焊線16與該引線架電互連。藉由一密封劑17保護該晶粒與焊線及該引線架之頂表面之區域，此外，該密封劑填滿該晶粒腳座與該等引線邊緣之間的間隙。將引線及晶粒腳座之邊緣底切，如13所展示，以提供該等引線架邊緣與於該引線架之第二("底")面之密封劑之間的經改良的互鎖。在該特定應用中，藉由(例如)焊球(未 圖示)將該引線之底面與(例如)諸如一母板(未圖示)之一印刷電路板相連接，來完成該封裝至電路之電互連。
圖1B展示通常如圖1A中之一習知之引線架，該引線架具有安裝於第一晶粒14上之額外晶粒124。該額外晶粒124使用一黏接劑125黏附於第一晶粒14，且其藉由將晶粒124上之結合墊片與引線11上之結合部位相連接之焊線126與引線架電互連。通常如圖1A中之實施例，該封裝17係被密封。該經堆疊晶粒構型，具有與圖1A中之構型相似之佔據面積，以額外之厚度為代價，獲得該封裝中半導體設備之一較高密度。
圖1B之實施例中的額外晶粒124比第一晶粒14具有一更窄佔據面積，以使安裝於該第一晶粒之上的該額外晶粒不接觸該第一晶粒上之結合墊片。在期望於該第一晶粒上堆疊一較大額外晶粒之處，在該第一晶粒與該額外晶粒之間可使用一間隔片，如圖1C中舉例所展示。在此實施例中，第一晶粒14安裝於該引線架腳座12上，且使用通常如圖1A及1B中之晶粒附著黏接劑15黏附於此。間隔片18(例如，一矽"虛設(dummy)"晶粒)可安裝於該第一晶粒上，並使用一黏接劑135黏附。第二晶粒134安裝於間隔片18上，並使用一黏接劑145黏附於此。藉由將第二晶粒134上之結合墊片與引線11上之結合部位相連接之焊線126，將第二晶粒134電互連。第一晶粒14藉由將晶粒14上之結合墊片與引線11上之結合部位相連接之焊線16來電互連。使間隔片18之厚度，連同黏接劑135及145之厚度，足夠大，以提供第一與 第二晶粒之間的足夠間隙，避免第二晶粒124之下面與焊線16之線迴路之間的接觸。通常如圖1A中之實施例，該封裝17係被密封。
圖1D說明一多晶片引線封裝，其中藉由將晶粒安裝於引線架之底面及頂面上獲得較大晶粒密度。該引線架包括一晶粒腳座112及多個引線111，晶粒腳座邊緣與引線之間具有一間隙。一第一("頂")晶粒164安裝於晶粒腳座112之頂面上，並使用一黏接劑155黏附。第二("底")晶粒154，為"中心墊片"晶片；意即，該晶粒為在其中該等結合墊片朝向該晶粒之活性面之一中心線排列之晶粒。每一第二晶粒154安裝於該引線架之底面上，且其經定位以便該晶粒上之結合墊片於該間隙內；且每一第二晶粒154使用黏接劑153部分黏附於該晶粒腳座之底面上，且部分黏附於該引線之底面上。頂晶粒164藉由將頂晶粒164上之結合墊片與引線111上之結合部位相連接之焊線156而電互連；且底晶粒154藉由將底晶粒154上之結合墊片與引線111上之結合部位相連接之焊線159，且視情況藉由將底晶粒154上之結合墊片與頂晶粒164上之結合墊片相連接之焊線158而電互連。該封裝由157密封，以密封該晶粒及線迴路，留下引線111之突出部分以互連至其中使用該封裝之設備(未圖示)。
圖1E以一平面圖展示一引線架，關於圖1D中之封裝。在圖1E之引線架中，引線111排列為兩列，鄰近位於中心之晶粒腳座112之兩個相對的大體上直邊緣，該等晶粒腳座邊緣與相應列之引線之間有一間隙。
圖2A-2C說明根據本發明之一實施例之一多晶片封裝，圖2A及2C以一平面圖展示根據此實施例之一引線架，圖2A展示"頂"面及圖2C展示"底"面；且，圖2B根據此實施例，以穿過圖2A或2C之2B-2B剖面圖展示通常在202之一封裝。該引線架包括位於中心之晶粒腳座212及排列於周邊之引線。晶粒腳座212包括一邊界232，且該等引線包括內結合指狀物部分231及槽脊部分211。若干該等引線架通常以一陣列形成於一金屬(諸如銅)薄片上。在引線架之陣列上形成該等封裝，並接著藉由切割或沖孔將已完成之個別封裝獨立(分離)。如於圖2B中之241所展示，圖2A及2C中之虛線241表示用於形成已完成封裝之邊緣之分離線。一第一("頂")晶粒24安裝於晶粒腳座212之頂面之表面之晶粒附著區域上，並使用一黏接劑25黏附。在圖2A中，由畫交叉陰影線區域24表示該頂晶粒佔據面積。該頂晶粒藉由將晶粒之結合片與引線指狀物231上之結合部位相連接之焊線26而電互連。該底面之引線架中之空穴具備在該引線之結合指狀物部分231中及在該晶粒腳座212之邊界232中形成之階梯233、234。底晶粒224安裝於該等空穴中，並使用黏接劑225分別黏附於該晶粒腳座邊界與該引線之結合指狀物部分232、231中之階梯234、233上之晶粒附著區域。該底晶粒224為中心墊片晶粒；意即，該等結合墊片朝向該晶粒之活性面之一中線定位。每一底晶粒224經定位，以使其跨越晶粒腳座212之邊緣236與結合指狀物231之末端235之間的間隙237，並使該晶粒上之結合墊片在間隙237之內。在圖2C 中，由畫交叉陰影線區域214表示該底晶粒之佔據面積。底晶粒224藉由通過該晶粒上之結合墊片與該結合指狀物上之結合部位之間的間隙237的焊線226而電互連。一密封劑217覆蓋並保護該晶粒及該等焊線；在此實施例中，該引線之槽脊末端211之底面的表面之一部分251，及晶粒腳座212之底面之表面之一中間部分252，未被密封劑覆蓋而保持曝露。在圖2B中所展示之封裝為模製的(比較圖3C)。藉由接觸引線之槽脊末端之曝露部分251，例如藉由焊球與例如一母板之一印刷電路板互連，完成該封裝與於其中使用該封裝之設備之電路(未圖示)的電互連(第二層互連)。該晶粒腳座之曝露部分252可用於自該晶粒及在該封裝外傳導熱並消散熱。
根據本發明之引線架可自諸如一銅片之一引線架材料片，藉由遮罩及蝕刻，來製造。舉例而言，該等階梯可藉由自該底面對該片部分地遮罩及蝕刻來形成，且晶粒腳座及引線在平面圖中之形狀藉由對該片完全地遮罩及蝕刻來形成。根據引線架技術中之熟知之程序，可藉由控制該蝕刻來限制該等階梯之深度。在實踐中，不期望形成該等階梯之部分蝕刻(以及其他蝕刻方法)以形成精確平坦並平行或垂直之表面，如該等圖中示意性地所表示。根據本發明，該等空穴之深度，意即，該等階梯形成所達之深度，必須足以容納該底晶粒及晶粒附著黏接劑之厚度；該等空穴之寬度及長度必須足以容納該底晶粒之佔據面積。該等空穴之晶粒附著表面需要足夠平坦，以提供用於使用一晶粒附 著黏接劑安裝該晶粒及用於黏附該晶粒之一適當表面。
圖2D展示經放大之圖2B之一區段，並將其標出以指出根據本發明之一引線架之某些厚度尺寸。特定言之，展示了引線之槽脊部分211及結合指狀物部分231之一區段，連同一安裝於在引線中形成之一階梯233上並使用一黏接劑225黏附於該階梯上的第二晶粒224之一區段，及密封劑227之一區段。晶粒224之厚度為TD ，且黏接劑225之厚度為TA 。該階梯之深度必須至少與該晶粒與該黏接劑之厚度之和TD+A 一樣大，且，通常，密封劑227較佳以具有一厚度TE 之密封劑之一層覆蓋該晶粒之背面。相應地，該階梯之深度可較佳具有一等於TD+A 加TE 之一深度。該結合指狀物之梯形部分之厚度為TF ，且因此該引線架之總厚度TO 必須為至少TD+A 加TF ，且可較佳為TD+A 加TF 加TE 。
因此，在根據本發明之一特定實施例中，該階梯所需之深度將視所選擇之底晶粒之厚度與底晶粒附著黏接劑之厚度而定。不同晶粒之厚度差異很大；本發明適用之底晶粒可比較地薄，且同時可藉由背面研磨使半導體圓晶變薄，作為實際問題，最小晶粒厚度可部分地視特定晶粒類型而定。對於至少某些半導體類型而言，目前背面研磨至小於約100微米之厚度是例行程序；且當處理改良時，生產日益更薄之晶粒是可能的。又，不同晶粒附著黏接劑具有有效晶粒附著之不同厚度。通常，薄膜黏接劑可為更薄；然而，若該階梯之晶粒附著表面為顯著非平坦的，則諸如一晶粒附著糊狀環氧樹脂之糊狀黏接劑可為更適宜的。舉例而 言，一典型控制器晶粒可具有約80微米或更小之厚度，且該晶粒附著黏接劑可具有約20微米之厚度，且在該實施例中，厚度TD+A 將為約100微米或更小。根據本發明之結合指狀物厚度TF 小於約100微米，且大體上小於約75微米，較佳為約50微米或更小。
根據本發明之引線架之總厚度TO (意即，該引線架之金屬片起始材料之厚度)可大於較薄習知引線架之厚度。舉例而言，在所選擇之底晶粒具有約80微米之厚度且該晶粒附著黏接劑具有約20微米之厚度之處，該空穴之深度必須為至少約100微米(4 mil)且，在需要約50微米(2 mil)之結合指狀物厚度之處，該引線架之總厚度必須為至少約150微米(6 mil)。根據本發明，視所選擇之底晶粒及晶粒附著環氧樹脂之厚度及該等結合指狀物之特定厚度而定，並視該底晶粒之背面是否待曝露或待被密封劑之一薄層覆蓋而定，該引線架之厚度可與約300微米(12 mil)一樣大。在該底晶粒待被一密封劑薄層覆蓋之處，厚度TE 應足夠大以允許密封劑在密封過程中在該模與該底晶粒之表面中間流動；此項技術中熟知之因素中，最小化厚度TE 可達之程度尤其視該密封劑材料之流動特徵及該晶粒表面之面積而定。另一方面，目前可製造50微米薄的晶粒。
藉由實例，在根據本發明之功率放大器封裝中，例如，該頂晶粒可為一功率放大器，且該底晶粒可為功率控制器，或可具有某些其他功能(或，不同底晶粒可具有不同類型)。由於若干原因，尤其因為可藉由縮短該控制器與該功 率放大器的互連，可使該控制功能變得更快，所以在與該功率放大器晶粒相同之封裝中，期望具有控制器晶粒。因為一功率放大器通常產生一顯著量的熱量，所以根據本發明之該構型之一個優勢為該晶粒腳座的底面之表面曝露於周圍環境，並提供自該封裝消散熱量之一有效構件-藉由與一散熱片接觸(舉例而言，諸如藉由附著至諸如一母板之一印刷電路板)或藉由曝露於一通風空氣流。
根據本發明之一多晶片封裝藉由提供具有一晶粒腳座及多個引線並具有在該底面中形成之空穴的引線架來製造。該等空穴經尺寸化以容納所選擇之下晶粒之厚度及佔據面積。該引線架置於一支撐件上，且將該下晶粒安裝於其個別空穴中，並使用諸如一黏接膜或糊狀環氧樹脂之一晶粒附著黏接劑將其黏附。該黏接劑可固化，或部分固化，以在後續處理過程中保護該等空穴中之下晶粒。或，該下晶粒藉由覆晶互連，藉由凸塊或球(例如，其可為焊料凸塊或金凸塊)來安裝。接著將該引線架倒置，並將其置於一支撐件上，且將該第一上晶粒安裝於該晶粒腳座之頂表面上，並使用諸如一黏接膜或糊狀環氧樹脂之一黏接劑黏附。可將該黏接劑固化，或部分固化，並接著，視情況而定，將一第二上晶粒安裝於該第一上晶粒之上，並使用一黏接劑將其黏附。在該堆疊中之晶粒之間需要一間隔片之處，可將該間隔片堆疊於該第一晶粒之上，且可將該第二晶粒堆疊於該間隔片之上，該間隔片及該第二晶粒兩者皆使用一黏接劑黏附。以一適當之序列，使用一線結合工具，完成 焊線互連。舉例而言，較佳可為，自附著該第一上晶粒之後之下晶粒形成焊線，並在附著一隔開之第二上晶粒之前自該第一上晶粒形成焊線。一旦所有焊線已形成，即使用一之後被固化的密封材料或模製化合物密封晶粒及線。密封可經模製，以使引線之槽脊末端之頂的邊界部分保持曝露，或未模製。通常，在製造封裝之一陣列之處，接著藉由切割或沖孔，來分離該等封裝及，在該密封未制模之處，單切或單沖切割過該密封劑及該引線架。根據此項技術可推斷該程序中之其他步驟；舉例而言，清洗步驟可於不同點實行(特定言之，例如，線結合程序之前及密封之前)。
藉由圖3A中以剖面圖之實例301所展示之實施例與圖2B中所展示之實施例類似；在圖3A之實施例中，底晶粒214另外藉由通過晶粒腳座邊緣與結合指狀物之間的間隙且分別連接在底晶粒上與頂晶粒上之晶粒墊片的焊線336與頂晶粒24電互連。圖3A中之引線架之槽脊末端311展示出大於圖2B中之槽脊末端，意即，(藉由單沖或單切形成)之該等槽脊末端之邊緣341自密封劑217橫向凸出地更遠；如下面所描述之圖3D中舉例所展示，該等較大槽脊末端，例如藉由焊球，提供一個該封裝與其上堆疊之一第二封裝之間的互連。
藉由圖3B中以剖面圖中之實例302所展示之實施例亦與圖2B中所展示之實施例類似；在圖3B之實施例中，一額外頂晶粒324堆疊於第一頂晶粒24之上，並使用黏接劑325黏附。藉由連接第一頂晶粒24上之結合墊片與結合指狀物231 上之結合部位之焊線26，及藉由連接額外頂晶粒324之結合墊片與結合指狀物231上之結合部位之焊線326，完成第一頂晶粒24及額外頂晶粒324的電互連。圖3A中之引線架之槽脊末端311展示出大於圖2B中之槽脊末端，意即，(藉由單沖或單切形成)之該等槽脊末端之邊緣341自密封劑217橫向凸出地更遠；如下面所述之圖3D中舉例所展示，該等較大槽脊末端提供一個該封裝與其上堆疊之一第二封裝之間的互連。
藉由圖3C中以剖面圖之實例303所展示之實施例亦與圖2B中所展示之實施例類似；在圖3C之實施例中，藉由沖孔或切割過密封劑327及該引線架之引線末端361來分離該等經密封封裝。在此實施例中，亦提供額外焊線互連346，其通過底晶粒24上之焊線墊片與結合指狀物231上之結合部位之間的間隙。
如上所指明，任何根據本發明之各種封裝可與其他封裝(其可根據或不根據本發明製造)相堆疊以形成多封裝模組。藉由實例，圖3D展示一多封裝模組304之一實施例，其具有兩個封裝306、307，根據本發明該等封裝一個堆疊於另一個之上，並藉由焊球316互連，該焊球排列於下封裝306之引線架346之槽脊末端387之頂表面381與上封裝307之引線架347之槽脊末端377之底表面371之間。根據本發明之一多封裝模組可具有兩個以上經堆疊之封裝，該等封裝之至少一個為根據本發明之一引線架封裝。根據本發明之該多封裝模組中之封裝不需為相同的；如上所指明，根據本發 明，該多封裝中之封裝之至少一個為根據本發明之一引線架封裝。
圖3E展示本發明之另一實施例，通常於305，其中藉由覆晶互連將每一底封裝314安裝於該空穴中之晶粒附著表面上，意即藉由導電球或凸塊325，該等球或凸塊可為金凸塊或焊料凸塊。球或凸塊345用於將頂覆晶晶粒314黏附於該空穴之晶粒附著表面上，並用於提供該晶粒與該晶粒腳座邊界之間的電互連，及該晶粒與不同引線之結合指狀物231之間的電互連。藉由密封劑357加強底晶粒314之附著。舉例而言，如圖2B之實施例中，藉由單切或單沖界定引線架之邊緣371，且該引線之槽脊末端381之部分表面未被密封劑357覆蓋，而保持曝露，以與於其中使用該封裝之設備(未圖示)進行第二層互連。
如參考圖3B之實例所指明，根據本發明，可將額外晶粒堆疊於該引線架之頂面上之第一晶粒之上。亦根據本發明，可將額外晶粒安裝於該引線架之底面中之空穴中。該等選擇於圖4A-4C中說明，其說明根據本發明之另一實施例之多晶片封裝。圖4A及4C以一平面圖展示根據此實施例之一引線架，圖4A展示該"頂"面且圖4C展示該"底"面；且圖4B以穿過圖4A或4C之4B-4B之一剖面圖展示根據該實施例之一封裝，通常於402。此處，如圖2A-2C之實施例中，該引線架包括位於中心之晶粒腳座212及排列於周邊之引線。晶粒腳座212包括一邊界232，且該等引線包括內結合指狀物部分231及槽脊部分211。若干該等引線架通常 以一陣列形成於諸如銅之一金屬薄片上。該等封裝形成於引線架之陣列上，並接著已完成之個別封裝藉由切割或沖孔獨立(分離)。如圖4B中於241所展示，圖4A及4C中之虛線241表示形成已完成封裝之邊緣之分離線。一第一"上"晶粒24安裝於晶粒腳座212之頂面之表面的一晶粒附著區域上，並使用一黏接劑25黏附。在圖2A中，該第一上晶粒佔據面積由畫交叉陰影線區域24表示。一第二上晶粒424安裝於該第一頂晶粒24之上，並使用一黏接劑425黏附。第一上晶粒24藉由連接晶粒上之結合墊片與引線指狀物231上之結合部位之焊線26而電互連，且第二上晶粒424藉由連接該晶粒上之結合墊片與引線指狀物231上之結合部位之焊線426而電互連。
亦於此處，如圖2A-2C之實施例中，藉由於該等引線之結合指狀物部分231中及晶粒腳座212之邊界232中形成之階梯233、234，提供於該底面之引線架中之空穴。底晶粒214及額外底晶粒424安裝於該等空穴中，並使用黏接劑225分別黏附至晶粒腳座邊界及引線之結合指狀物部分232、231中之階梯234、233上之晶粒附著區域。底晶粒214及424為中心墊片晶粒；意即，該等結合墊片朝向該晶粒之活性面之中線定位。每一底晶粒214，224經定位，以使其跨越晶粒腳座212之邊緣236與結合指狀物231之末端235之間的間隙237，並使該晶粒上之結合墊片在間隙237之內。在圖4C中，該底晶粒之佔據面積由畫交叉陰影線區域214及414表示。底晶粒214及424藉由焊線226電互連，該焊線通過該 晶粒上之結合墊片與該結合指狀物上之結合部位之間的間隙237。一密封劑427覆蓋並保護該晶粒及該等焊線；在此實施例中，引線之槽脊末端211之底面的表面之一部分251，及晶粒腳座212之底面之表面的一中間部分252，未被密封劑覆蓋，而保持曝露。在圖4B中所展示之封裝為模製的(比較圖3C)。藉由與引線之槽脊末端之曝露部分251接觸，例如藉由與例如一母板之一印刷電路板之焊球互連，完成該封裝與於其中使用該封裝之設備之電路(未圖示)的電互連(第二層互連)。該晶粒腳座之曝露部分252可用於自該晶粒及在該封裝外傳導熱並消散熱。
在圖2A及2C及圖4A及4C之實施例中，該等空穴是連續的且，在該等實施例之每一個中，個別底晶粒可安裝於相同連續晶粒空穴之不同區域中。意即，該晶粒腳座中之階梯連續地向該晶粒腳座之邊界周圍延伸；且相反階梯(跨越該間隙)形成於所有引線指狀物中。其他變化為可能的；每一空穴需要足夠大以容納所選擇待安裝於其中之晶粒的佔據面積(長度及寬度)。在如圖2A、2C中之一實施例中，例如，由於具有沿該腳座之相對邊緣的間隙上排列之兩個底晶粒，所以該腳座邊界及該等引線中之階梯不需擴展至另兩個邊緣，亦不需擴展至該引線架之角中。
將本文中所參考之所有專利及專利公開案以參考之方式併入。
其他實施例係在本發明之範疇內。
11‧‧‧引線
12‧‧‧晶粒腳座
13‧‧‧內切口
14‧‧‧晶粒
15‧‧‧晶粒附著黏接劑
16‧‧‧焊線
17‧‧‧密封劑
18‧‧‧間隔片
24‧‧‧第一頂晶粒
25‧‧‧黏接劑
26‧‧‧焊線
111‧‧‧引線
112‧‧‧晶粒墊片
124‧‧‧第二晶粒
125‧‧‧黏接劑
126‧‧‧焊線
134‧‧‧第二晶粒
135‧‧‧黏接劑
145‧‧‧黏接劑
153‧‧‧黏接劑
154‧‧‧第二晶粒
155‧‧‧黏接劑
156‧‧‧焊線
157‧‧‧密封劑
158‧‧‧焊線
159‧‧‧焊線
164‧‧‧第二晶粒
202‧‧‧封裝
211‧‧‧槽脊末端
212‧‧‧晶粒腳座
214‧‧‧底晶粒
217‧‧‧密封劑
224‧‧‧底晶粒
225‧‧‧黏接劑
226‧‧‧焊線
227‧‧‧密封劑
231‧‧‧結合指狀物
232‧‧‧邊界
233‧‧‧階梯
234‧‧‧階梯
235‧‧‧結合指狀物之末端
236‧‧‧腳座之邊緣
237‧‧‧間隙
241‧‧‧分離線(虛線)
251‧‧‧脊面末端之曝露部分
252‧‧‧晶粒腳座之曝露部分
301‧‧‧實例
302‧‧‧實例
303‧‧‧實例
304‧‧‧實例
305‧‧‧實例
306‧‧‧低封裝
307‧‧‧高封裝
311‧‧‧槽脊末端
314‧‧‧底覆晶晶粒
316‧‧‧焊線
324‧‧‧額外頂晶粒
325‧‧‧黏接劑
326‧‧‧焊線
327‧‧‧密封劑
336‧‧‧焊線
341‧‧‧邊線
345‧‧‧球或凸塊
346‧‧‧額外焊線互連
347‧‧‧引線架
357‧‧‧密封劑
361‧‧‧引線末端
371‧‧‧邊緣
377‧‧‧槽脊末端
381‧‧‧槽脊末端
387‧‧‧槽脊末端
402‧‧‧封裝
424‧‧‧額外底晶粒
425‧‧‧黏接劑
426‧‧‧焊線
427‧‧‧密封劑
圖1A-1C為示意草圖，其以剖視圖展示習知之半導體引線架封裝。
圖1D為一示意草圖，其以剖視圖展示一具有安裝於引線架之頂面及底面之晶粒的習知半導體封裝。
圖1E為一示意草圖，其以一平面圖展示圖1D之封裝中之一引線架。
圖2A與2C為示意草圖，其以一平面圖展示根據本發明之一實施例之一引線架；圖2A為自該引線架之一第一("頂")面觀察，圖2C為自該引線架之一第二("底")面觀察。
圖2B為一示意草圖，其以穿過2B-2B之一剖視圖展示根據本發明之一實施例之一多晶片引線架封裝，該封裝具有圖2A與2C中舉例所展示之引線架。
圖2D為一示意草圖，其展示圖2B之引線架封裝之一區段。
圖3A為一示意草圖，其以剖面圖展示根據本發明之一態樣之一多晶片引線架封裝。
圖3B為一示意草圖，其以剖面圖展示根據本發明之另一態樣之一多晶片引線架封裝，該封裝具有堆疊於該引線架之第一("頂")面上之晶粒。
圖3C為一示意草圖，其以剖面圖展示根據本發明之另一態樣之一多晶片引線架封裝。
圖3D為一示意草圖，其以一剖面圖展示具有根據本發明之經堆疊之多晶片引線架封裝的一多封裝模組。
圖3E為一示意草圖，其以一剖面圖展示根據本發明之另一態樣之一多晶片引線架封裝，該封裝具有覆晶下晶粒。
圖4A及4C為示意草圖，其以一平面圖展示根據本發明之一實施例之一引線架；圖4A為自該引線架之一第一("頂")面觀察，且圖4C為自該引線架之一第二("底")面觀察。
圖4B為一示意草圖，其以穿過4B-4B之一剖面圖展示根據本發明之一實施例之多晶片引線架封裝，該封裝具有圖4A及4C中舉例所展示之一引線架。
24‧‧‧第一頂晶粒
25‧‧‧黏接劑
26‧‧‧焊線
202‧‧‧一封裝之處
211‧‧‧槽脊末端
212‧‧‧晶粒腳座
217‧‧‧密封劑
224‧‧‧底晶粒
225‧‧‧黏接劑
226‧‧‧焊線
231‧‧‧結合指狀物
232‧‧‧邊界
233‧‧‧梯階
234‧‧‧梯階
235‧‧‧結合指狀物之末端
236‧‧‧腳座之邊緣
237‧‧‧間隙
241‧‧‧分離線(虛線)
251‧‧‧脊面末端之曝露部分
252‧‧‧晶粒腳座之曝露部分

Claims (22)

  1. 一種引線架，其具有一第一面及一第二面，該引線架包含一晶粒腳座及多個引線，每一引線包含一外槽脊部分(outer land portion)及一內結合指狀物部分(bond finger portion)，該晶粒腳座具有一邊界及一邊緣，在該晶粒腳座邊緣與該等引線之該等結合指狀物部分的內末端之間有一間隙，該晶粒腳座之該第一面之一表面包括一第一面晶粒附著區域，且進一步包含在該引線架之該第二面中的至少一空穴，每一空穴具有一深度且至少一晶粒安裝表面跨越該間隙，該晶粒安裝表面經尺寸化以容納一所選擇之第二面晶粒之佔據面積，且該深度經尺寸化為至少與該所選擇之第二面晶粒之厚度加上所選擇之第二面晶粒安裝構件之厚度一樣大。
  2. 如請求項1之引線架，其於該引線架之該第二面中包含至少兩個該等空穴。
  3. 如請求項1之引線架，其於該引線架之該第二面中包含四個該等空穴。
  4. 如請求項1之引線架，其包含跨越該間隙之至少兩個該等晶粒安裝表面。
  5. 如請求項1之引線架，其包含跨越該間隙之四個該等晶粒安裝表面。
  6. 一種引線架，其具有一第一面及一第二面，該引線架包含一晶粒腳座及多個引線，每一引線包含一外槽脊部分及一內結合指狀物部分，該晶粒腳座具有一邊界及一邊 緣，在該晶粒腳座邊緣與該等引線之該等結合指狀物部分的內末端之間有一間隙，該晶粒腳座之該第一面之一表面包括一第一面晶粒附著區域，且進一步包含在該引線架之該第二面中的至少一空穴，每一空穴跨越該間隙，並包含在該晶粒腳座邊界之該第二面之一部分中的一階梯(step)，及在至少一引線之該結合指狀物部分之該第二面的一部分中的一階梯，該等階梯包含該空穴的一晶粒安裝表面，其包含經尺寸化以容納一所選擇之第二面晶粒之佔據面積的一晶粒附著表面，且該深度經尺寸化為至少與該所選擇之第二面晶粒之厚度加上所選擇之第二面晶粒安裝構件之厚度一樣大。
  7. 一種引線架，其具有一第一面及一第二面，該引線架包含一晶粒腳座及多個引線，每一引線包含一外槽脊部分及一內結合指狀物部分，該晶粒腳座具有一邊界及一邊緣，在該晶粒腳座邊緣與該等引線之該等結合指狀物部分的內末端之間有一間隙，該晶粒腳座之該第一面之一表面包括一第一面晶粒附著區域，且進一步包含在該晶粒腳座邊界之該第二面之一部分中的一階梯，及在至少一引線之該結合指狀物部分之該第二面之一部分中的一階梯，在該晶粒腳座邊界之至少一部分之該第二面中的該等階梯連同在至少一引線之結合指狀物部分的至少一部分之該第二面中的一階梯形成一跨越該間隙的空穴，該等階梯具有大體上共平面之第二晶粒附著表面，其在一大體上平行於該引線架之該第二面之一表面的平面 中，該空穴經尺寸化以容納一第二晶粒之佔據面積，該空穴具有至少與該第二晶粒之厚度加上第二晶粒附著構件之厚度一樣大之一深度。
  8. 一種多晶片引線架半導體封裝，其包含如請求項1之引線架、黏附於該第一面晶粒附著區域之一第一晶粒及黏附於一該空穴之一晶粒安裝表面之一第二晶粒。
  9. 如請求項8之封裝，其中該第一晶粒經定向，以使該第一晶粒之該活性表面朝向遠離該第一面晶粒附著區域。
  10. 如請求項9之封裝，其中該第一晶粒藉由焊線與該引線架電互連。
  11. 如請求項8之封裝，其中該第二晶粒經定向，以使該第二晶粒之該活性表面朝向該空穴之該晶粒安裝表面。
  12. 如請求項11之封裝，其中該第二晶粒藉由焊線與該引線架電互連。
  13. 如請求項11之封裝，其中該第二晶粒經定位，以使該等晶粒墊片位於該間隙之下，且該等焊線通過該間隙。
  14. 如請求項11之封裝，其中該第二晶粒藉由覆晶互連與該引線架電互連。
  15. 如請求項8之封裝，其進一步包含堆疊於該第一晶粒上之一額外晶粒。
  16. 如請求項8之封裝，其進一步包含覆蓋該晶粒及該等互連之一密封劑。
  17. 如請求項16之封裝，其中該引線架之該第二面之一表面未由該密封劑覆蓋。
  18. 如請求項16之封裝，其中該晶粒腳座之該第二面上之槽脊(lands)的一表面未由該密封劑覆蓋。
  19. 一種多封裝模組，其包含如請求項8之至少一第一多晶片引線架半導體封裝，其經堆疊有至少一第二封裝，該等封裝具有在該第一多晶片引線架半導體封裝上之第二層互連部位與該第二封裝上之第二層互連部位之間的電互連。
  20. 如請求項19之多封裝模組，其中該等電互連包含焊線。
  21. 如請求項19之多封裝模組，其中該等電互連包含焊球。
  22. 如請求項19之多封裝模組，其中該至少一第二封裝為如請求項8之一第二多晶片引線架半導體封裝。
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