JP4860442B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4860442B2 JP4860442B2 JP2006313011A JP2006313011A JP4860442B2 JP 4860442 B2 JP4860442 B2 JP 4860442B2 JP 2006313011 A JP2006313011 A JP 2006313011A JP 2006313011 A JP2006313011 A JP 2006313011A JP 4860442 B2 JP4860442 B2 JP 4860442B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor
- die bonding
- bonding pad
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
10,20 メインリード
11,21 ダイボンディングパッド
11a,21a 裏面
12,22 端子部
23 傾斜部
31A,32A リード群
31,32 リード
31a,32a 端子部
31b,32b 傾斜部
31c,32c ワイヤボンディングパッド
41,42 半導体素子
51,52 ワイヤ群
60 樹脂パッケージ
Claims (1)
- 複数の半導体素子と、
表面に上記半導体素子がボンディングされた複数のダイボンディングパッドと、
上記半導体素子を覆う樹脂パッケージと、
を備えた半導体装置であって、
上記複数の半導体素子は、第1の半導体素子と第2の半導体素子とを含んでおり、
上記複数のダイボンディングパッドは、上記第1の半導体素子がボンディングされた第1のダイボンディングパッドと、上記第2の半導体素子がボンディングされた第2のダイボンディングパッドとを含んでおり、
上記第1のダイボンディングパッドと上記第2のダイボンディングパッドとは、上記第1の半導体素子と上記第2の半導体素子とが正対する配置とされており、かつそれぞれの裏面の少なくとも一部ずつが上記樹脂パッケージから露出しており、
上記第1の半導体素子に対して第1のワイヤ群を介して導通する第1のリード群と、上記第2の半導体素子に対して第2のワイヤ群を介して導通する第2のリード群と、を備えており、
上記第1のリード群と上記第2のリード群とは、上記第1および第2の半導体素子が正対する方向と直角である方向において反対の方向に向かって上記樹脂パッケージから延出しており、
上記第1のワイヤ群と上記第2のワイヤ群とは、上記第1および第2の半導体素子が正対する方向と直角である方向において互いに重ならない配置とされていることを特徴とする、半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006313011A JP4860442B2 (ja) | 2006-11-20 | 2006-11-20 | 半導体装置 |
EP07120552A EP1923916A2 (en) | 2006-11-20 | 2007-11-13 | Semiconductor device |
TW096143455A TW200834872A (en) | 2006-11-20 | 2007-11-16 | Semiconductor device |
CNA2007101667900A CN101188227A (zh) | 2006-11-20 | 2007-11-19 | 半导体装置 |
US11/985,936 US20080116590A1 (en) | 2006-11-20 | 2007-11-19 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006313011A JP4860442B2 (ja) | 2006-11-20 | 2006-11-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008130750A JP2008130750A (ja) | 2008-06-05 |
JP4860442B2 true JP4860442B2 (ja) | 2012-01-25 |
Family
ID=39086121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006313011A Expired - Fee Related JP4860442B2 (ja) | 2006-11-20 | 2006-11-20 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20080116590A1 (ja) |
EP (1) | EP1923916A2 (ja) |
JP (1) | JP4860442B2 (ja) |
CN (1) | CN101188227A (ja) |
TW (1) | TW200834872A (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009283656A (ja) * | 2008-05-22 | 2009-12-03 | Denso Corp | 半導体装置およびその製造方法 |
JP2010109255A (ja) * | 2008-10-31 | 2010-05-13 | Sanyo Electric Co Ltd | 半導体装置 |
JP5813963B2 (ja) | 2011-02-28 | 2015-11-17 | ローム株式会社 | 半導体装置、および、半導体装置の実装構造 |
US9997437B2 (en) | 2015-04-28 | 2018-06-12 | Shindengen Electric Manufacturing Co., Ltd. | Power semiconductor module for improved thermal performance |
JP6162764B2 (ja) * | 2015-09-17 | 2017-07-12 | ローム株式会社 | 半導体装置、および、半導体装置の実装構造 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0778596B2 (ja) * | 1988-08-19 | 1995-08-23 | 富士写真フイルム株式会社 | ハロゲン化銀写真乳剤の製造方法 |
JP2960283B2 (ja) * | 1993-06-14 | 1999-10-06 | 株式会社東芝 | 樹脂封止型半導体装置の製造方法と、この製造方法に用いられる複数の半導体素子を載置するためのリードフレームと、この製造方法によって製造される樹脂封止型半導体装置 |
JP3023303B2 (ja) * | 1996-01-16 | 2000-03-21 | 松下電子工業株式会社 | 半導体装置の成形方法 |
JPH1168034A (ja) * | 1997-08-25 | 1999-03-09 | Sanyo Electric Co Ltd | 半導体装置 |
US6541856B2 (en) * | 2001-06-06 | 2003-04-01 | Micron Technology, Inc. | Thermally enhanced high density semiconductor package |
US7208821B2 (en) * | 2004-10-18 | 2007-04-24 | Chippac, Inc. | Multichip leadframe package |
-
2006
- 2006-11-20 JP JP2006313011A patent/JP4860442B2/ja not_active Expired - Fee Related
-
2007
- 2007-11-13 EP EP07120552A patent/EP1923916A2/en not_active Withdrawn
- 2007-11-16 TW TW096143455A patent/TW200834872A/zh unknown
- 2007-11-19 US US11/985,936 patent/US20080116590A1/en not_active Abandoned
- 2007-11-19 CN CNA2007101667900A patent/CN101188227A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
TW200834872A (en) | 2008-08-16 |
JP2008130750A (ja) | 2008-06-05 |
CN101188227A (zh) | 2008-05-28 |
EP1923916A2 (en) | 2008-05-21 |
US20080116590A1 (en) | 2008-05-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5232367B2 (ja) | 半導体装置 | |
JP5528900B2 (ja) | 発光素子モジュール | |
JP6065979B2 (ja) | 半導体装置 | |
JP5098301B2 (ja) | 電力用半導体装置 | |
WO2014034411A1 (ja) | 電力用半導体装置 | |
KR102511000B1 (ko) | 반도체 패키지용 클립 구조체 및 이를 포함하는 반도체 패키지 | |
JP4860442B2 (ja) | 半導体装置 | |
JPWO2021002132A1 (ja) | 半導体モジュールの回路構造 | |
JP2007027404A (ja) | 半導体装置 | |
JP6909630B2 (ja) | 半導体装置 | |
JP2006310609A (ja) | 半導体装置 | |
JP5273265B2 (ja) | 電力用半導体装置 | |
JP5693395B2 (ja) | 半導体装置 | |
JP5601282B2 (ja) | 半導体装置 | |
JP2006294729A (ja) | 半導体装置 | |
JP7050487B2 (ja) | 電子デバイス | |
JP2008177424A (ja) | 半導体装置 | |
JP2015037151A (ja) | 半導体装置 | |
WO2015107997A1 (ja) | モジュール基板 | |
JP5180495B2 (ja) | 半導体装置およびその製造方法 | |
WO2013065647A1 (ja) | 半導体装置 | |
JP4994883B2 (ja) | 樹脂封止型半導体装置 | |
CN111602240B (zh) | 树脂封装型半导体装置 | |
JP6416055B2 (ja) | 半導体装置 | |
JP5819469B2 (ja) | 発光素子モジュール |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20091112 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110811 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110817 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111017 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111101 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111102 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4860442 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141111 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |