TWI556367B - 一種積體電路結構與其製造方法 - Google Patents

一種積體電路結構與其製造方法 Download PDF

Info

Publication number
TWI556367B
TWI556367B TW103145301A TW103145301A TWI556367B TW I556367 B TWI556367 B TW I556367B TW 103145301 A TW103145301 A TW 103145301A TW 103145301 A TW103145301 A TW 103145301A TW I556367 B TWI556367 B TW I556367B
Authority
TW
Taiwan
Prior art keywords
molding compound
wafer
layer
electrical connection
passivation
Prior art date
Application number
TW103145301A
Other languages
English (en)
Other versions
TW201532207A (zh
Inventor
林俊宏
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201532207A publication Critical patent/TW201532207A/zh
Application granted granted Critical
Publication of TWI556367B publication Critical patent/TWI556367B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14179—Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10271—Silicon-germanium [SiGe]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

一種積體電路結構與其製造方法
本發明是有關於一種積體電路結構與其製造方法。
於晶圓級的晶片尺寸封裝件(wafer-level chip scale packages；WLCSP)中，積體電路裝置如電晶體為先形成於晶圓中的半導體基板之表面。互連結構接著形成於積體電路裝置上。金屬墊形成於互連結構上，並與之電性連接。鈍化層與第一聚醯亞胺(polyimide)層形成於金屬墊之上，且金屬墊透過鈍化層與第一聚醯亞胺層中的開口暴露出來。
接著形成後鈍化互連層(post-passivation interconnect；PPI)以及接續形成第二聚醯亞胺層於鈍化互連層上。焊球下層金屬(under-bump metallurgy；UBM)形成並延伸至第二聚醯亞胺層的開口內，其中焊球下層金屬電性連接至鈍化互連層。焊球接著設置於焊球下層金屬上，並進行重熔。
接著提供模塑化合物以保護焊球。於模塑化合物的提供過程中，先提供液態的模塑化合物，接續再對液態的模塑化合物上的脫模薄膜施壓，以將多餘的液態的模塑化合物擠 出。因此，焊球的頂部將會穿過液態的模塑化合物而暴露出來。接著液態的模塑化合物被固化。當液態的模塑化合物被固化成固態後，移除脫模薄膜。晶圓接著再被切成多個晶片。
根據本揭露之部分的實施方式，晶片包含半導體基板、設置於半導體基板之上的電性連接元件以及成形於電性連接元件之底部的模塑化合物。模塑化合物之上表面低於電性連接元件之上端。凹槽自模塑化合物之上表面朝向模塑化合物內延伸。
根據本揭露之替代的實施方式，積體電路結構包含基板、位於基板之上的金屬墊、一部分位於金屬墊之上的鈍化層、位於鈍化層之上的高分子層與後鈍化互連層。後鈍化互連層包含位於高分子層之上的第一部分以及延伸至高分子層內的第二部分。後鈍化互連層與該金屬墊電性連接。焊接區位於後鈍化互連層之上，並與後鈍化互連層電性連接。模塑化合物位於後鈍化互連層之上。模塑化合物包圍並以物理接觸於焊接區之底部部分。焊接區的上部部分自模塑化合物向外突出。凹槽自模塑化合物之上表面朝模塑化合物內延伸，其中凹槽之底部高於模塑化合物之下表面。
根據本揭露之其他替代的實施方式，方法包含分配模塑化合物於電性連接元件之上，其中電性連接元件位於晶圓的基板之上。方法更包含提供脫模薄膜於模塑化合物之上，並朝電性連接元件對脫模薄膜施壓，其中電性連接元件之頂部 被壓入至脫模薄膜內。於脫模薄膜朝該模塑化合物進行施壓時，固化模塑化合物。自模塑化合物移除脫模薄膜。於模塑化合物中形成凹槽。
10‧‧‧晶片
20‧‧‧基板
22‧‧‧互連結構
24‧‧‧主動元件
25‧‧‧低介電常數材料層
26‧‧‧金屬線與通孔
28‧‧‧金屬墊
30‧‧‧鈍化層
32、40‧‧‧高分子層
38‧‧‧後鈍化互連層
42‧‧‧焊球下層金屬
44、202‧‧‧電性連接元件
46、60‧‧‧模塑化合物
46A‧‧‧上表面
48‧‧‧脫模薄膜
50‧‧‧箭頭
52、52A、52B、52C‧‧‧凹槽
53‧‧‧虛線
54‧‧‧刀片/鑽頭
56‧‧‧分隔線
57‧‧‧模具
57A‧‧‧針腳
58‧‧‧底膠
60A‧‧‧輪狀部
62‧‧‧金屬柱
100‧‧‧晶圓
D1‧‧‧深度
R1‧‧‧半徑
R2‧‧‧橫向尺寸
S1、S2‧‧‧間隙
T1‧‧‧厚度
W1‧‧‧寬度
W2‧‧‧寬度
細讀以下詳細敘述並搭配對應之圖式，可了解到本揭露之多個態樣。須注意的是，圖式中的多個特徵並未依照該業界領域之標準作法繪製實際比例。事實上，為了討論的清楚，所述之特徵的尺寸可以任意的增加或減少。
第1A圖、第1B圖以及第2圖至第6圖繪示依照部分實施方式的晶片之形成方式中的中介階段的側視剖面圖與上視圖。
第7圖繪示依照部分實施方式的將晶片貼合至封裝元件的側視剖面圖。
第8圖繪示依照部分實施方式的扇出型封裝件的側視剖面圖。
本揭露將提供許多個實施方式或實施方法以實現本揭露之多個不同的特徵。許多元件與排列將以特定實施方法在以下敘述以簡化本揭露。當然，這些敘述僅止於範例，且不應用以限制本揭露。舉例而言，敘述「第一特徵形成於第二特徵上」包含多種實施方式，其中涵蓋第一特徵與第二特徵直接接觸，以及額外的特徵形成於第一特徵與第二特徵之間而使兩者不直接接觸。此外，本揭露在多個範例中會重複參考號碼與 字母。這樣的重複方式是為了簡單與明瞭的目的而其本身並不會決定多個範例以及/或所討論的配置之間的關係。
此外，方位相對詞彙，如「在...之下」、「下面」、「下」、「上方」或「上」或類似詞彙，在本文中為用來便於描述繪示於圖式中的一個元件或特徵至另外的元件或特徵之關係。方位相對詞彙除了用來描述裝置在圖式中的方位外，其包含裝置於使用或操作下之不同的方位。當裝置被另外設置(旋轉90度或者其他面向的方位)，本文所用的方位相對詞彙同樣可以相應地進行解釋。
具有降低應力之結構的封裝件與其形成方法將根據多個示範的實施方式揭露。形成封裝件的中介階段也以圖式繪示方式表示之。實施方式的變型也會進行討論。在各個視圖和說明的實施方式中，相同的參考標號用於標示相同的元件。
第1A圖繪示依照一實施方式的晶圓100的側視剖面圖。晶圓100包含多個晶片10於其中，並以分隔線56將多個晶片10彼此互相分離。晶圓100(以及每一個晶片10)包含基板20，基板20可以是半導體基板，例如矽基板。半導體基板20也可以由其他半導體材料形成，例如矽化鍺、矽化碳、III-V族化合物半導體或類似物。主動元件24，例如電晶體，形成於基板20之表面。互連結構22形成於基板20之上。互連結構22包含金屬線與通孔26，金屬線與通孔26形成於互連結構22之中並與主動元件24電性連接。金屬線與通孔26形成於低介電常數材料層25，其可以是極端低的(或特別低的)介電常數材 料層，即low-K材料或ELK(extreme low-k)材料，其所具有的介電常數為小於2.5或大致小於2.0。
金屬墊28形成於互連結構22之上。金屬墊28可以包含鋁、銅、鋁銅合金、銀、金、鎳、鎢、其組合之合金以及/或由其組合的多層結構。可以理解到，雖然每一個晶片10為繪示一個金屬墊28，然而多個金屬墊28也可以存在於同一個晶片10之中。金屬墊28可以電性連接至主動元件24，舉例而言，以穿過互連結構22之底層的方式連接。鈍化層30與高分子層32覆蓋金屬墊28的邊緣部份。於部分示範的實施方式中，鈍化層30由介電材料形成，例如氧化矽、氮化矽或是由其組成的多層結構。開口形成於鈍化層30與高分子層32之中，以暴露金屬墊28。
高分子層32位於鈍化層30之上，其中高分子層32延伸至鈍化層30的開口內。於部分實施方式中，高分子層32可以包含光感材料。舉例而言，高分子層32包含聚酰亞胺(polyimide)、聚苯並噁唑(polybenzoxazole；PBO)與類似物，然而並不以此為限。高分子層32也可以透過進行圖案化以形成額外的開口，使得金屬墊28被暴露出來。
形成後鈍化互連層38(post-passivation interconnect；PPI)，其中每一後鈍化互連層38包含第一部分與第二部分，第一部分位於高分子層32之上，第二部分延伸至鈍化層30與高分子層32的開口內。後鈍化互連層38的第二部分電性連接至對應的金屬墊28，其也可以是透過接觸的方式連接。
高分子層40更形成於後鈍化互連層38之上。高分子層40可以透過選擇與高分子層32之相同的預定材料形成。焊球下層金屬42(under-bump metallurgy；UBM)之形成為延伸至高分子層40的開口內。焊球下層金屬42電性連接至後鈍化互連層38，且可以與後鈍化互連層38中的後鈍化互連層墊片接觸，其中後鈍化互連層墊片為組成後鈍化互連層38且比其他部分寬之部分。電性連接元件44形成於焊球下層金屬42之上。縱使圖式中只繪示一個電性連接元件44，然而每一個晶片10可以包含多個電性連接元件44。於部分實施方式中，電性連接元件44為焊球，其形成於以及/或置放於焊球下層金屬42上並進行重熔。於替代的實施方式中，電性連接元件44包含非焊料金屬柱，其中銲接層也可以形成於非焊料金屬柱的上表面之上。
第1B圖為繪示晶片10的其中之一的上視範例圖。多個電性連接元件44分布於晶片10的表面各處。於部分實施方式中，電性連接元件44為不均勻分布，且電性連接元件44之間的間隙也為不均勻。舉例而言，相鄰的電性連接元件44之間的間隙包含間隙S1與S2，其中間隙S1大於間隙S2。於替代的實施方式中，電性連接元件44為均勻分布並形成陣列。
接著，如第2圖所示，液態的模塑化合物46被分配於晶圓100之上，其中電性連接元件44沉浸於液態的模塑化合物46之下。液態的模塑化合物46的命名歸因於其為低黏滯力。另一可替換方案中，電性連接元件44的頂部為位於液態的模塑化合物46之上表面之上。
請參照第3圖，脫模薄膜48被提供於液態的模塑化合物46之上。雖然第2圖與第3圖繪示脫模薄膜48是提供於分配液態的模塑化合物46之後，然而，於替代的實施方式中，脫模薄膜48為先提供(亦即，使脫模薄膜48與晶圓100先置於模具中)，而液態的模塑化合物為注入至由脫模薄膜48所定義的空間內。
施加如箭頭50所示之壓力。脫模薄膜48透過軟質材料形成，以致於電性連接元件44的頂部被壓入至脫模薄膜48內。此外，脫模薄膜48使液態的模塑化合物46之過量部分自晶圓100的上表面流出，且脫模薄膜48的下表面低於電性連接元件44的頂端。
隨著脫模薄膜48維持被推向電性連接元件44與液態的模塑化合物46，固化步驟將會進行，以使得液態的模塑化合物46固化與凝固。於模塑化合物46之固化步驟之後，電性連接元件44的頂端為高於模塑化合物46的上表面。
接著脫模薄膜48自呈固化形態的模塑化合物46脫離。所成之結構如第4圖所示。將殘留於電性連接元件44之上表面的模塑化合物蝕刻。於所成之結構中，部分的電性連接元件44埋入於所形成之模塑化合物46之中。電性連接元件44的頂端為高於模塑化合物46的上表面。
第5A圖繪示凹槽52於模塑化合物46中形成的側視剖面圖。根據部分實施方式，凹槽52自模塑化合物46的上表面46A延伸至其中介高度內。於替代的實施方式中，凹槽52貫穿模塑化合物46以與底層的高分子層40接觸。虛線53繪示 對應的凹槽52的側壁之底部。凹槽52的深度D1可以大致大於模塑化合物46的厚度T1的百分之五十。深度D1也可以介於模塑化合物46的厚度T1的百分之五十至百分之八十之間。模塑化合物46具有內應力。舉例而言，模塑化合物46於固化時收縮，從而因此承受內應力。受應力之模塑化合物46會施予張力至底層的低介電常數材料層25。凹槽52具有降低/釋放模塑化合物46的內應力之功效，也因此模塑化合物46施予至底層的低介電常數材料層25之應力也降低。此應力釋放之效果與D1與T1之比值有關，當為高比值時，凹槽52具有更有效的應力釋放效果。因此，D1與T1之比值較佳為高於0.5。當深度D1為小於厚度T1，例如比率為百分之八十，凹槽52的應力釋放效果可以使層狀結構留下(以足夠的餘量)，以致於後鈍化互連層38(當高分子層40未被提供時)與高分子層40可以受到模塑化合物46的防護。
如第5A圖所示，凹槽52包含內部型的凹槽52A與52B(也繪於第6圖)，其位於晶片10之內並彼此被各自的晶片10之邊緣隔開。凹槽52更包含邊緣型的凹槽52C，其位於晶片10之邊界。邊緣型的凹槽52C可以與晶圓100之分隔線56重疊。
於部分實施方式中，如第5A圖所示，凹槽52透過雷射切割形成，其中雷射是用以燒毀部分模塑化合物46。於替代的實施方式中，凹槽52為透過刀片/鑽頭54以對模塑化合物46裁切或鑽孔。亦即，凹槽52之側壁形狀是由刀片或是鑽頭定義。舉例而言，凹槽52可以於部分實施方式中具有V形底 部，並連接至垂直的側壁，或是，凹槽52可以具有實質上為平坦之底部，如同第5A圖所繪。凹槽52之側壁也可以是垂直的，或當使用錐形刀片/鑽頭54時，其也可以是傾斜的。
於替代的實施方式中，如第5B圖所示，凹槽52為透過模製形成。於此實施方式中，於模塑化合物46上的脫模薄膜48(請見第3圖)被施壓之期間，部分之模塑化合物46被固化。亦即，當脫模薄膜48被移除時，模塑化合物46雖不再具有流動性，然而其為尚未完全硬化並維持其軟質性質。接著，如第5B圖所示，對模具57朝向模塑化合物46施壓。模具57的針腳57A插入至模塑化合物46內。針腳57A的位置與尺寸設計成同於凹槽52之預計位置與形狀。隨著模具57對模塑化合物46施壓，固化過程仍持續，使模塑化合物46更進一步被固化。於部分實施方式中，模具57移除於模塑化合物46完全固化之後。當模具57移除之後，晶圓100中所成之凹槽具有如第5A圖所示之形狀。
於此實施方式中，憑藉著針腳57A之形狀，凹槽52(請見第5A圖)可以具有垂直的側壁並垂直於模塑化合物46的上表面，或是，凹槽52可以具有傾斜的側壁，即凹槽52之底部較凹槽52所對應之頂部窄。凹槽52也可以具有實質上為平坦的底面或是傾斜的底面。
於形成凹槽52之後，晶圓100於晶圓切塊步驟中被切成塊，也因此使晶片10彼此互相被隔開。第6圖繪示晶片10的上視範例圖。於範例晶片10的上視圖中，凹槽52包含任意組合的凹槽52A、52B與52C。應可理解到，晶片10可以包 含一種、兩種或是全部三種類型之任意組合的凹槽52A、52B與52C。凹槽52A可以具有圓形的上視形狀，其可以透過使用鑽頭、雷射或是類似物形成。凹槽52A之半徑R1可以大致介於電性連接元件44的橫向尺寸R2之百分之五十至百分之一百五十之間。於部分實施方式中，凹槽52A與電性連接元件44之組合形成陣列。替代狀態中，此陣列可以具有電性連接元件44，而凹槽52A形成於設置電性連接元件44之前。
凹槽52B於晶片10之上視圖中具有拉長的形狀。舉例而言，凹槽52B具有矩形的上視圖。凹槽52B可以透過刀片、雷射或是類似物形成。凹槽52B同樣可以形成於設置電性連接元件44之前。凹槽52B之長度由可用的空間決定。於部分實施方式中，凹槽52B所具有之長度L1大致大於電性連接元件44的橫向尺寸R2的百分之兩百。凹槽52B之寬度W1可以大致介於電性連接元件44的橫向尺寸R2之百分之五十至百分之一百五十之間。
凹槽52C為位於晶片10之邊緣的邊緣型的凹槽。凹槽52C之寬度W2可以大致介於電性連接元件44的橫向尺寸R2之百分之五十至百分之一百五十之間，而縱使較大或是較小的值也可使用。於部分實施方式中，如第6圖所示，凹槽52C形成於晶片10的全部邊緣之上。於替代的實施方式中，凹槽52C形成於晶片10的部分(例如一個、兩個或三個)邊緣之上，亦即非全部。這部分的實施方式可以使用於當電性連接元件44接近晶片10之部分邊緣之時，即此部份之邊緣並未具有足夠的空間以設置邊緣型的凹槽52C。第7圖包含晶片10的側視剖面 圖，如第7圖中的晶片10的側視剖面圖所示，邊緣型的凹槽52將導致形成若干階梯於晶片10之邊緣，其中每一個階梯包含兩個模塑化合物46的上表面，其透過對應的凹槽52C之側壁連接。
請再看到第6圖，模塑化合物46會因收縮而導致模塑化合物46有應力產生。應力的主要組成為位於平行模塑化合物46之上表面的方向。內部型的凹槽52A與52B中斷應力的路徑，也因此降低了應力。於晶片10之角落與邊緣有較大的應力，且此較大的應力可能導致模塑化合物46有碎裂產生。藉由形成邊緣型的凹槽52C，模塑化合物46具有較大應力的部分會被移除，也因此模塑化合物46之邊緣部分的碎裂會減少。
第7圖繪示晶片10貼合至其他封裝元件200，例如封裝件基板、載板或是印刷電路板。電性連接元件44貼合至封裝元件200的電性連接元件202，其中電性連接元件202可以是金屬墊、金屬柱或是類似物。於部分實施方式中，晶片10與封裝元件200之間的間隙填充有底膠58。因此凹槽52也被填充有底膠58。於替代的實施方式中，沒有底膠設置於晶片10與封裝元件200之間的間隙內。因此，凹槽52為維持氣體間隙。
第8圖繪示依照替代實施方式中的扇出型封裝件，其中後鈍化互連層38延伸至晶片10的邊緣外的區域之內。於此部分的實施方式中，模塑化合物60用以包覆晶片10於其中。模塑化合物60可以包含輪狀部60A以環繞晶片10，其中輪狀部60A接觸於基板20之側壁、鈍化層30以及高分子層32。模塑化合物60之上表面可以是與金屬柱62之上表面為同 一水平面。後鈍化互連層38與高分子層40之形成與模塑化合物60重疊。凹槽52(其包含凹槽52A、52B以及/或52C)形成於模塑化合物46之中，其同於第5A圖、第5B圖與第6圖所示。於此部分的實施方式中，部分的凹槽52可以與晶片10重疊，同時其他部分的凹槽52可以與模塑化合物60的輪狀部60A重疊。第8圖之扇出型封裝件也可以貼合至第7圖的封裝元件200，且凹槽52也可以填充有底膠。
本揭露之實施方式具有些許有助益的技術特徵。藉由於包覆電性連接元件(例如焊球)的模塑化合物中形成凹槽，應力的路徑會被中斷，因此使得模塑化合物中的應力降低。也因此，由模塑化合物施予給底層的低介電常數材料層的應力也被降低。模擬的結果表示，於形成圓形孔洞以形成具有焊球之陣列的情況中，施予至低介電常數材料層的應力可以被降低大約43個百分比(請注意，由於此應力應與應用最小材料情況(least material condition；LMC)作為比較，因此此計算方式是由1-(0.88/1.55)而得)。
根據本揭露之部分的實施方式，晶片包含半導體基板、設置於半導體基板之上的電性連接元件以及成形於電性連接元件之底部的模塑化合物。模塑化合物之上表面低於電性連接元件之上端。凹槽自模塑化合物之上表面朝向模塑化合物內延伸。
根據本揭露之替代的實施方式，積體電路結構包含基板、位於基板之上的金屬墊、一部分位於金屬墊之上的鈍化層、位於鈍化層之上的高分子層與後鈍化互連層。後鈍化互 連層包含位於高分子層之上的第一部分以及延伸至高分子層內的第二部分。後鈍化互連層與該金屬墊電性連接。焊接區位於後鈍化互連層之上，並與後鈍化互連層電性連接。模塑化合物位於後鈍化互連層之上。模塑化合物包圍並以物理接觸於焊接區之底部部分。焊接區的上部部分自模塑化合物向外突出。凹槽自模塑化合物之上表面朝模塑化合物內延伸，其中凹槽之底部高於模塑化合物之下表面。
根據本揭露之其他替代的實施方式，方法包含分配模塑化合物於電性連接元件之上，其中電性連接元件位於晶圓的基板之上。方法更包含提供脫模薄膜於模塑化合物之上，並朝電性連接元件對脫模薄膜施壓，其中電性連接元件之頂部被壓入至脫模薄膜內。於脫模薄膜朝該模塑化合物進行施壓時，固化模塑化合物。自模塑化合物移除脫模薄膜。於模塑化合物中形成凹槽。
上敘概述了多個實施方法的特徵，使得本技術領域中具有通常知識者更可以理解本揭露之技術態樣。本技術領域中具有通常知識者應當理解，其可以適當地以本揭露作為基礎以設計或修改其他製程以及結構以實現相同目的和/或達到本文所教示之實施方法的相同優點。本技術領域中具有通常知識者應該也要瞭解到，等效的構造並不脫離本揭露的精神和範圍，且作出各種改變、替換和變更仍不脫離本揭露的精神和範圍。
10‧‧‧晶片
20‧‧‧基板
22‧‧‧互連結構
24‧‧‧主動元件
25‧‧‧低介電常數材料層
26‧‧‧金屬線與通孔
28‧‧‧金屬墊
30‧‧‧鈍化層
32、40‧‧‧高分子層
38‧‧‧後鈍化互連層
44‧‧‧電性連接元件
46‧‧‧模塑化合物
46A‧‧‧上表面
52、52A、52B、52C‧‧‧凹槽
53‧‧‧虛線
54‧‧‧刀片/鑽頭
56‧‧‧分隔線
100‧‧‧晶圓
D1‧‧‧深度
T1‧‧‧厚度

Claims (10)

  1. 一種積體電路結構，包含：一晶片，包含：一半導體基板；一電性連接元件，設置於該半導體基板之上；一模塑化合物，成形於該電性連接元件之底部，其中該模塑化合物之上表面低於該電性連接元件之上端，其中該模塑化合物之邊緣垂直地對齊該半導體基板之對應的邊緣；以及一凹槽，重疊於該半導體基板之該些邊緣且自該模塑化合物之上表面朝向該模塑化合物內延伸。
  2. 如申請專利範圍第1項之積體電路結構，其中該凹槽之底部位於該模塑化合物之上表面與下表面之間的中介高度。
  3. 如申請專利範圍第1項之積體電路結構，其中該凹槽之深度大致大於該模塑化合物之厚度的百分之五十。
  4. 如申請專利範圍第1項之積體電路結構，其中該凹槽形成一環形缺口且位於該晶片之邊緣。
  5. 一種積體電路結構，包含：一基板； 一金屬墊，設置於該基板之上；一鈍化層，該鈍化層之一部分位於該金屬墊之上；一高分子層，位於該鈍化層之上；一後鈍化互連層(post-passivation interconnect；PPI)，包含位於該高分子層之上的一第一部分以及延伸至該高分子層內的一第二部分，其中該後鈍化互連層與該金屬墊電性連接；一焊接區，位於該後鈍化互連層之上，並與該後鈍化互連層電性連接；一模塑化合物，位於該後鈍化互連層之上，其中該模塑化合物包圍並以物理接觸於該焊接區之底部部分，且其中該焊接區之上部部分自該模塑化合物向外突出；一凹槽，自該模塑化合物之上表面朝該模塑化合物內延伸，其中該凹槽之底部高於該模塑化合物之下表面，且該凹槽形成一矩形的環形缺口，該矩形的環形缺口包含四個部分，且每一該四個部分延伸至對應之個別晶片的邊緣，而該個別晶片之邊緣包含該基板之一邊緣。
  6. 如申請專利範圍第5項之積體電路結構，更包含：一外加封裝元件，接合於該焊接區之上；以及一底膠，位於該模塑化合物與該外加封裝元件之間的間隙，其中該底膠之一部分位於該凹槽中。
  7. 如申請專利範圍第5項之積體電路結構，更包含：複數個電性連接元件，具有圓形的上視形狀；以及複數個凹槽，包含該凹槽，其中該些電性連接元件與該些凹槽組合成一陣列。
  8. 一種積體電路結構的製造方法，包含：分配一模塑化合物於一電性連接元件之上，其中該電性連接元件重疊於一晶圓的一半導體基板之上；提供一脫模薄膜於該模塑化合物之上；朝該電性連接元件對該脫模薄膜施壓，其中該電性連接元件之頂部被壓入至該脫模薄膜內；於該脫模薄膜朝該模塑化合物進行施壓時，固化該模塑化合物；自該模塑化合物移除該脫模薄膜；以及於該模塑化合物中形成一凹槽，其中該凹槽重疊於該半導體基板之邊緣。
  9. 如申請專利範圍第8項之製造方法，於提供該脫模薄膜之前更包含：形成一鈍化層於一金屬墊之上，其中該金屬墊更覆蓋於該晶圓之該半導體基板；形成一後鈍化互連層，電性連接至該金屬墊，其中該後鈍化互連層之一部分覆蓋於該鈍化層；以及 形成一高分子層於該後鈍化互連層之上，其中該電性連接元件透過於該高分子層之中的一焊球下層金屬(under-bump metallurgy；UBM)與該後鈍化互連層電性連接，且其中該模塑化合物形成且接觸於該高分子層之上。
  10. 如申請專利範圍第8項之製造方法，更包含將該晶圓切成複數個封裝件，其中該凹槽於切斷該晶圓時被切斷。
TW103145301A 2014-02-07 2014-12-24 一種積體電路結構與其製造方法 TWI556367B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/175,080 US9472481B2 (en) 2014-02-07 2014-02-07 Packages with stress-reducing structures and methods of forming same

Publications (2)

Publication Number Publication Date
TW201532207A TW201532207A (zh) 2015-08-16
TWI556367B true TWI556367B (zh) 2016-11-01

Family

ID=53775594

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103145301A TWI556367B (zh) 2014-02-07 2014-12-24 一種積體電路結構與其製造方法

Country Status (2)

Country Link
US (4) US9472481B2 (zh)
TW (1) TWI556367B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9653417B2 (en) 2013-11-07 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for singulating packaged integrated circuits and resulting structures
US9484318B2 (en) * 2014-02-17 2016-11-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
KR102634946B1 (ko) * 2016-11-14 2024-02-07 삼성전자주식회사 반도체 칩
US11024593B2 (en) * 2018-09-28 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Metal bumps and method forming same
JP7291558B2 (ja) * 2019-07-03 2023-06-15 株式会社荏原製作所 渦電流センサ
US12103230B2 (en) * 2020-01-20 2024-10-01 Hewlett-Packard Development Company, L.P. Three-dimensional printing
KR20210115160A (ko) 2020-03-12 2021-09-27 삼성전자주식회사 Pid를 포함하는 반도체 패키지 및 이의 제조 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110233747A1 (en) * 2010-03-25 2011-09-29 Seongmin Lee Integrated circuit packaging system with stacking option and method of manufacture thereof
US20120228780A1 (en) * 2011-03-08 2012-09-13 Ji Hwang Kim Semiconductor device and method of manufacturing the same
US20130009307A1 (en) * 2011-07-08 2013-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3729573A (en) * 1971-01-25 1973-04-24 Motorola Inc Plastic encapsulation of semiconductor devices
JPH05144982A (ja) * 1991-11-19 1993-06-11 Nippon Precision Circuits Kk 集積回路装置
US6173490B1 (en) * 1997-08-20 2001-01-16 National Semiconductor Corporation Method for forming a panel of packaged integrated circuits
US7259448B2 (en) * 2001-05-07 2007-08-21 Broadcom Corporation Die-up ball grid array package with a heat spreader and method for making the same
TWI414047B (zh) * 2010-03-17 2013-11-01 Ind Tech Res Inst 電子元件封裝結構及其製造方法
US9431316B2 (en) * 2010-05-04 2016-08-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming channels in back surface of FO-WLCSP for heat dissipation
US8610267B2 (en) * 2010-07-21 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing delamination between an underfill and a buffer layer in a bond structure
US9627290B2 (en) * 2011-12-07 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure design for stress reduction
US9196532B2 (en) * 2012-06-21 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods for forming the same
US9318404B2 (en) * 2013-02-05 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110233747A1 (en) * 2010-03-25 2011-09-29 Seongmin Lee Integrated circuit packaging system with stacking option and method of manufacture thereof
US20120228780A1 (en) * 2011-03-08 2012-09-13 Ji Hwang Kim Semiconductor device and method of manufacturing the same
US20130009307A1 (en) * 2011-07-08 2013-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers

Also Published As

Publication number Publication date
TW201532207A (zh) 2015-08-16
US11658153B2 (en) 2023-05-23
US20170025394A1 (en) 2017-01-26
US9472481B2 (en) 2016-10-18
US20200286863A1 (en) 2020-09-10
US20150228600A1 (en) 2015-08-13
US10685936B2 (en) 2020-06-16
US20230253370A1 (en) 2023-08-10

Similar Documents

Publication Publication Date Title
TWI556367B (zh) 一種積體電路結構與其製造方法
US11984342B2 (en) Info structure with copper pillar having reversed profile
TWI732014B (zh) 封裝結構及其形成方法
TWI584423B (zh) 半導體封裝及其形成方法
KR101731684B1 (ko) 디바이스 다이의 링 구조물
TWI595614B (zh) 扇出型封裝物中之分離聚合物
TWI588916B (zh) 半導體裝置及製造其之方法
TWI584435B (zh) 封裝及其製造方法
TWI464859B (zh) 封裝結構與其製法
TWI629722B (zh) 晶圓級封裝中的切割
TW201539678A (zh) 封裝半導體裝置以及形成封裝半導體裝置之方法
US11476205B2 (en) Package structure and method for forming the same
TWI591797B (zh) 用於雷射標記的金屬墊
TWI587464B (zh) 封裝結構及其製造方法
US10658321B2 (en) Semiconductor chip, method for manufacturing semiconductor chip, integrated circuit device, and method for manufacturing integrated circuit device
JP2007165402A (ja) 半導体装置