TWI595614B - 扇出型封裝物中之分離聚合物 - Google Patents

扇出型封裝物中之分離聚合物 Download PDF

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TWI595614B
TWI595614B TW104139363A TW104139363A TWI595614B TW I595614 B TWI595614 B TW I595614B TW 104139363 A TW104139363 A TW 104139363A TW 104139363 A TW104139363 A TW 104139363A TW I595614 B TWI595614 B TW I595614B
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Taiwan
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molding compound
device die
package
layer
die
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TW104139363A
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TW201639093A (zh
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陳憲偉
陳潔
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台灣積體電路製造股份有限公司
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    • H01L2225/06503—Stacked arrangements of devices
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Description

扇出型封裝物中之分離聚合物
本揭露是關於一半導體封裝物。
隨著半導體技術的發展，半導體晶粒也越來越小。然而，卻需要將更多的功能整合到一半導體晶粒上。因此，半導體晶粒需要將在較小的面積上封裝入更多數目的輸入/輸出(I/O)墊，且I/O墊的密度也大幅提升。因此，半導體晶粒的封裝越來越困難，且使得量率降低。
封裝技術可分為兩大類。第一類通常稱為晶圓級封裝(Wafer Level Package，WLP)，這是在鋸切晶粒之前先封裝晶圓上的晶粒。WLP技術有某些優點，例如產率較高且成本較低。此外，其所需要的底膠或模塑料也較少。然而，WLP技術也有其缺點。習知的WLP只能是扇入型封裝，其中每一晶粒的I/O墊僅限於直接設於各別晶粒表面上方的區域內。由於晶圓的面積有限，I/O墊的數目會受到I/O墊間距的限制。若縮減I/O墊墊的間距，就可能發生錫橋(solder bridge)的問題。此外，在錫球尺寸固定的要求下，焊球必須要有特定的尺寸，這又會限制可放置於一晶圓表面上之焊球的數目。
在另一類的封裝技術中，在將晶粒封裝到其他晶圓上之前，先鋸切晶粒，且僅會封裝「已知良好的晶粒」。此種封裝技術的優點之一物是能夠形成扇出型封裝物，這表示在一晶粒上的I/O墊 可被重新分配至比晶粒本身還大的區域中，因此能夠增加可設置於晶粒表面上的I/O墊數目。
本揭露某些實施方式提出一封裝物，其包括第一模塑料、於第一模塑料中之下層裝置晶粒、於下層裝置晶粒及第一模塑料上之介電層、以及延伸至第一介電層中並電性耦接至下層裝置晶粒之複數個重佈線。所述封裝物進一步包括於介電層上之上層裝置晶粒，以及用以使其中之上層裝置晶粒成型之第二模塑料。第二模塑料之一部分的底面與第一模塑料之頂面接觸。
本揭露替代性的實施方式提出一封裝物，其包括第一模塑料、於第一模塑料中之下層裝置晶粒、於下層裝置晶粒及第一模塑料上之介電層、以及延伸至第一介電層中並電性耦接至下層裝置晶粒之第一複數個重佈線。上層裝置晶粒係設於第一聚合物層上。第二模塑料使其中之上層裝置晶粒成型，其中第一模塑料之第一邊緣以及第二模塑料之第二邊緣位於相同的平面中，以形成封裝物之邊緣。第二模塑料之一部分包括第二邊緣與第三邊緣，兩者互相相對，且第三邊緣與第一聚合物層接觸。一貫穿通路係設於第二模塑料中，其中通路與所述第一複數個重佈線其中之一將下層裝置晶粒電性耦接至上層裝置晶粒。
本揭露替代性的實施方式提出一方法，其包括使一下層裝置晶粒於第一模塑料中成型，平坦化第一模塑料，以使下層裝置晶粒裸露，形成第一聚合物層於第一模塑料上，圖案化第一聚合物層，以形成第一渠道，將上層裝置晶粒設於第一聚合物層上，以及使上層裝置晶粒於第二模塑料中成型，其中第二模塑料填充第一渠道以接觸第一模塑料。第二模塑料經平坦化，以使上層裝置晶粒裸露。
30‧‧‧載體
32‧‧‧黏著層
34‧‧‧緩衝層
36、52‧‧‧裝置晶粒
38、54‧‧‧晶粒附接膜
40、50、56‧‧‧金屬柱
42、46、58、62‧‧‧介電層
44、60‧‧‧模塑料
46A、60A、62A‧‧‧邊緣
48、64‧‧‧重佈線(RDL)
49、66‧‧‧開孔
68‧‧‧電連接件
70‧‧‧封裝物
72‧‧‧分離封裝物
74‧‧‧液態模塑料(模塑料)
76、80‧‧‧介面
76A、76B‧‧‧填料
78‧‧‧渠道
78A、78B‧‧‧聚合物
200‧‧‧方法
202-224‧‧‧步驟
D1、D2‧‧‧內凹距離
W1、W2、W3、W4‧‧‧寬度
在閱讀了下文實施方式以及附隨圖式時，能夠最佳地理解本揭露的多種態樣。應注意到，根據本領域的標準作業習慣，圖中的各種構件並未依比例繪製。事實上，為了能夠清楚地進行描述，可能會刻意地放大或縮小某些構件的尺寸。
圖1至圖11繪示根據某些實施方式，於形成多層堆疊之扇出型封裝物之中間階段的剖面圖；圖12繪示多層堆疊扇出型封裝物之一部分的上視圖；圖13繪示根據某些實施方式，多層堆疊扇之出型封裝物之一部分的放大圖；圖14至圖16繪示根據替代性實施方式，於形成多層堆疊之扇出型封裝物之中間階段的剖面圖，其中於上聚合物層中並未形成開孔；圖17與圖18繪示根據替代性實施方式，於形成多層堆疊之扇出型封裝物之中間階段的剖面圖，其中施用液態模塑料；圖19與圖21繪示根據替代性實施方式，於形成多層堆疊之扇出型封裝物之中間階段的剖面圖，其中於施用液態模塑料之前進行部分切割；以及圖22繪示根據某些實施方式，用以形成多層堆疊扇出型封裝物之方法的流程圖。
以下揭示內容提供了多種實施方式或例示，其能用以實現本揭示內容的不同特徵。下文所述之元件與配置的具體例子係用以簡化本揭示內容。當可想見，這些敘述僅為例示，其本意並非用於限制本揭示內容。舉例來說，在下文的描述中，將一第一構件形成於一第二構件上或之上，可能包含某些實施例其中所述的第一與第二構件彼此直接接觸；且也可能包含某些實施例其中還有而外的元件形成 於上述第一與第二構件之間，而使得第一與第二構件可能沒有直接接觸。此外，本揭示內容可能會在多個實施例中重複使用元件符號和/或標號。此種重複使用乃是基於簡潔與清楚之目的，且其本身不代表所討論的不同實施例和/或組態之間的關係。
再者，在此處使用空間上相對的詞彙，譬如「之下」、「下方」、「低於」、「之上」、「上方」及與其相似者，可能是為了方便說明圖中所繪示的一元件或構件相對於另一或多個元件或構件之間的關係。這些空間上相對的詞彙其本意除了圖中所繪示的方位之外，還涵蓋了裝置在使用或操作中所處的多種不同方位。可能將所述設備放置於其他方位(如，旋轉90度或處於其他方位)，而這些空間上相對的描述詞彙就應該做相應的解釋。
根據多種例示性的實施方式，提出了一種多層堆疊扇出型封裝物及其形成方法。繪示了形成多層堆疊扇出型封裝物之中間階段，討論實施方式之變形。在不同的圖式與多個說明性的實施方式中，使用類似的元件符號來指稱相似的部件。
圖1至圖11繪示根據某些實施方式，於形成多層堆疊之扇出型封裝物之中間階段的剖面圖。在下文的討論中，參照圖22所示之製程步驟來說明圖1至圖11的製程步驟。
參照圖1，提供載體30，且於載體30上設有黏著層32。載體30可以是空白玻璃載體、空白陶瓷載體或與其相似者，且其形狀可如半導體晶圓，一般由上方看來成圓形。載體30有時亦稱為載體晶圓。可利用譬如光熱轉換(Light-to-Heat Conversion，LTHC)材料來形成黏著層32，且亦可使用其他種類的黏著劑。根據本揭露某些實施方式，黏著層32會在光的熱能影響下分解，且能夠使載體30與形成於其上之結構分離。
於黏著層32上形成緩衝層34。根據本揭露某些實施方 式，緩衝層34是由苯并口咢唑(polybenzoxazole，PBO)、聚醯亞胺或與其相似者所形成之聚合物層。
多個裝置晶粒36係設於緩衝層34上。此步驟如圖22之流程圖之步驟202所示。可透過晶粒附接膜38，將裝置晶粒36接著至緩衝層34。晶粒附接膜38之邊緣與其上之各別裝置晶粒36的邊緣共邊緣(對齊)。晶粒附接膜38為黏性膜。可將所放置之該些裝置晶粒36排列為包括複數個行與複數個列之陣列。裝置晶粒36可包括一半導體基板，其有一後表面(朝下之表面)與各別晶粒附接膜38相接觸。裝置晶粒36進一步包括積體電路裝置(譬如主動元件，其包括如電晶體；圖中未繪示)，其位於半導體基板之前表面(朝上之表面)。裝置晶粒36可包括記憶體晶粒，如靜態隨機存取記憶體(Static Random Access Memory，SRAM)晶粒、動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)晶粒或與其相似者。
裝置晶粒36包括了在其頂面的導電性構件，譬如金屬柱40。金屬柱40電性耦接至裝置晶粒36內之積體電路。根據本揭露某些例示性之實施方式，金屬柱40之頂面為裸露的，如圖1所示。金屬柱40可以是銅柱，且亦可包括其他導電性/金屬材料，譬如鋁、鎳或與其相似者。根據本揭露某些實施方式，金屬柱40之頂面與介電層42之頂面共平面。根據本揭露可替代的實施方式，金屬柱40係嵌於介電層42中，而介電層42之頂面高於金屬柱40之頂面。介電層42可由聚合物所形成，所述聚合物可包括PBO、聚醯亞胺或與其相似者。於本說明書中，裝置晶粒36亦稱為第一層(level-1)晶粒或下層晶粒。
參照圖2，模塑料44於裝置晶粒36上成型。此步驟如圖22之流程圖之步驟204所示。以液體形式施佈模塑料44，且之後利用譬如熱固化製程使其固化。模塑料44可填充於裝置晶粒36之間的間隙，且可和緩衝層34接觸。模塑料44可包括模塑料、成型底膠、環氧 樹脂或樹脂。在成型製程之後，模塑料44之頂面高於金屬柱40之上端。
接著進行平坦化步驟例如化學機械研磨(Chemical Mechanical Polish，CMP)步驟或研磨步驟，以使模塑料44平坦化，直到裝置晶粒36之金屬柱40裸露為止。此步驟如圖22之流程圖之步驟206所示。所得到之結構如圖3所示。由於平坦化作業的關係，金屬柱40之頂面實質上和模塑料44之頂面齊平(共平面)。
參照圖4，於模塑料44及金屬柱40上形成一或更多層的介電層46與各別的重佈線(Redistribution Line，RDL)48。此步驟如圖22之流程圖之步驟208所示。根據本揭露某些實施方式，介電層46係由一或多種聚合物所形成，譬如PBO、聚醯亞胺或與其相似者。根據本揭露可替代的實施方式，介電層46係由無機介電材料(們)所形成，譬如氮化矽、氧化矽、矽氮氧化物或與其相似者。
RDL 48經形成而能夠電性耦接至金屬柱40。RDL 48可包括金屬導線(金屬線)與通路，所述通路位於金屬導線下方並連接至各別金屬導線。根據本揭露某些實施方式，經由鍍覆製程來形成RDL 48，其中每一RDL 48包括一晶種層(圖中未繪示)及於晶種層上之經鍍覆之金屬材料。可利用相同或不同的材料來形成晶種層及經鍍覆之金屬材料。
在形成RDL 48的過程中，將介電層46圖案化以形成通路開孔(由RDL 48所佔據)，且上層RDL 48延伸進入通路開孔內以接觸下層RDL 48或金屬柱40。同時，形成通路開孔，移除介電層46之某些部分，以在介電層46中形成開孔49。可利用相同的微影遮罩與相同的微影製程，來進行通路開孔與開孔49之形成。開孔49可形成一格柵，其包括水平開孔(渠道，由上方觀之)其與垂直的開孔交錯。因此，介電層46留存之部分位於所述格柵所定義之區域內。
參照圖5，金屬柱50係形成於介電層46上，且電性連接至RDL 48。在本說明書中，金屬柱50亦稱為貫穿通路50，因為金屬柱50穿透其後形成之模塑料。此步驟如圖22流程圖之步驟210所示。貫穿通路50經由形成於介電層46上層中之通路而連接至RDL 48。根據本揭露某些實施方式，利用鍍覆法形成貫穿通路50，且其形成製程可包括圖案化介電層46之上層，以形成開孔而使RDL 48裸露；於開孔形成一披覆晶種層(圖中未繪示)；形成並圖案化光阻(圖中未繪示)；以及鍍覆晶種層之部分上因光阻中之開孔而裸露之貫穿通路50。之後，移除光阻及被所移除之光阻所覆蓋之晶種層部分。貫穿通路50之材料可包括銅、鋁、鎳、鎢或與其相似者。貫穿通路50的形狀為柱狀。貫穿通路50的上視形狀可以是圓形、矩形、正方形、六邊形或與其相似者。
圖6繪示裝置晶粒52經放置於介電層46上。在本說明書中，裝置晶粒52亦稱為第二級晶粒或上層晶粒。此步驟如圖22流程圖之步驟212所示。可經由晶粒附接膜54將裝置晶粒52接著至上方介電層46，所述晶粒附接膜54為黏性膜。每一裝置晶粒52可包括一半導體基板，其有一後表面(朝下之表面)與各別晶粒附接膜54物理接觸。裝置晶粒52進一步包括積體電路裝置(譬如主動元件，其包括如電晶體，圖中未繪示)，其位於半導體基板之前表面(朝上之表面)。裝置晶粒52可包括邏輯晶粒，譬如中央處理單元(Central Processing Unit，CPU)晶粒、圖形處理單元(Graphic Processing Unit，GPU)晶粒、行動應用晶粒或與其相似者。裝置晶粒52亦可包括單晶片(System on Chip，SoC)晶粒。
裝置晶粒52之頂面上包括導電性構件譬如金屬柱56。金屬柱56係電性耦接至裝置晶粒內之積體電路。根據本揭露某些例示性之實施方式，如圖6所示，金屬柱56之頂面為裸露的。金屬柱56可 以是銅柱，且亦可亦可包括其他導電性/金屬材料，如鋁、鎳或與其相似者。根據本揭露某些實施方式，金屬柱56之頂面與介電層58之頂面共平面。根據本揭露可替代的實施方式，金屬柱56嵌於介電層58內，且介電層58之頂面高於金屬柱56之頂面。介電層58可由聚合物所形成，其可包括PBO、聚醯亞胺或與其相似者。
參照圖7，模塑料60於裝置晶粒52及貫穿通路50上成型。此步驟如圖22流程圖之步驟214所示。模塑料60可包括模塑料、成型底膠、環氧樹脂或樹脂。在成型製程之後，模塑料60之頂面高於金屬柱56及貫穿通路50的上端。將模塑料60填入開孔49(圖6)中，以接觸模塑料44。根據本揭露某些實施方式，可利用相同的模塑料來形成上述模塑料44與模塑料60。根據可替代的實施方式，可利用不同類型的模塑料來形成上述模塑料44與模塑料60。
接著進行平坦化步驟，以使模塑料60平坦化，直到貫穿通路50裸露為止。此步驟如圖22流程圖之步驟216所示。所得之結構如圖8所示。裝置晶粒52之金屬柱56也會因為平坦化作業而裸露。由於平坦化作業的關係，貫穿通路50之頂面實質上和模塑料60之頂面齊平(共平面)。
參照圖9，於模塑料60、貫穿通路50及金屬柱56上形成一或更多層的介電層62與各別的重佈線(RDL)64。此步驟如圖22之流程圖之步驟218所示。根據本揭露某些實施方式，介電層62係由一或多種聚合物所形成，譬如PBO、聚醯亞胺或與其相似者。根據本揭露可替代的實施方式，介電層62係由無機介電材料(們)所形成，譬如氮化矽、氧化矽、矽氮氧化物或與其相似者。
RDL 64經形成而能夠電性耦接至金屬柱56及貫穿通路50。RDL 64亦可將金屬柱56、貫穿通路50與金屬柱40彼此電性互連。RDL 64可包括金屬導線與通路，所述通路位於金屬導線下方並 連接至金屬導線。根據本揭露某些實施方式，經由鍍覆製程來形成RDL 64，其中每一RDL 64包括一晶種層(圖中未繪示)及設於晶種層上之經鍍覆之金屬材料。可利用相同或不同的材料來形成晶種層及經鍍覆之金屬材料。
在形成RDL 64的過程中，將介電層62圖案化以形成通路開孔(由RDL 64所佔據)，且上層RDL 64延伸進入通路開孔內以接觸下層RDL 64或金屬柱56。同時，形成通路開孔，移除介電層62之某些部分以在介電層62中形成開孔66。可利用相同的微影遮罩與相同的微影製程，來進行通路開孔與開孔66之形成。開孔66可形成一格柵，而介電層62留存之部分位於所述格柵所定義之區域內。因此，模塑料60經由開孔66而裸露。
圖10繪示根據本揭露某些例示性之實施方式，電連接件68之形成。此步驟如圖22流程圖之步驟224所示。電連接件68係電性耦接至RDL 64、金屬柱40及56、和/或貫穿通路50。電連接件68之形成可包括將焊球放置於RDL 64上，且之後使焊球回流。根據本揭露可替代的實施方式，電連接件68之形成包括進行鍍覆步驟以於RDL 64上形成焊料區域，且之後回流焊料區域。電連接件68亦可包括金屬柱或金屬柱與焊料帽，其亦可經由鍍覆而形成。在本說明書中，包括裝置晶粒52、貫穿通路50、模塑料60、RDL 64與介電層62之總體結構稱為封裝物70，其亦為一複合晶圓。
根據本揭露某些實施方式，開孔49之寬度W1(亦參見圖4)介於約100μm至約300μm之間。開孔66之寬度W2介於約100μm至約300μm之間。寬度W2可大於或等於寬度W1。鋸切線之寬度W3介於約30μm至約40μm之間。
接著使封裝物70由載體30脫離。根據某些例示性之脫離製程，將切割膠帶(圖中未繪示)接著至封裝物70以保護電連接件 68。可藉由譬如在黏著層32投射UV光線或雷射，以使封裝物70與載體30脫離。譬如，當黏著層32是由LTHC所形成時，光線或雷射所產生的熱會使得LTHC分解，且因而載體30會由封裝物70脫離。在後續的步驟中，進行晶粒鋸切，以將封裝物70鋸切為多個分離封裝物72。其步驟亦如步驟224所示。
圖11繪示所得之分離封裝物72。封裝物72包括位於下層之裝置晶粒36以及位於上層之裝置晶粒52。裝置晶粒36與52經由RDL 48與64以及貫穿通路50而電性互連，以形成一多層堆疊封裝物72。介電層46，可以是聚合物層，其係形成於下層晶粒(們)36與上層晶粒52之間。下層晶粒36係於模塑料44中成型，且上層晶粒52係於模塑料60中成型。模塑料60向下延伸，且模塑料60之一部分與介電層46共平面。
圖12繪示分離封裝物72之一部分的上視圖，其中在介電層46的高度取得此上視圖。如圖12所示，模塑料60之一部分(在下文中稱為一環部)環繞介電層46。此外，介電層62之邊緣62A並未與模塑料44與60的各別邊緣對齊，而是朝向封裝物72之中心內凹。
根據本揭露某些實施方式，介電層62之邊緣62A自模塑料60的邊緣60A(以及模塑料44的邊緣44A)以距離D1而內凹，內凹距離D1可介於約30μm至約130μm之間。模塑料60之環部的寬度等於內凹距離D2，內凹距離D2是介電層46之其邊緣46A自模塑料60之邊緣60A內凹之內凹距離。內凹距離D2亦可介於約30μm至約130μm之間。
再者，模塑料60之環部的底面與介電層46之底面共平面，如圖11所示，且與模塑料44之頂面接觸以形成介面80。不論模塑料44與60是由相同材料或不同模塑料所形成，由於模塑料44的平坦化作業，介面80都是可區分的。譬如，圖13繪示封裝物72於區域74(圖 11)中之一部分的簡要放大圖。模塑料44可包括聚合物78A中之填料76A。模塑料60可包括聚合物78B中之填料76B。填料76A及76B可由氧化矽、氧化鋁、氮化鋁、碳化矽或與其相似者，且填料76A之材料可和填料76B之材料相同或不同。再者，填料76A與76B之形狀可為球體。由於模塑料44之平坦化作業的關係，填料76A也會被研磨，而某些填料76A之上部會被移除。因此，某些填料76A的上部有平面的頂面且與介面80共平面，而這些填料76A的下方部分則仍為圓形。另一方面，與介面80接觸之某些填料76B在和介面80共平面的底部端仍為圓形。因此，可藉由填料76A及76B的形狀區別出介面80。
圖14至圖16繪示根據本揭露可替代的實施方式，於形成多層堆疊之扇出型封裝物之中間階段的剖面圖。除非另有說明，這些實施方式中組件之材料與形成方法實質上和參照圖1至圖13所示之實施方式中的相似組件(以相同元件符號表示)所用者相同。因此，關於圖14至圖16(圖17至圖21亦然)所示組件之形成製程與材料的細節，可參見圖1至圖13所示之實施方式的相關討論。
這些實施方式的起始步驟實質上和圖1至圖8所示者相同。接著，如圖14所示，形成介電層62與RDL 64。形成製程與圖9所示製程相似，只不過當在介電層62中形成通路開孔時，不會在裝置晶粒52之間形成開孔。換句話說，這些實施方式中不會形成圖9所示之開孔66。接著如圖15所示，形成電連接件68並進行晶粒鋸切，以將封裝物70分離為多個封裝物72。所得之一分離封裝物72如圖16所示。圖16之封裝物72與圖11所示之封裝物72類似，只不過介電層62之邊緣與模塑料44與60的各別邊緣垂直對齊(兩者其共端點且位於相同的垂直平面)。
圖17及圖18繪示根據本揭露又一可替代的實施方式，於形成多層堆疊之扇出型封裝物之中間階段的剖面圖。這些實施方式 的起始步驟實質上和圖1至圖9所示者相同。接著，如圖17所示，施佈液態模塑料74以保護封裝物70，其中電連接件68之下方部分係成型於液態模塑料74中。此步驟如圖22流程圖之步驟222所示，其中虛線方塊表示在不同實施方式中，可進行或跳過步驟222。成型製程包括施佈液態模塑料74，以及利用離型膜(圖中未繪示)加壓液態模塑料74，而使得電連接件68的上部被壓入離型膜中，且多餘的液態模塑料74會被離型膜擠壓至封裝物72外。之後將液態模塑料74固化。接著移除離型膜，以得到圖17中之結構。在下文中，經固化之液態模塑料74稱為模塑料74。模塑料60與74可由相同的模塑料或不同的模塑料所形成。
之後，使封裝物70與載體30脫離並將其鋸切。所得到之分離封裝物72如圖18所示。在封裝物72中，除了環繞介電層46之模塑料60的環部(一個完整的全環)之外，模塑料74也有環繞介電層62之環部(一個完整的全環)。模塑料74之底面接觸模塑料60之頂面，以形成介面76。介面76是可區分的，因為模塑料60經過研磨或拋光，且因此模塑料60中之填料經過拋光，使得其有平面的頂面並與介面76共平面。介面76之可區分的構件類似圖13所示者。
圖19至圖21繪示根據本揭露可替代的實施方式，於形成多層堆疊之扇出型封裝物之中間階段的剖面圖。這些實施方式的起始步驟實質上和圖1至圖9所示者相同。接著，如圖19所示，進行部分裁切以裁切(譬如，經由鋸切)至模塑料60中，且因而在模塑料60內形成渠道78。此步驟如圖22流程圖之步驟220所示。可將渠道78對齊至各別上方渠道66之中心。渠道78之底部可位於上方介電層46之頂面以及底部介電層46之底面之間的中間高度。根據某些例示性之實施方式，渠道78之寬度W4介於約50μm至約80μm之間。渠道78之深度介於約50μm至約80μm之間。同樣地，渠道78可形成一格柵，而介電 層46位於格柵所定義之格柵開孔內。
圖20繪示模塑料74之形成，譬如，藉由施佈與固化液態模塑料。模塑料74填充於渠道78中(圖19)並接觸其側壁與模塑料60之頂面。
之後將封裝物70自載體30脫離並將其鋸切。由封裝物70鋸切所得之封裝物72如圖21所示。在根據這些實施方式之封裝物72中，模塑料74之部分係填入於渠道78中(圖19)而形成環繞模塑料60之部分的環部。再者，模塑料74也有一環部，圍繞介電層62及介電層46上部的至少一部分。
本揭露之實施方式具有某些優點。藉由圖案化於下層晶粒及上層晶粒之間的聚合物層，於製備過程中，可將聚合物層分為分離的部分，且因而可降低聚合物層對封裝物所造成的應力。原本由聚合物層所佔據的空間因此改由包括填料之模塑料所佔據，且因此其導致封裝物中之翹曲的效應小於聚合物面積較大者之翹曲效應。
本揭露某些實施方式提出一封裝物，其包括第一模塑料、於第一模塑料中之下層裝置晶粒、於下層裝置晶粒及第一模塑料上之介電層、以及延伸至第一介電層中並電性耦接至下層裝置晶粒之複數個重佈線。所述封裝物進一步包括於介電層上之上層裝置晶粒，以及用以使其中之上層裝置晶粒成型之第二模塑料。第二模塑料之一部分的底面與第一模塑料之頂面接觸。
本揭露替代性的實施方式提出一封裝物，其包括第一模塑料、於第一模塑料中之下層裝置晶粒、於下層裝置晶粒及第一模塑料上之介電層、以及延伸至第一介電層中並電性耦接至下層裝置晶粒之第一複數個重佈線。上層裝置晶粒係設於第一聚合物層上。第二模塑料使其中之上層裝置晶粒成型，其中第一模塑料之第一邊緣以及第二模塑料之第二邊緣位於相同的平面中，以形成封裝物之邊緣。第 二模塑料之一部分包括第二邊緣與第三邊緣，兩者互相相對，且第三邊緣與第一聚合物層接觸。一貫穿通路係設於第二模塑料中，其中貫穿通路與所述第一複數個重佈線其中之一將下層裝置晶粒電性耦接至上層裝置晶粒。
本揭露替代性的實施方式提出一方法，其包括使一下層裝置晶粒於第一模塑料中成型，平坦化第一模塑料，以使下層裝置晶粒裸露，形成第一聚合物層於第一模塑料上，圖案化第一聚合物層，以形成第一渠道，將上層裝置晶粒設於第一聚合物層上，以及使上層裝置晶粒於第二模塑料中成型，其中第二模塑料填充第一渠道以接觸第一模塑料。第二模塑料經平坦化，以使上層裝置晶粒裸露。
上文的敘述簡要地提出了本發明某些實施例之特徵，而使得本發明所屬技術領域具有通常知識者能夠更全面地理解本揭示內容的多種態樣。本發明所屬技術領域具有通常知識者當可明瞭，其可輕易地利用本揭示內容作為基礎，來設計或更動其他製程與結構，以實現與此處所述之實施方式相同的目的和/或達到相同的優點。本發明所屬技術領域具有通常知識者應當明白，這些均等的實施方式仍屬於本揭示內容之精神與範圍，且其可進行各種變更、替代與更動，而不會悖離本揭示內容之精神與範圍。
200‧‧‧方法
202-224‧‧‧步驟

Claims (10)

  1. 一種封裝物，其包括：一第一模塑料；一下層裝置晶粒，於該第一模塑料中；一第一介電層，於該下層裝置晶粒及該第一模塑料上；複數個重佈線，延伸進入該第一介電層中以電性耦接至該下層裝置晶粒；一上層裝置晶粒，於該第一介電層上；以及一第二模塑料，用以使其中之該上層裝置晶粒成型，其中該第二模塑料之一部分的一底面接觸該第一模塑料的一頂面。
  2. 如請求項1所述的封裝物，其中該第二模塑料之該部分形成環繞該第一介電層之一全環。
  3. 如請求項1所述的封裝物，其中該第一模塑料及該第二模塑料形成一可區分介面。
  4. 如請求項1所述的封裝物，進一步包括：一第二介電層，於該上層裝置晶粒及該第二模塑料上，其中該第二介電層之一邊緣平行於該封裝物之一邊緣，且比該封裝物之該邊緣更朝向該封裝物之一中心而下凹。
  5. 如請求項4所述的封裝物，進一步包括一第三模塑料，其包括：一環部，環繞該第二介電層，其中該環部接觸該第二模塑料之一頂面。
  6. 如請求項5所述的封裝物，其中該第二模塑料及該第三模塑料之該環部形成一可區分介面。
  7. 如請求項5所述的封裝物，其中該第三模塑料之該環部進一步包括與該第二模塑料共平面且環繞該第二模塑料之一部分。
  8. 如請求項1所述的封裝物，進一步包括一貫穿通路，其貫穿該第二模塑料，其中該貫穿通路將該下層裝置晶粒電性耦接至該上層裝置晶粒。
  9. 一種封裝物，其包括：一第一模塑料；一下層裝置晶粒，於該第一模塑料中；一第一聚合物層，於該下層裝置晶粒及該第一模塑料上；一第一複數個重佈線，延伸進入該第一聚合物層中以電性耦接至該下層裝置晶粒；一上層裝置晶粒，於該第一聚合物層上；一第二模塑料，用以使其中之該上層裝置晶粒成型，其中該第一模塑料之一第一邊緣及該第二模塑料之一第二邊緣位於一相同平面中，以形成該封裝物之一邊緣，且其中該第二模塑料之一部分包括該第二邊緣及一第三邊緣，兩者彼此相對且該第三邊緣與該第一聚合物層接觸；以及一貫穿通路，於該第二模塑料中，其中該貫穿通路與該第一複數個重佈線其中之一將該下層裝置晶粒電性耦接至該上層裝置晶粒。
  10. 一種用以形成多層堆疊扇出型封裝物之方法，其包括：使一下層裝置晶粒於一第一模塑料中成型；平坦化該第一模塑料，以使該下層裝置晶粒裸露；形成一第一聚合物層於該第一模塑料上；圖案化該第一聚合物層，以形成一第一渠道；將一上層裝置晶粒設於該第一聚合物層上；使該上層裝置晶粒於一第二模塑料中成型，其中該第二模塑料填充該第一渠道以接觸該第一模塑料；以及 平坦化該第二模塑料，以使該上層裝置晶粒裸露。
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US20160307872A1 (en) 2016-10-20
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US9837379B2 (en) 2017-12-05
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US20180090465A1 (en) 2018-03-29
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