TWI629722B - 晶圓級封裝中的切割 - Google Patents

晶圓級封裝中的切割 Download PDF

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Publication number
TWI629722B
TWI629722B TW104139608A TW104139608A TWI629722B TW I629722 B TWI629722 B TW I629722B TW 104139608 A TW104139608 A TW 104139608A TW 104139608 A TW104139608 A TW 104139608A TW I629722 B TWI629722 B TW I629722B
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Taiwan
Prior art keywords
die
edge
package
trench
packaging material
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TW104139608A
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English (en)
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TW201701339A (zh
Inventor
鄭佳申
蘇安治
劉重希
林修任
陳憲偉
鄭明達
陳威宇
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台灣積體電路製造股份有限公司
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Publication of TW201701339A publication Critical patent/TW201701339A/zh
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Publication of TWI629722B publication Critical patent/TWI629722B/zh

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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

一種方法包括：將第一元件晶粒和第二元件晶粒放置在載體之上，且該第一元件晶粒和該第二元件晶粒之間具有切割道。使用封裝材料封裝該第一元件晶粒和該第二元件晶粒，該封裝材料包括該切割道中的部分。該方法進一步包括在該封裝材料之上形成介電層，進行第一晶粒切割以在該切割道中形成第一溝槽，進行第二晶粒切割以在該切割道中形成第二溝槽，以及在該切割道上進行第三晶粒切割以將該第一元件晶粒與該第二元件晶粒分離。

Description

晶圓級封裝中的切割
本揭露涉及晶圓級封裝中的切割。
隨著半導體技術的不斷發展，半導體晶片/晶粒變得越來越小。與此同時，需要集成更多功能到半導體晶粒上。因此，半導體晶粒需要在更小區域上封裝數量越來越大的I/O墊，並且I/O墊的密度隨時間迅速上升。其結果是，該半導體晶粒的封裝變得更加困難，對封裝的產率產生不利影響。
傳統的封裝技術可以分為兩類。在第一類中，晶圓上的晶粒在它們切割之前被封裝。該封裝技術具有一些有利的特點，如更大的生產量和較低的成本。另外，需要較少的底膠填充或模塑料。然而，該封裝技術還有缺點。由於晶粒的尺寸變得越來越小，各自的封裝只能是扇入型封裝，其中每個晶粒的I/O墊被限制在每個晶粒表面正上方的區域。由於所述晶粒的區域有限，I/O墊的數量由於I/O墊間距的限制而受到限制。如果所述墊的間距被降低，可能會發生橋焊。此外，在球大小固定的要求下，焊球必須具有一定的尺寸，其反過來限制可以封裝在晶粒表面的所述焊球的數量。
在另一類封裝中，晶粒在其封裝之前從晶圓切割。這種封裝技術的有利特徵是可以形成扇出封裝，這意味著晶粒上的I/O墊可以被重新分配到比晶粒更大區域，因此可以增加封裝在晶粒表面的I/O墊 的數量。這種封裝技術的另一個有利特徵是，“已知良好的晶粒(known-good-dies)”被封裝，並且丟棄有缺陷的晶粒，因此成本和精力都不會浪費在有缺陷的晶粒上。
根據本揭露的一些實施例，一種方法包括將第一元件晶粒和第二元件晶粒放置在載體之上，且該第一元件晶粒和該第二元件晶粒之間具有切割道。該第一元件晶粒和該第二元件晶粒使用封裝材料封裝，該封裝材料具有該切割道中的部分。該方法還包括在該封裝材料之上形成介電層，進行第一晶粒切割以在切割道中形成第一溝槽，進行第二晶粒切割以在切割道中形成第二溝槽，以及在切割道上進行第三晶粒切割以將該第一元件晶粒與該第二元件晶粒分離。
根據本揭露的一些實施例，一種方法包括將第一元件晶粒和第二元件晶粒置於載體之上，且該第一元件晶粒和第二元件晶粒間具有切割道。該第一元件晶粒和該第二元件晶粒被封裝材料封裝，該封裝材料具有切割道中的部分。該方法還包括在封裝材料之上形成聚合物層，該聚合物層包括該切割道中的部分，並在該切割道中進行第一晶粒切割以形成第一溝槽。利用第一刀片進行該第一晶粒切割。在該切割道上執行二晶粒切割。該第二晶粒切割使用比該第一刀片寬的第二刀片進行。
根據本揭露的一些實施例，封裝包括元件晶粒和包圍元件晶粒的封裝材料。該封裝材料具有實質上垂直於封裝材料主頂面的第一邊緣。該封裝還包括聚合物層，其具有位於與該第一邊緣的元件晶粒相同側上的第二邊緣。該第二邊緣從該第一邊緣朝元件晶粒凹陷。
20、162、300‧‧‧封裝
30‧‧‧載體
32‧‧‧黏合層
34、51、56‧‧‧介電層
40‧‧‧導電晶種層
42‧‧‧光阻
44‧‧‧開口
46‧‧‧貫穿通路
48‧‧‧元件晶粒
50‧‧‧晶粒附接膜
52‧‧‧封裝材料
52A、52B、56A‧‧‧邊緣
54‧‧‧金屬柱
58‧‧‧RDL
60‧‧‧電連接器
62‧‧‧晶圓級封裝
63‧‧‧開口
64‧‧‧切割膠帶
65‧‧‧雷射光束
67、166、170、174‧‧‧溝槽
70‧‧‧焊接區
72‧‧‧底膠填充
162C‧‧‧主頂面
163‧‧‧切割道
164、172‧‧‧刀片
168‧‧‧中線
302‧‧‧基板
304‧‧‧元件晶粒
W1、W2、W3、W4‧‧‧寬度
α、β‧‧‧傾斜角
D1‧‧‧深度
D3‧‧‧長度
200方法‧‧‧方法
202、204、206、208、210‧‧‧步驟
212、214、216、218、220‧‧‧步驟
222、224、226、228‧‧‧步驟
結合附圖閱讀下面的詳細描述，可以更好地理解本揭露的各個 方面。應該注意的是，根據本行業的標準做法，各種特徵並非按比例繪製。事實上，為了討論的清晰，各種特徵的尺寸可以任意增加或減少。
圖1至圖21B示出根據一些實施例的扇出堆疊式封裝(Package-on-Package,PoP)形成的中間階段的剖面圖和俯視圖；圖22示出根據一些實施例的切割步驟中晶圓級封裝的俯視圖；和圖23示出根據一些實施例的形成PoP封裝的流程圖。
以下公開內容提供了許多不同的實施例或示例，用於實現本揭露的不同特徵。元件和佈置的具體實例描述如下，以簡化本揭露。當然，這些元件和佈置僅僅是示例性的，並不意在限制本揭露。例如，以下描述中在第二特徵之上或在第二特徵上形成第一特徵可以包括形成直接接觸的第一特徵和第二特徵的實施例，還可以包括在第一特徵和第二特徵之間可以形成附加特徵從而使得第一特徵和第二特徵可以不直接接觸的實施例。此外，本揭露可以在各個示例中重複使用符號和/或字母。這種重複使用用於簡化和清楚的目的，其本身並不表明所討論的各個實施例和/或配置之間的關係。
而且，空間關係術語，例如“之下”、“下方”、“下面”、“之上”、“上方”等，在此用於簡化描述附圖所示的一個單元或特徵對另一個單元或特徵的關係。除了附圖中描寫的方向，空間關係術語旨在包含使用或操作的裝置的不同方向。元件可以以其他方式定向(旋轉90度或者在其他方向)，並可以據此同樣地解釋本文所使用的空間關係描述語。
根據各種示例性的實施例，提供了扇出堆疊式封裝(PoP)結構/封裝以及形成封裝的方法。討論了一些實施例的變體。在各個視圖和示意性的實施例中，相同的符號用於表示相同的元件。
圖1至圖21B示出根據本揭露一些實施例的扇出堆疊式封裝(PoP)形成中間階段的剖面圖和俯視圖。圖1至圖21B所示的步驟還在圖23所示的處理流程200中示意性的示出。在隨後的討論中，參照圖23示出的處理步驟，对圖1至圖21B所示的處理步驟進行討論。
參照圖1，提供了載體30，並且黏合層32放置在載體30之上。載體30可以是空白玻璃載體，空白陶瓷載體，或類似物，並且可具有俯視圖為圓形的半導體晶圓的形狀。載體30有時被稱為載體晶圓。例如，黏合層32可以由光熱轉換(Light-to-Heat Conversion,LTHC)材料形成，儘管也可使用其他類型的黏合劑。根據本揭露的一些實施例，黏合層32能夠在光的熱量之下分解，因此可以從其上形成的結構釋放載體30。
參照圖2，介電層34在黏合層32之上形成。相應的步驟如圖23的處理流程中的步驟202所示。根據本揭露的一些實施例，介電層34是由聚合物形成的聚合物層，其可以是光敏感的聚合物，例如聚苯並惡唑(PBO)，聚醯亞胺，或類似物。根據一些實施例，介電層34由如氮化矽的氮化物、如氧化矽的氧化物、磷矽酸鹽玻璃(PhosphoSilicate Glass,PSG)、硼矽玻璃(BoroSilicate Glass,BSG)、硼摻雜磷矽酸鹽玻璃(Boron-doped PhosphoSilicate Glass,BPSG)或類似物形成。
參照圖3，導電晶種層40在介電層34上方形成，例如，藉由物理氣相沉積(PVD)。相應的步驟如圖23的處理流程中的步驟206所示。導電晶種層40可以是金屬晶種層，包括銅，鋁，鈦，以及上述金屬的合金，或上述金屬或合金的多層。根據本揭露的一些實施例，導電晶種層40包括諸如鈦層的第一金屬層(未示出)，以及第一金屬層上諸如銅層的第二金屬層(未示出)。根據本揭露的另外實施例，導電晶種層40包括單個金屬層，例如銅層，其可以由基本上為純銅或銅合金 形成。
圖4至7示出貫穿通路的形成。如圖4所示，圖案化遮罩層42(如光阻)施加在導電晶種層40之上，然後，使用光微影遮罩進行圖案化。相應的步驟如圖23的處理流程中的步驟208所示。根據本揭露一些實施例，光阻42是乾膜，其層壓到導電晶種層40上。根據可替代的實施實施例，光阻42藉由旋塗形成。作為圖案化(曝光和顯影)的結果，開口44在光阻42中形成，導電晶種層40的某些部分透過開口44被暴露。光阻42的厚度由隨後放置的元件晶粒48(圖8)的厚度決定。根據本揭露的一些實施例，光阻42大於元件晶粒48的厚度。
如圖5中所示，貫穿通路46在開口44中藉由鍍覆形成，其可以是電鍍或者無電式電鍍。相應的步驟如23的處理流程中的步驟210所示。貫穿通路46被鍍在導電晶種層40的暴露部分。貫穿通路46導電，並且可以是包括銅，鋁，鎢，鎳，或者它們的合金的金屬通路。貫穿通路46的俯視圖形狀包括但並不限於，矩形，正方形，圓形，和類似物。貫穿通路46的高度由隨後放置的元件晶粒48(圖8)的厚度決定，根據本揭露的一些實施例，貫穿通路46的高度略微大於或等於設備晶粒48的厚度。
鍍覆貫穿通路46後，光阻42被除去，並且所產生的結構如圖6所示。相應的步驟如圖23的處理流程中的步驟212所示。這樣，導電晶種層40之前被光阻42覆蓋的部分被暴露。
接著，如圖7中所示，進行蝕刻步驟以去除導電晶種層40的暴露部分，其中該蝕刻可以是非等向性或等向性蝕刻。相應的步驟也如圖23的處理流程中的步驟212所示。另一方面，貫穿通路46所覆蓋的導電晶種層40的部分仍然不被蝕刻。在整個描述中，導電晶種層40下面的剩餘部分被稱為貫穿通路46的底部部分。雖然導電晶種層40被示為與貫穿通路46的上覆部分具有可區分的交界面，當形成導電晶種層40 的材料與各自上面覆蓋的貫穿通路46的材料相似或相同時，一些或所有導電晶種層40可以與貫穿通路46合併，它們之間沒有可區分的交界面。例如，導電晶種層40中的銅層可以與貫穿通路46合併，而沒有可區分的交界面。根據可替代的實施例，導電晶種層40和各自上面覆蓋的貫穿通路46的鍍覆部分之間存在可區分的交界面。例如，導電晶種層40中的鈦層可以與含銅的貫穿通路46區分。蝕刻導電晶種層40的結果是，介電層34被暴露。
圖8示出元件晶粒48放置在介電層34之上。相應的步驟如圖23的處理流程中的步驟214所示。元件晶粒48可以藉由晶粒附接膜50黏附到黏合層32。晶粒附接膜50的邊緣與各自元件晶粒48的邊緣相鄰(對齊)。晶粒附接膜50是黏合膜。所放置的兩個以上的元件晶粒48可被佈置為包括多行和多列的陣列。每個元件晶粒48可以包括半導體基板，其背面(表面朝下)與各自覆蓋的晶粒附接膜50物理接觸。元件晶粒48進一步在半導體基板的前表面(表面朝上)包括積體電路元件(比如有源元件，其包括例如電晶體，未示出)。元件晶粒48可包括邏輯晶粒，如中央處理單元(Central Processing Unit,CPU)晶粒，圖形處理單元(Graphic Processing Unit,GPU)晶粒，移動應用晶粒，或類似物。
元件晶粒48可在其頂面包括金屬柱54。金屬柱54被電耦合到元件晶粒48內部的積體電路。根據本揭露的一些示例性實施例，如圖8所示，金屬柱54被介電層51覆蓋，介電層51的頂面比金屬柱54的頂面高。介電層51進一步延伸到金屬柱54之間的間隙。根據本揭露的一些實施例，金屬柱54的頂面與各自介電層51的頂面共面。根據一些示例性實施例，介電層51可由諸如PBO的聚合物形成。金屬柱54可以是銅柱，並且還可以包括其它導電/金屬材料，如鋁，鎳或類似物。
參考圖9，封裝材料52在元件晶粒48和貫穿通路46上封裝/成型。 相應的步驟如圖23的處理流程中的步驟216所示。封裝材料52填充元件晶片和貫穿通路46之間的間隙，並且可以與介電層34接觸。封裝材料52可包括模塑料，模底膠填充，環氧樹脂，或樹脂。在封裝處理之後，封裝材料52的頂表面高於金屬柱54和貫穿通路46的頂端。
接著，進行諸如化學機械拋光(Chemical Mechanical Polish,CMP)步驟或研磨步驟的平坦化步驟以平整封裝材料52，直到貫穿通路46暴露。相應的步驟也如圖23的處理流程中的步驟216所示。所得到的結構示於圖10。元件晶粒48的金屬柱54由於平坦化也被暴露。由於平坦化，貫穿通路46的頂面基本與金屬柱54的頂面實質上齊平(共面)，並且實質上與封裝材料52的頂面齊平(共面)。
參考圖11，介電層56的一個或兩個以上層和相應的重佈線(redistribution line,RDL)58在封裝材料52、貫穿通路46和金屬柱54上形成。相應的步驟如圖23的處理流程中的步驟218所示。RDL 58由於在元件晶粒48的正面而被稱為正面RDL。根據本揭露的一些實施例，介電層56由聚合物形成，例如PBO，聚醯亞胺，或類似物。根據本揭露可替代的實施例，介電層56由無機介電材料形成，例如氮化矽，氧化矽，氮氧化矽，或類似材料。
RDL 58被形成以電耦合到金屬柱54和貫穿通路46。RDL 58也可將金屬柱54和貫穿通路46彼此互連。RDL 58可以包括金屬佈線(金屬線)和下面連接到金屬佈線的通路。根據本揭露的一些實施例，RDL 58藉由電鍍製程形成，其中每個RDL 58包括晶種層(未示出)和在晶種層上的鍍覆金屬材料。所述晶種層和所述電鍍金屬材料可由相同的材料或不同的材料製成。
圖12根據本揭露一些示例性實施例示出電連接器60的形成。電連接器60電耦合到RDL 58，金屬柱54，和/或貫穿通路46。電連接器60的形成可包括將焊球放置在RDL 58之上，然後回銲焊球。根據本 揭露的可替代實施例，電連接器60的形成包括執行鍍覆步驟，以在RDL 58上形成焊接區，接著回銲焊接區。電連接器60還可以包括金屬柱，或者金屬柱和焊帽，其也可以藉由鍍覆形成。在整個說明書中，包括元件晶粒48，貫穿通路46，封裝材料52，RDL 58以及介電層56的組合結構將被稱為晶圓級封裝62，其是包括兩個以上元件晶粒48的複合晶圓。
圖12示出兩個RDL層58。根據本揭露可替代的實施例，根據相應封裝的佈線需求，可以是單個RDL層58或複數個RDL層58。按照本揭露的另一可替代實施例，不存在RDL，並且在貫穿通路46和金屬柱54之上直接形成電連接器60，在金屬連接器60和下面的貫穿通路46以及金屬柱54之間不形成RDL。
參考圖13，晶圓級封裝62包括兩個以上封裝162，每個都包括一個或複數個元件晶粒48和兩個以上貫穿通路46。封裝162彼此隔開，相鄰封裝162之間的空間(和填充空間的材料)被稱為切割道163。圖15B示出了晶圓級封裝62的俯視圖，其中封裝162被佈置為包括兩個以上的行和列的陣列，第一切割道163在X方向延伸，第二切割道163在Y方向延伸。
復參照圖13，進行第一晶粒切割。根據本揭露的一些實施例，使用刀片164執行第一晶粒切割，所述刀片164在切割過程中旋轉。相應的步驟如圖23的處理流程中的步驟220所示。根據本揭露的一些實施例，第一晶粒切割使用雷射進行。刀片164的寬度W1相對較小。例如，寬度W1可以是在介於約35微米與約50微米的範圍內。較薄刀片164具有在晶粒切割中減少介電層56剝落(peeling)的有利特徵，其剝落狀況可能發生在介電層56和封裝材料52之間的交界面。第一晶粒切割導致位於封裝材料52之上的介電層56被切割開。此外，第一晶粒切割在封裝材料52的中間層停止。第一晶粒切割導致產生溝槽166，如 圖14所示。所得溝槽166的深度D1(圖14)可以在約30微米和約80微米之間的範圍內。
切割道163具有中線168，其到封裝162的相對側具有相同距離。根據本揭露一些示例性的實施例，溝槽166可以在中線168的一側，並且不延伸到中線168。
參考圖14，執行第二晶粒切割，形成溝槽170(圖15A)。相應的步驟也如圖23的處理流程中的步驟220所示。也使用相對薄的刀片執行第二晶粒切割，例如，用於第一晶粒切割的相同刀片164。第二晶粒切割也在進行第一晶粒切割的相同切割道163上進行。此外，第一晶粒切割和第二晶粒切割可在中線168的相對側執行。第一晶粒切割和第二晶粒切割可以中線168呈現鏡像對稱。例如，第二晶粒切割產生的溝槽170(圖15A)的深度與溝槽166的深度D1相同。
圖15A和15B分別示出在每個切割道163上執行兩個晶粒切割之後，晶圓級封裝62部分剖面圖和俯視圖。如圖15A所示，在溝槽166和170之間的介電層56的部分與封裝162中介電層56的部分完全分離。參考圖15B，對於晶圓級封裝62，執行兩個以上的晶粒切割(每個類似於第一或第二晶粒切割)。每個水平切割道163(在X方向延伸)被切割兩次，且每個垂直切割道163(在Y方向延伸)也被切割兩次。
接著，封裝62從載體30(圖15A)剝離(de-bond)。根據一些示例性的剝離處理，切割膠帶64附接至封装62(圖16)，以保護電連接器60，其中切割膠帶64被固定到切割架(未示出)。相應步驟如圖23的處理流程中的步驟222所示。例如，藉由在黏合層32(圖15A)投射UV光或雷射執行剝離。例如，當黏合層32藉由光熱轉換形成時，從所述光或雷射生成的熱引起光熱轉換而被分解，因此載體30從晶圓級封裝62分離。所得結構示於圖16。
圖17示出在介電層34中形成開口63的圖案化。相應步驟如圖23 的處理流程中的步驟224所示。例如，當介電層34是聚合物層時，可以使用雷射鑽(藉由雷射光束65)圖案化以除去覆蓋貫穿通路46的部分，使得貫穿通路46透過開口63暴露。
在導電晶種層40的一部分是由鈦製成的實施例中，導電晶種層40的鈦層也可以被除去。例如，氟化氫(HF)氣體或稀釋的HF溶液可以用於蝕刻鈦。導電晶種層40中的銅被暴露，因此隨後形成的背側RDL或諸如焊接區的電連接器可以在其上形成。
根據本揭露的一些實施例，此時(在晶粒切割之前)沒有焊接區在封裝62的背側形成。此外，沒有背側RDL形成。根據本揭露的替代實施例，背側RDL(未示出)和/或所述電連接器在元件晶粒48的背側(圖15A所示的頂側圖)形成，背側RDL電耦合至貫穿通路46。根據本揭露示例性的一些實施例，存在單一的背側RDL層。根據一些實施例，存在兩個以上的RDL層，其中通路形成以互連在不同RDL層中的不同金屬佈線。背面介電層由諸如PBO，BCB，聚醯亞胺的聚合物，或諸如氧化矽，氮化矽，氮氧化矽的無機材料，或類似物形成。可以形成諸如焊接區，具有焊帽的金屬柱或其類似物的電連接器。
在隨後的步驟中，如圖18A所示，封裝62被分割成兩個以上的封裝162，每一個包括(至少)一個元件晶粒48的和相應的貫穿通路46。相應步驟如圖23的處理流程中的步驟226所示。例如，如圖18A所示，使用刀片172執行第三晶粒切割。第三晶粒切割從晶圓級封裝62相對第一和第二晶粒切割的一側進行。刀片172比第一和第二晶粒切割中使用的刀片164(如圖13和14)更寬。刀片172的寬度W2可以在介於約180微米與約220微米的範圍。根據一些實施例，W2/W1之比大於2，並可以大於3或4。由於第三晶粒切割的刀片比第一和第二晶粒切割的更寬，由第三晶粒切割所產生的溝槽比由第一和第二晶粒切割的溝槽也更寬。在所述第三晶粒切割之後，所示切割道163左側的 封裝162被完全與所示切割道163右側的封裝162分離。所述第三晶粒切割對準切割道163的中線168。
兩個以上類似於圖18A所示的第三晶粒切割在晶圓級封裝62上進行，且每個晶粒切割在切割道163(圖15B)中的一者上進行，使得晶圓級封裝62被分離成兩個以上的封裝162。
圖18B示出第三晶粒切割未對準切割道163中心的情景。因此，介電層56剩餘部分的一部分可以在第三晶粒切割後留下。
圖19示出在第三晶粒切割後所得到的晶圓級封裝62，其產生溝槽174。溝槽174與溝槽166和170相接。有利的是，由於切割道163中心區域的介電層56的(中心)部分已經從封裝162的介電層56的部分分離，即使介電層56的中心部分在第三晶粒切割期間從封裝材料52剝落，這種剝落將停在溝槽166和170，因此將不會有晶粒切割引致的剝落蔓延到封裝162。
圖20示出封裝162的剖面圖。圖21A示出封裝300接合至到封裝162，從而形成PoP封裝20。相應步驟如圖23的處理流程中的步驟228所示。封裝300和162也分別被稱為PoP封裝20的頂部封裝和底部封裝。在如圖21A所示的示例性實施例中，沒有示出背側RDL，而背側RDL可以根據本揭露可替代的實施例形成。接合可藉由焊接區70進行，所述焊接區70連接貫穿通路46至上方的封裝300中的金屬墊。根據本揭露的一些實施例，封裝300包括(多個)元件晶粒304，其可以是記憶體晶粒，如靜態隨機存取記憶體(Static Random Access Memory,SRAM)晶粒、動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)晶粒等。所述記憶體晶粒在一些示例性實施例中還可以接合到封裝基板302。頂部封裝300接合到底封裝162後，底膠填充72放置在頂部封裝300和底部封裝162之間的間隙，然後被固化。
如圖21A所示，底部封裝162包括封裝材料52，其具有邊緣52A。根據一些示例性實施例，邊緣52A是直線邊緣，其垂直於封裝162的主頂面162C。封裝材料52還可以包括邊緣52B，其是傾斜的邊緣，既不平行也不垂直於封裝162的主頂面162C。直線邊緣52A可具有介於約120微米至約220微米範圍內的長度D3。長度D3還可以與被溝槽66和170(圖15A)所覆蓋的封裝材料52的部分的厚度相同。介電層56具有邊緣52A，其可以是垂直於封裝162的主頂面162C的直線邊緣，或者可以是既不垂直也不平行於封裝162主頂面162C的傾斜邊緣。邊緣52A通過邊緣52B連接到邊緣56A以形成階梯(圖21A中上下顛倒的階梯)。封裝162具有在封裝材料52的部分(例如頂面)處測量的寬度W3，和在介電層56底面測量的寬度W4。寬度W4大於寬度W3。另外，從直線邊緣52A的底端到邊緣56A的底端，封裝162的寬度可以連續地逐漸降低，造成錐形(tapered)封裝162。
進一步參考圖21A，根據本揭露的一些實施例，邊緣56A是具有傾斜角α的傾斜和直線邊緣，所述傾斜角α可以在包括0度和大約30度之間的範圍內。當傾斜角度α為0度時，邊緣56A垂直於主表面162C。封裝材料52的邊緣52B是傾斜的邊緣，其可以是具有傾斜角β的直線邊緣，所述傾斜角β在包括大約30度和大約60度之間的範圍內。或者，邊緣52B是彎曲邊緣，且彎曲邊緣的不同部分具有在大約30度和大約60度之間範圍內不同的傾斜角。在這些實施例中，彎曲邊緣的上部可以比下部具有更大的傾斜角，並且從上部到下部，傾斜角可以連續地逐漸減小。邊緣52A，52B，和56A被刀片的形狀限定。
圖21B示出當第三晶粒切割未對準切割道163的中心時形成的封裝20。因此，在第三晶粒切割後，溝槽166和170之間的介電層56的中心部分保留在封裝162中的一者上。介電層56所保留的部分位於直線邊緣52A和溝槽66之間。當從封裝20的仰視圖觀察時，溝槽66平行於 邊緣52A。此外，在這些實施例中，邊緣52A可從封裝162的頂面一直延伸到底面。應該認識到，每個封裝162的邊緣可以具有圖21A或21B中所示形狀的任意組合。
圖22示出根據本揭露一些實施例形成的溝槽67，其中圖13和14所示的步驟被形成溝槽67代替。這些實施例類似於圖13和14中所示的實施例，除了窄溝槽67形成以包圍封裝162。窄溝槽67可以使用雷射形成。窄溝槽67形成後，進行如圖16至21A/21B所示的步驟。所得結構類似於圖21A和21B中所示的結構。然而，由於雷射的使用，溝槽67的邊緣可以是粗糙的。
本揭露的實施例有一些有利特徵。在傳統的晶粒切割過程中，使用單個寬刀片。因此，由聚合物形成的介電層56(圖19)很容易從封裝材料上剝落。在本揭露的一些實施例中，使用薄刀片的晶粒切割顯著降低了剝落狀況。在隨後使用寬刀片的晶粒切割中，使用薄刀片形成的溝槽阻止其剝落狀況蔓延至封裝。
以上概述了幾個實施例的特徵，使得本領域熟練的技術人員可以更好地理解本揭露的各個方面。本領域熟練的技術人員應當理解，他們可以容易地使用本揭露作為基礎，用於設計或修改其他過程或步驟，以實現相同目的和/或實現本文所介紹實施例的相同優點。那些熟練的技術人員也應該認識到，這樣的等效構造不偏離本揭露的精神和範圍，並且它們可以在此不脫離本揭露的精神和範圍的前提下進行各種改變，替換以及變更。

Claims (9)

  1. 一種半導體元件的製造方法，其包括：將第一元件晶粒和第二元件晶粒放置在載體之上，且該第一元件晶粒和該第二元件晶粒之間具有切割道；使用封裝材料封裝該第一元件晶粒和該第二元件晶粒，其中該封裝材料包括該切割道中的部分；在該封裝材料之上形成介電層；進行第一晶粒切割以在該切割道中形成第一溝槽；進行第二晶粒切割以在該切割道中形成第二溝槽；以及在該切割道上進行第三晶粒切割以將該第一元件晶粒與該第二元件晶粒分離。
  2. 如請求項1所述的製造方法，其中，該第一溝槽和該第二溝槽彼此隔開，並且該第三晶粒切割在該第一溝槽和該第二溝槽之間的切割道部分進行。
  3. 如請求項1所述的製造方法，其中，執行該第一晶粒切割和該第二晶粒切割所使用的刀片比用於該第三晶粒切割的刀片窄。
  4. 如請求項1所述的製造方法，其中，該第一溝槽和該第二溝槽穿透該介電層，並在該封裝材料的中間層停止。
  5. 如請求項1所述的製造方法，還包括該第一元件晶粒和該第二元件晶粒從載體上剝離，其中進行該第一晶粒切割和該第二晶粒切割的方向與進行該第三晶粒切割的方向相反。
  6. 如請求項1所述的製造方法，其中，由該第三晶粒切割形成的第三溝槽連接到該第一溝槽。
  7. 一種半導體元件的製造方法，其包括：將第一元件晶粒和第二元件晶粒放置在載體之上，且該第一元件晶粒和該第二元件晶粒之間具有切割道；使用封裝材料封裝該第一元件晶粒和該第二元件晶粒，其中該封裝材料包括該切割道中的部分；在該封裝材料上形成聚合物層，其中該聚合物層包括該切割道中的部分；進行第一晶粒切割以在該切割道中形成第一溝槽，其中該第一晶粒切割使用第一刀片；以及進行第二晶粒切割以在該切割道中形成第二溝槽，其中該第二晶粒切割使用比該第一刀片更寬的第二刀片進行。
  8. 一種半導體元件，包括：封裝，該封裝包括：元件晶粒；封裝材料，其包圍該元件晶粒，其中該封裝材料具有第一邊緣，其實質上垂直於該封裝材料的主頂面；以及聚合物層，其位於該封裝材料之下，其中該聚合物層包含：一頂部表面，其與該封裝材料的一底部表面相接觸；一第二邊緣，其中該第二邊緣位於該元件晶粒與該第一邊緣的相同側，其中該第一邊緣與該第二邊緣分別為該封裝之一邊緣的第一部分與第二部分，以及其中該第二邊緣從該第一邊緣朝該元件晶粒凹陷，其中該第二邊緣具有一第一傾斜角，該第一傾斜角是以該封裝的一垂直邊緣為基準，該封裝的該垂直邊緣垂直於該封裝材料的一主要頂部表面；及一第三邊緣，其連接該第一邊緣至該第二邊緣，其中該第三邊緣既未垂直也未平行該第一邊緣，及該第三邊緣具有一第二傾斜角，該第二傾斜角大於該第一傾斜角，及該第二傾斜角是以該封裝的該垂直邊緣為基準。
  9. 如請求項8所述的半導體元件，其中，該封裝還包括第四邊緣，該第四邊緣為從該封裝的頂面延伸到底面的直線，該第一邊緣和該第四邊緣是該封裝的不同邊緣，並且其中該封裝還包括溝槽，其穿透該聚合物層且延伸到該封裝材料的中間層，並且該溝槽鄰近並平行於該第四邊緣。
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