JPH05144982A - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JPH05144982A
JPH05144982A JP3303445A JP30344591A JPH05144982A JP H05144982 A JPH05144982 A JP H05144982A JP 3303445 A JP3303445 A JP 3303445A JP 30344591 A JP30344591 A JP 30344591A JP H05144982 A JPH05144982 A JP H05144982A
Authority
JP
Japan
Prior art keywords
chip
resin
package
angled portions
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3303445A
Other languages
English (en)
Inventor
Kazuhiro Matsumoto
一裕 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Precision Circuits Inc
Original Assignee
Nippon Precision Circuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Precision Circuits Inc filed Critical Nippon Precision Circuits Inc
Priority to JP3303445A priority Critical patent/JPH05144982A/ja
Priority to US07/970,366 priority patent/US5309026A/en
Publication of JPH05144982A publication Critical patent/JPH05144982A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】 パッケージクラックの防止およびＩＣチップ
への応力集中を緩和する集積回路装置を提供することで
ある。 【構成】 凹部３〜３を少なくともＩＣチップ２の角部
に対応した位置に形成してＩＣチップ２の角部に生じる
応力集中を緩和する。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、ＩＣチップを樹脂でモ
ールドしてある集積回路装置に関するものである。
【０００２】
【従来の技術】従来のＩＣチップを樹脂でモールドした
集積回路装置は、図１０で示すような構成である。
【０００３】
【発明が解決しようとする課題】上記の集積回路装置で
は、モールドする樹脂がＩＣチップやリードフレーム材
料に比べ約１０倍大きい線膨脹係数をもっている。この
ため、一般的に１７０℃前後で行なわれるモールド工程
時と室温に冷却したときの温度差により、収縮率の大き
い樹脂に図１１の矢印で示したような歪みが発生し、Ｉ
Ｃチップの角部に応力集中が生じることによりパッケー
ジクラックやパッシベーションクラックなどの不都合が
生じてしまう。
【０００４】本発明の目的は、パッケージクラックの防
止およびＩＣチップへの応力集中を緩和することであ
る。
【０００５】
【課題を解決するための手段】本発明では、樹脂による
パッケージの表面および／または裏面の、少なくともＩ
Ｃチップの角部に対応した位置に凹部を形成することに
より上記目的を達成している。
【０００６】
【実施例】以下、図面に示す一実施例に基づいて説明す
る。
【０００７】図１において、１はパッケージであり、エ
ポキシ樹脂等の樹脂などにより形成し、図２で示すよう
にＩＣチップ２などをモールドする。３〜３は凹部であ
り、図２で示すように、少なくともＩＣチップ２の角部
に対応した位置に形成してあり、深さは０．１ｍｍ〜
２．０ｍｍ、幅は０．１ｍｍ〜２．０ｍｍ程度とするこ
とが望ましい。４はリードフレーム、５，５はボンディ
ングワイヤである。
【０００８】上記のように凹部３〜３をＩＣチップ２の
少なくとも角部に形成することにより、ＩＣチップ２の
角部に生じる応力集中を緩和することができる。
【０００９】なお、凹部３〜３は図１で示した形状に限
らず、図３のように円状に形成した溝を連ねることによ
り構成してもよく、また、図４、５、６に示したように
構成してもよい。また、上記のような形状以外のもので
も同様の効果が得られる。
【００１０】また、凹部３を形成する位置も図１に限ら
ず、図７〜９のように少なくともＩＣチップの角部に対
応する位置に形成してあれば、上記以外の位置に形成し
てもよい。
【００１１】また、上記の凹部３は裏面に形成してもよ
く、表面、裏面の双方に形成しても同様な効果が得られ
る。
【００１２】
【発明の効果】本発明は、樹脂によるパッケージの表面
および／または裏面の少なくともＩＣチップの角部に対
応した位置に凹部を形成することにより、ＩＣチップや
リードフレーム材料と樹脂との収縮率の違いにより生じ
るＩＣチップの角部に発生する応力集中を緩和すること
ができ、これによりＩＣチップやリードフレームおよび
ボンディングワイヤなどの破損やパッケージクラックや
パッシベーションクラックなどを防止することができ
る。
【図面の簡単な説明】
【図１】本発明の一実施例の斜視図。
【図２】図１のＡ−Ａ線断面図。
【図３】図１の凹部の他の実施例を示した図。
【図４】図１の凹部の他の実施例を示した図。
【図５】図１の凹部の他の実施例を示した図。
【図６】図１の凹部の他の実施例を示した図。
【図７】本発明の他の実施例を示した上面図。
【図８】本発明のさらに他の実施例を示した上面図。
【図９】本発明のさらに他の実施例を示した上面図。
【図１０】従来の集積回路装置の斜視図。
【図１１】図１０のＢ−Ｂ線断面図。
【符号の説明】
２ ＩＣチップ ３ 凹部

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 ＩＣチップを樹脂でモールドした集積回
    路装置において、上記樹脂によるパッケージの表面およ
    び／または裏面の、少なくとも上記ＩＣチップの角部に
    対応した位置に凹部を形成したことを特徴とする集積回
    路装置。
JP3303445A 1991-11-19 1991-11-19 集積回路装置 Withdrawn JPH05144982A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3303445A JPH05144982A (ja) 1991-11-19 1991-11-19 集積回路装置
US07/970,366 US5309026A (en) 1991-11-19 1992-11-02 Integrated circuit package having stress reducing recesses

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3303445A JPH05144982A (ja) 1991-11-19 1991-11-19 集積回路装置

Publications (1)

Publication Number Publication Date
JPH05144982A true JPH05144982A (ja) 1993-06-11

Family

ID=17921082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3303445A Withdrawn JPH05144982A (ja) 1991-11-19 1991-11-19 集積回路装置

Country Status (2)

Country Link
US (1) US5309026A (ja)
JP (1) JPH05144982A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6316829B1 (en) * 1998-06-18 2001-11-13 Texas Instruments Incorporated Reinforced semiconductor package
JP2017157672A (ja) * 2016-03-01 2017-09-07 株式会社デンソー 回路装置
EP4276896A4 (en) * 2021-02-24 2024-07-03 Huawei Tech Co Ltd CHIP ENCAPSULATING STRUCTURE AND ELECTRONIC DEVICE

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766325A (ja) * 1993-08-26 1995-03-10 Rohm Co Ltd 合成樹脂パッケージ型電子部品の構造
US5604376A (en) * 1994-06-30 1997-02-18 Digital Equipment Corporation Paddleless molded plastic semiconductor chip package
JP3294740B2 (ja) * 1995-07-31 2002-06-24 富士通株式会社 半導体装置
DE19534607C2 (de) * 1995-09-18 2002-02-07 Eupec Gmbh & Co Kg Gehäuse mit Leistungs-Halbleiterbauelementen
US6373088B2 (en) 1997-06-16 2002-04-16 Texas Instruments Incorporated Edge stress reduction by noncoincident layers
US6589820B1 (en) 2000-06-16 2003-07-08 Micron Technology, Inc. Method and apparatus for packaging a microelectronic die
US6483044B1 (en) * 2000-08-23 2002-11-19 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6979595B1 (en) * 2000-08-24 2005-12-27 Micron Technology, Inc. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices
US6838760B1 (en) * 2000-08-28 2005-01-04 Micron Technology, Inc. Packaged microelectronic devices with interconnecting units
JP2002110718A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 半導体装置の製造方法
US6570259B2 (en) 2001-03-22 2003-05-27 International Business Machines Corporation Apparatus to reduce thermal fatigue stress on flip chip solder connections
US20050133913A1 (en) * 2003-12-17 2005-06-23 Dan Okamoto Stress distribution package
US20060076694A1 (en) * 2004-10-13 2006-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package with concavity-containing encapsulation body to prevent device delamination and increase thermal-transferring efficiency
US20060261498A1 (en) * 2005-05-17 2006-11-23 Micron Technology, Inc. Methods and apparatuses for encapsulating microelectronic devices
US7615861B2 (en) * 2006-03-13 2009-11-10 Sandisk Corporation Methods of promoting adhesion between transfer molded IC packages and injection molded plastics for creating over-molded memory cards
US8304874B2 (en) * 2006-12-09 2012-11-06 Stats Chippac Ltd. Stackable integrated circuit package system
US7772683B2 (en) * 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7635913B2 (en) * 2006-12-09 2009-12-22 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7833456B2 (en) * 2007-02-23 2010-11-16 Micron Technology, Inc. Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece
US8008787B2 (en) * 2007-09-18 2011-08-30 Stats Chippac Ltd. Integrated circuit package system with delamination prevention structure
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US8183095B2 (en) * 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US8378476B2 (en) * 2010-03-25 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with stacking option and method of manufacture thereof
US8901755B2 (en) * 2012-03-20 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming conductive layer over metal substrate for electrical interconnect of semiconductor die
US9472481B2 (en) * 2014-02-07 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with stress-reducing structures and methods of forming same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827347A (ja) * 1981-08-12 1983-02-18 Hitachi Ltd 半導体装置
IT1201836B (it) * 1986-07-17 1989-02-02 Sgs Microelettronica Spa Dispositivo a semiconduttore montato in un contenitore segmentato altamente flessibile e fornite di dissipatore termico
US4855807A (en) * 1986-12-26 1989-08-08 Kabushiki Kaisha Toshiba Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6316829B1 (en) * 1998-06-18 2001-11-13 Texas Instruments Incorporated Reinforced semiconductor package
JP2017157672A (ja) * 2016-03-01 2017-09-07 株式会社デンソー 回路装置
EP4276896A4 (en) * 2021-02-24 2024-07-03 Huawei Tech Co Ltd CHIP ENCAPSULATING STRUCTURE AND ELECTRONIC DEVICE

Also Published As

Publication number Publication date
US5309026A (en) 1994-05-03

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