TWI584423B - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

Info

Publication number
TWI584423B
TWI584423B TW104137132A TW104137132A TWI584423B TW I584423 B TWI584423 B TW I584423B TW 104137132 A TW104137132 A TW 104137132A TW 104137132 A TW104137132 A TW 104137132A TW I584423 B TWI584423 B TW I584423B
Authority
TW
Taiwan
Prior art keywords
polymer layer
package
layer
top surface
die
Prior art date
Application number
TW104137132A
Other languages
English (en)
Other versions
TW201642408A (en
Inventor
陳潔
陳憲偉
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201642408A publication Critical patent/TW201642408A/zh
Application granted granted Critical
Publication of TWI584423B publication Critical patent/TWI584423B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

半導體封裝及其形成方法
本揭露係關於經由形成溝槽而消除切割導致的剝落。
隨著半導體技術的演進，半導體晶片/晶粒變得越來越小。同時，半導體晶粒上需要整合越來越多的功能。因此，半導體晶粒需要在較小的面積上封裝越來越多數目的輸出入接墊，並且輸出入接墊的密度隨著時間快速增加。因此，半導體晶粒的封裝變得越加困難，進而不利地影響封裝產量。
習知的封裝技術可分為兩類。在第一類中，晶圓上的晶粒在切割之前先進行封裝。此封裝技術具有一些優點特徵，例如較大的生產量與較低成本。再者，此技術所需的底膠填充或是模塑料較少。然而，此封裝技術亦有缺點。由於晶粒的尺寸越來越小，因而其相對應的封裝可僅為扇入型封裝(fan-in type package)，其中各晶粒的輸出入接墊被直接侷限在個別晶粒之表面上方的區域。由於晶粒面積有限，輸出入接墊的數目因輸出入接墊間隔的限制而受到侷限。如果墊的間距減少，可能會產生銲橋(solder bridge)現象。此外，在將銲球尺寸固定的需求之下，銲球必具有某種尺寸，其因而限制了在晶粒表面上可封裝的銲球數目。
在另一類封裝中，晶粒在封裝之前進行切割。此封裝 技術的優點特徵在於可形成扇出封裝(fan-out package)，其係指晶粒上的輸出入接墊可分布至比晶粒更大的面積，因而可增加晶粒表面上封裝的輸出入接墊數目。此封裝技術的另一優點特徵係封裝「已知的良好晶粒」，並且捨棄有缺陷的晶粒，因而不會浪費成本與氣力在有缺陷的晶粒上。
本揭露的一些實施例係提供一種封裝，其包括：元件晶粒；成型材料，其包圍該元件晶粒，其中該成型材料的頂部表面係與該元件晶粒的頂部表面實質齊平；底部介電層，其係位於該元件晶粒與該成型材料上方；複數個重佈線(RDL)，其係延伸至該底部介電層中並且電性耦合至該元件晶粒；頂部聚合物層，其位於底部介電層上方，溝槽環係穿過該頂部聚合物層，其中該溝槽環係與該封裝的邊緣相鄰；以及凸塊下金屬層(UBM)，其係延伸至該頂部聚合物層中。
本揭露的一些實施例係提供一種封裝，其包括元件晶粒；成型材料，其包圍該元件晶粒，其中該成型材料的頂部表面係與該元件晶粒的頂部表面實質齊平；貫穿通路，其係穿過該成型材料，其中該貫穿通路的頂部表面係與該元件晶粒的該頂部表面實質共平面；第一聚合物層，其係位於該元件晶粒、該貫穿通路與該成型材料上方，並且接觸該元件晶粒、該貫穿通路與該成型材料；複數個重佈線(RDL)，其係延伸至該第一聚合物層中，以電性耦合至該元件晶粒與該貫穿通路；第二聚合物層，其係位於該第一聚合物層與該複數個RDL上方，其中第一溝槽環系從該第二聚合物層的頂部表面延伸至該第一聚合物層的頂部表面；第三聚合物層，其係位於該第三聚合物層上方並且接觸該第三聚合物層，其中第二溝槽環係從該第三聚合物層的頂部表面延伸至該第二聚合物層的頂部表面；以及凸塊下金屬層(UBM)，其係延伸至該第三聚合物層中。
本揭露的一些實施例係提供一種方法，其包括在成型材料中，成型複數個元件晶粒；平坦化該複數個元件晶粒與該成型材料，其中該元件晶粒的頂部表面係與該成型材料的頂部表面齊平；形成第一聚合物層，其係位於該複數個元件晶粒與該成型材料上方，並且接觸該複數個元件晶粒與該成型材料；圖案化該第一聚合物層，以形成第一複數個開口，該元件晶粒的金屬柱係經由該第一複數個開口而暴露，其中藉由圖案化該第一聚合物層而形成切割線；形成複數個重佈線，其包括穿過該第一聚合物層的通路部分；形成第二聚合物層，其係位於該第一聚合物層上方；以及圖案化該第二聚合物層，以形成第二複數個開口與第一複數個溝槽環，該第一複數個溝槽環各自包圍該複數個元件晶粒之一，並且該第一複數個溝槽環係藉由該切割線而彼此分離；以及形成複數個凸塊下金屬層(UBM)，其係延伸至該第二聚合物層中。
20‧‧‧載體
22‧‧‧釋放層
24‧‧‧介電層
26‧‧‧重佈線(RDL)
36‧‧‧元件晶粒
28‧‧‧介電層
30‧‧‧開口
32‧‧‧貫穿通路
45‧‧‧晶粒附接膜(DAF)
40‧‧‧頂部介電層
44‧‧‧成型材料
46‧‧‧介電層
48‧‧‧光微影蝕刻遮罩
50‧‧‧開口
52‧‧‧切割線
54‧‧‧封裝
58‧‧‧重佈線
38‧‧‧金屬柱
60‧‧‧聚合物層
61‧‧‧光微影蝕刻遮罩
100‧‧‧複合封裝
64‧‧‧開口
60’‧‧‧殘留物
66‧‧‧重佈線
68‧‧‧聚合物層
70‧‧‧光微影蝕刻製程遮罩
72‧‧‧開口
74‧‧‧凸塊下金屬層(UBM)
76‧‧‧電連接物
67‧‧‧路徑
98‧‧‧銲區
200‧‧‧封裝
202‧‧‧元件晶粒
204‧‧‧封裝基板
64B、72B‧‧‧溝槽環
由以下詳細說明與附隨圖式得以最佳了解本揭露之各方面。注意，根據產業之標準實施方式，各種特徵並非依比例繪示。實際上，為了清楚討論，可任意增大或縮小各種特徵的尺寸。
圖1至16係根據一些實施例說明在製造封裝的中間階段之剖面圖與俯視圖。
圖17至20係根據其他實施例說明封裝的剖面圖。
圖21係根據一些實施例說明封裝的俯視圖。
圖22係根據一些實施例說明切割的封裝之俯視圖。
圖23係根據一些實施例說明形成封裝的製程流程。
以下揭示內容提供許多不同的實施例或範例，用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下，以簡化 本申請案之揭示內容。當然，這些僅為範例，並非用於限制本申請案。例如，以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施例，亦可包含在該第一與第二特徵之間形成其他特徵的實施例，因而該第一與第二特徵並非直接接觸。此外，本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的，而非支配不同實施例與/或所討論架構之間的關係。
再者，本申請案可使用空間相對用語，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似用語之簡單說明，以描述圖式中一元件或特徵與另一元件或特徵的關係。空間相對用語係用以包括除了裝置在圖式中描述的位向之外，還有在使用中或操作中之不同位向。該裝置或可被重新定位(旋轉90度或是其他位向)，並且可相應解釋本申請案使用的空間對應描述。
根據不同的例示實施例，本揭露提供封裝及其形成方法。本揭露係說明形成封裝的中間階段。本揭露討論實施例的變化。在本揭露之各種圖式與說明實施例中，相同的元件符號係用以代表相同的元件。
圖1至16係根據一些實施例說明形成封裝的中間階段之剖面圖。圖1至16所示之步驟亦說明於圖23所示的製程流程300中。在後續的討論中，圖1至16所示之製程步驟係如圖23中所說明之製程步驟。
圖1係說明載體20以及形成於載體20上的釋放層22。載體20可為玻璃載體、陶瓷載體、或類似物。載體20可具有圓形俯視形狀，並且可具有矽晶圓的尺寸。例如，載體20可具有8吋直徑、12吋直徑、或類似者。釋放層22可由聚合物為基底的材料形成(例如光熱轉換(LTHC)材料)，可隨著載體20從後續步驟中所形成的上方結構 中移除。在一些實施例中，釋放層22係由環氧化合物為主的熱釋放材料而形成。在其他實施例中，釋放層22係由紫外線(UV)膠而形成。釋放層22可以液態方式施作並且加以硬化。在其他實施例中，釋放層22係壓層膜，並且被壓層在載體20上。釋放層22的頂部表面係平坦的，並且具有高度共平面性。
在釋放層22上，形成介電層24。根據本揭露的一些實施例，介電層24係由聚合物形成，其可為光敏材料，例如聚苯并噁唑(polybenzoxazole，PBO)、聚亞醯胺、或類似物，可使用光微影蝕刻製程而輕易將其圖案化。在其他實施例中，介電層24係由例如氮化矽之氮化物、例如氧化矽之氧化物、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)、或類似物而形成。
參閱圖2，在介電層24上方，形成重佈線(RDL)26。其相對步驟係如圖23之製成流程中的步驟310所示。由於RDL 26係位於元件晶粒36的背面上，因而亦稱為背面RDL(圖5)。RDL 26的形成可包含在介電層24上方形成晶種層(未繪示)，形成圖案化的遮罩(未繪示)，例如在晶種層上方的光阻，而後在暴露的晶種層上進行金屬電鍍。而後，移除圖案化遮罩以及圖案化遮罩覆蓋的部分之晶種層，留下圖2所示之RDL 26。根據一些實施例，晶種層包括鈦層以及在鈦層上方的銅層。例如，可使用物理氣相沉積(PVD)，形成晶種層。例如，可使用無電鍍(electro-less plating)，進行電鍍製程。
參閱圖3，在RDL 26上，形成介電層28。介電層28的底部表面係接觸RDL 26與介電層24的頂部表面。根據本揭露的一些實施例，介電層28係由聚合物形成，期可為光敏聚合物，例如PBO、聚亞醯胺、或類似物。在其他實施例中，介電層28係由例如氮化矽的氮化物、例如氧化矽的氧化物、PSG、BSG、BPSG、或類似物而形成。而後，將介電層28圖案化形成開口30。因此，經由介電層28中的 開口30，暴露RDL 26。
參閱圖4，形成金屬柱32。在本揭露的說明中，由於金屬柱32穿過後續形成的成型材料，因而亦稱為貫穿通路32。其對應步驟係如圖23之製程流程中的步驟312所示。根據本揭露的一些實施例，藉由電鍍形成貫穿通路32。貫穿通路32的電鍍步驟可包含在層28上方形成毯晶種層(未繪示)，延伸至開口30中(圖3)，形成且圖案化光阻(未繪示)，以及在經由光阻中的開口所暴露的部分晶種層上，電鍍貫穿通路32。而後，移除光阻以及光阻所覆蓋之部分晶種層。貫穿通路32的材料可包含銅、鋁、或類似物。貫穿通路32為桿狀形狀。貫穿通路的俯視形狀可為圓形、矩形、正方形、六角形、或類似形狀。
圖5係說明元件晶粒36的設置。其相對應步驟係如圖23之製程流程的步驟314所示。元件晶粒36係經由晶粒附接膜(DAF)而附貼至介電層28，DAF 45可為黏著膜。元件晶粒36可為邏輯元件晶粒，其包含邏輯電晶體於其中。在一些例示實施例中，元件晶粒36設計用於行動裝置的應用，並且可為功率管理積體電路(PMIC)、收發器(TRX)、或類似物。
在一些例示實施例中，預先形成金屬柱38(例如銅柱)成為元件晶粒36的最頂部部分，其中金屬柱38係電性耦合至積體電路裝置，例如元件晶粒36中的電晶體。根據本揭露的一些實施例，聚合物填充相鄰的金屬柱38之間的間隙，以形成頂部介電層40，其中頂部介電層40亦可在(可接觸也可不接觸)下方鈍化層的頂部上，該下方鈍化層可包括氮化矽、氮氧化矽、氧化矽、或其多層。根據一些例示實施例，聚合物層40可由PBO形成。
接著，如圖6所示，在元件晶粒36上，塑形成型材料44。其相對應步驟係如圖23之製程流程的步驟316所示。成型材料44係填充相鄰的貫穿通路32之間的間隙以及貫穿通路32與元件晶粒36之 間的間隙。成型材料44可包含模塑料、成型底膠填充、環氧化合物、或樹脂。成型材料44的頂部表面係高於金屬柱38的頂端。
再者，參閱圖6，進行平坦化，例如化學機械拋光(CMP)步驟或是研磨步驟，以薄化成型材料44，直到暴露貫穿通路32與金屬柱38。其相對應步驟係如圖23之製程流程中的步驟318所示。由於研磨之故，貫穿通路32的頂端係與金屬柱38的頂部表面實質齊平(共平面)，並且與成型材料44的頂部表面實質共平面。
參閱圖7，形成介電層46。其相對應步驟係如圖23之製程流程中的步驟320所示。根據本揭露的一些實施例，介電層46係由聚合物形成，根據本揭露的一些實施例，該聚合物亦可為光敏介電材料。例如，介電層46可由PBO、聚亞醯胺、或類似物。在其他實施例中，介電層46係由氮化物、氧化物、或類似物形成。在本揭露的說明中，介電層46亦可稱為底部內含RDL聚合物層。
參閱圖7，在光微影蝕刻製程中，圖案化介電層46。其相對應步驟係如圖23之製程流程中的步驟322所示。例如，在介電層46係由光敏材料所形成的實施例中，光微影蝕刻遮罩48係用於曝光。光微影蝕刻遮罩48係包含可使光通過的透明部分，以及阻光的不透光部分。而後，進行曝光，其中光(箭號)的投射係將光敏介電層46曝光。在顯影與烘烤製程之後，形成開口50，如圖8所示。
如圖8所示，經由開口50暴露貫穿通路32與金屬柱38。在後續的說明內容中，在釋放層22上方的結構部分，其包含晶粒36、貫穿通路32以及對應RDL(以及一些在後續步驟會形成的部分)，合稱為封裝100，其包含複數個封裝54。此外，切割線52係在封裝54之間，而底部內含RDL聚合物層46的邊緣係定義封裝54的邊界。切割線52係後續晶粒切割製程中切割刀將穿過的區域。據此，內含RDL聚合物層46不延伸至切割線52中，而是位於封裝54內。圖案化的結果是 在切割線52中暴露成型材料44。
圖21係說明封裝54與切割線52的俯視圖。如圖21所示，切割線52形成格狀圖案以分離封裝54。
接著，參閱圖9，形成重佈線(RDL)58以連接金屬柱38與貫穿通路32。RDL 58包含在介電層46上方的金屬導線(金屬線)以及延伸至開口50(圖8)中的通路，以電性連接貫穿通路32與金屬柱38。根據本揭露的一些實施例，在電鍍製程中形成RDL 58，其中各個RDL 58係包含晶種層(未繪示)以及在晶種層上方所鍍之金屬材料。晶種層與所鍍材料可由相同材料或不同材料所形成。RDL 58可包括金屬或是金屬合金，其包含鋁、銅、鎢、及其合金。在形成RDL 58之後，切割線52中的開口50(圖8)保持未被RDL 58填充。
參閱圖10，以例如經由旋塗方式，在RDL 58與介電層46上方，形成聚合物層60。其相對應步驟係如圖23之製程流程中的步驟326所示。聚合物層60可使用選自與介電層46相同的候選材料而形成。例如，聚合物層60可包括PBO、聚亞醯胺、或類似物。在形成之後，聚合物層60填充切割線52中的開口50(圖9)並且覆蓋RDL 58。
接著，亦如圖10所示，光微影蝕刻遮罩61係設置在複合封裝100上方。而後，進行曝光，其中光(箭號)投射係暴露聚合物層60。在顯影與烘烤製程之後，形成開口64(包含64A、64B與64C)，如圖11所示。其相對步驟係如圖23之製程流程的步驟328所示。經由開口64C暴露RDL 58的接墊部分，開口64C係封裝54中分離的開口。開口64B亦在封裝54中，並且從聚合物層60的頂部表面延伸至介電/聚合物層46的頂部表面，因而經由開口64B暴露介電層46。根據一些實施例，如圖21所示，開口64B形成接近切割線52的溝槽環，例如，開口64B與個別切割線52之間的距離係小於約100微米。再者，可形成開口64B，其包圍但不重疊個別封裝54中的個別晶粒36與傳導特徵。 換言之，根據本揭露的一些實施例，晶粒36與傳導特徵並不直接延伸於溝槽環64B下方，並且侷限在溝槽環64B包圍的區域中。
如圖11所示，切割線52中的聚合物60之部分係比封裝54中的聚合物60之部分更厚。因此，在圖案化聚合物60的微影蝕刻製程中，由於切割線52中聚合物60的底部有不適當的曝光，因而在圖案化之後可能留下殘留物60’。切割線52中亦可能沒有聚合物60的殘留物。可理解是否有殘留物60’係受到一些因子影響，包含層46與60的厚度與材料、曝光條件、以及類似因子。
接著，參閱圖12，形成RDL 66以連接至RDL 58。其相對應步驟係如圖23之製程流程的步驟330所示。RDL 66亦包含聚合物層60上方的金屬導線(金屬線)以及延伸至開口64C(圖11)中的通路，以電連接至RDL 58。RDL 66的材料與形成製程可類似於RDL 58的材料與形成製程。溝槽環64B與切割線52保持不被RDL 66填充。
參閱圖13，以例如經由旋塗方式，在RDL 66上方，形成聚合物層68。其相對應步驟係如圖23之製程流程的步驟332所示。在本文中，聚合物層68係指頂部聚合物層。雖然所述之範例實施例係說明三層介電(聚合物)層與對應的RDL，然而在其他實施例中的層數可更多或更少。亦可使用與介電層46相同的候選材料之聚合物，以形成聚合物層68。例如，聚合物層68可包括PBO、聚亞醯胺、或類似物。在形成之後，聚合物層68係填充開口64A與64B(圖12)，並且覆蓋RDL 66。
接著，亦如圖13所示，將聚合物層68圖案化。其相對應步驟係如圖23之製程流程的步驟334所示。在複合封裝100上方，配置光微影蝕刻製程遮罩70。而後，進行曝光，其中光(箭號)的投射係曝光聚合物層68。在顯影與烘烤製程之後，形成開口72(包含72A、72B與72C)，如圖14所示。經由開口72C，暴露RDL 66的接墊部分， 開口72C係封裝54中的分離開口。開口72B亦在封裝54中，並且從聚合物層68的頂部表面延伸至聚合物層60的頂部表面，因而聚合物層60係經由開口72B而暴露。根據一些實施例，開口72B係形成接近切割線52的溝槽環(亦參閱圖22)。再者，可形成開口72B，其包圍但不重疊在個別封裝54中的個別晶粒36與傳導特徵。換言之，根據本揭露的一些實施例，封裝54中的晶粒36與傳導特徵並未直接延伸於溝槽環72B下方，而是受限在溝槽環72B所包圍的區域中。在一些例示實施例中，如圖14所示，溝槽環72B形成在溝槽環64B(其係被聚合物層68填充)的內側上。
如圖13所示，切割線52中的聚合物68之部分係比封裝54中的聚合物60之部分更厚。因此，在圖案化聚合物60的微影蝕刻製程之後，如圖14所示，殘留物部分68，(圖14)係留在切割線52中。殘留物部分68’的厚度可大於、等於、或小於封裝54中的聚合物層68之部分的厚度。
根據一些例示實施例，溝渠環64B與最近的切割線52相距D1。距離D1可大於約10微米，並且可小於約50微米。溝槽環64B的寬度W1可大於約10微米，並且小於約50微米。溝槽環64B與溝槽環72B的距離D2範圍可在約10微米與約50微米之間。溝槽環72B的寬度W2範圍亦可在約10微米與約50微米之間。
圖15係根據一些例示實施例說明凸塊下金屬層(UBM)74與電連接物76的形成。其相對應步驟係如圖23之製程流程的步驟336所示。UBM74的形成可包含沉積與圖案化。電連接物76的形成可包含在UBM 74的暴露部分上設置銲球，而後迴銲該銲球。在其他實施例中，電連接物76的形成包含進行電鍍步驟，以於RDL 66上方形成銲區，而後迴銲該銲區。電連接物76亦可包含金屬柱或是金屬柱與銲帽，其亦可經由電鍍而形成。
接著，從載體20剝離封裝100。在釋放層22上投射光，例如UV光，以分解釋放層22而進行剝離。在剝離製程中，可在聚合物層68與電連接物76上，附貼膠帶(未繪示)。在後續步驟中，從封裝100移除載體20與釋放層22。所得的結構係如圖16所示。
如圖16所示，進行晶粒切割步驟，將封裝100切割為複數個封裝54，其各自包含元件晶粒22與貫穿通路32。切割刀所穿過的路徑係標示為路徑67。其相對應步驟係如圖23之製程流程的步驟338所示。圖22係說明從封裝100切割的封裝54之一的俯視圖。可理解的是，由於一般切割刀的寬度係小於切割線52的寬度，如圖15所示，因此所得的封裝54可包含小部分的原始切割線52。
再次參閱圖16，在切割封裝100的過程中，由於切割線有殘留物，因此相鄰的介電/聚合物層46、60與/或68會被切過。由於相鄰的介電/聚合物層46、60及68與成型材料44之間的介面係較脆弱的部分，因而介電/聚合物層46、60與68的上方部分可能會從下方的介電/聚合物層46、60、68與成型材料44產生脫層。脫層容易經由該些介面散布至封裝54中。藉由形成溝槽區64B與72B，若發生脫層，則溝槽環可停止脫層。例如，假設在聚合物層46與60的介面處發生脫層並經由該介面散布，脫層會到標示為63的位置處停止，其亦為環。若在聚合物層60與68的介面發生脫層並經由該介面散部，則脫層會到標示為65的位置處停止，其亦為環。
圖16亦說明接合封裝54與另一封裝200。根據本揭露的一些實施例，經由銲區98進行接合，其接合RDL 26的金屬墊部分至封裝200中的金屬墊。根據本揭露的一些實施例，封裝200包含元件晶粒202，其可為記憶體晶粒，例如靜態隨機存取記憶體(SRAM)晶粒、動態隨機存取記憶體(DRAM)晶粒、或類似物。在一些例示實施例中，記憶體晶粒亦可接合至封裝基板204。
圖21係說明封裝100與切割線52的俯視圖。如圖21所示，溝槽環72B係形成包圍元件晶粒36、電連接物76與RDL 58及66的環。溝槽環64B亦形成環。根據本揭露的一些實施例，如圖21所示，溝槽環72B係包圍溝槽環64B。在其他實施例(未繪示)中，溝槽環72B係被溝槽環64B包圍。切割封裝100之後所得到的封裝54係如圖22所示。
圖17至20係根據其他實施例說明封裝100(與其中的封裝54)之剖面圖。在圖17至20中，溝槽64B與72B可形成接近封裝之個別邊緣的完整環。如圖17所示，溝槽環64B與溝槽環72B彼此重疊，溝槽環72B的寬度W2係小於溝槽環64B的寬度W1。據此，溝槽環72B係延伸至聚合物層68的部分，聚合物層68係延伸至溝槽環64B中。
圖18係根據其他實施例說明封裝100(與其中的封裝54)的剖面圖。在這些實施例中，溝槽環64B與溝槽環72B亦彼此重疊，溝槽環72B的寬度W2係大於溝槽環64B的寬度W1。據此，聚合物層68未延伸至溝槽環64B中。在這些實施例中，溝槽環64B與72B係合併成為大的溝槽環。
圖19係根據其他實施例說明封裝100(與其中的封裝54)的剖面圖。在這些實施例中，聚合物層60中，沒有形成溝槽環。當圖11所示之步驟後，沒有聚合物層60的殘留物部分留在切割線52中，則可使用這些實施例，因而不需要在聚合物層60中形成溝槽區。然而，當形成越多聚合物層，切割線52中的溝槽變得越來越深，因而上方的聚合物層，例如聚合物層68，更有可能留下殘留物部分。因此，在這些實施例中，在聚合物層68中，形成溝槽環72B。
圖20係根據其他實施例說明封裝100(與其中的封裝54)的剖面圖。在這些實施例中，溝槽環64B與72B彼此重疊，溝槽環72B的寬度W2’係小於溝槽環64B的寬度W1。據此，溝槽環72B係延伸 至部分的聚合物層68中，該部分的聚合物層68係延伸至溝槽環64B中。此外，在切割線52對側上的兩個封裝之溝槽環72B係延伸至切割線52中，並且合併在一起。因此，在封裝100切割之後的最終結構中，溝槽環72B係延伸至封裝54的邊緣。
本揭露的實施例具有一些有利的特徵。在整合型扇出(Integrated Fan-Out，InFO)封裝的聚合物層中，形成溝槽環。溝槽環可作為封裝切割中的脫層阻止件，用以防止聚合物層之間的脫層延伸至封裝的內部中。本揭露的實施例之有利特徵在於溝槽環的形成與形成UBM及RDL開口係同步達到，因而沒有額外的製造成本。
根據本揭露的一些實施例，封裝包含元件晶粒、包圍元件晶粒的成型材料，其中成型材料的頂部表面係與元件晶粒的頂部表面實質齊平，以及在元件晶粒與成型材料上方的底部介電層。複數個RDL延伸至底部介電層中，並且電性耦合至元件晶粒。頂部聚合物層係位於底部介電層上方，溝槽環係穿過頂部聚合物層。溝槽環係與封裝的邊緣相鄰。封裝進一步包含UBM，其延伸至頂部聚合物中。
根據本揭露的其他實施例，封裝包含元件晶粒，以及包圍元件晶粒的成型材料，其中成型材料的頂部表面係與元件晶粒的頂部表面實質齊平。貫穿通路係穿過成型材料，其中貫穿通路的頂部表面係與元件晶粒的頂部表面實質共平面。封裝進一步包括第一聚合物層，其係位於元件晶粒、貫穿通路與成型材料上方，並且接觸元件晶粒、貫穿通路與成型材料。複數個RDL係延伸至第一聚合物層中，以電性耦合至元件晶粒與貫穿通路。第二聚合物層係位於第一聚合物層與複數個RDL上方，其中第一溝槽環係從第二聚合物層的頂部表面延伸至第一聚合物層的頂部表面。封裝進一步包括第三聚合物層，其係位於第二聚合物層上方並且接觸第二聚合物層，其中第二溝槽環係從第三聚合物層的頂部表面延伸至第二聚合物層的頂部表面。UBM 係延伸至第三聚合物層中。
根據本揭露的其他實施例，方法包含在成型材料中，成型複數個元件晶粒，以及將複數個元件晶粒與成型材料平坦化，其中元件晶粒的頂部表面係與成型材料的頂部表面齊平。該方法進一步包含在複數個元件晶粒與成型材料上方形成第一聚合物層，其係接觸複數個元件晶粒與成型材料，以及將第一聚合物層平坦化，以形成複數個第一開口，元件晶粒的金屬柱係經由複數個第一開口而暴露。藉由圖案化第一聚合物層的步驟，形成切割線。該方法進一步包括形成複數個重佈線，其具有穿過第一聚合物層的通路部分，在第一聚合物層上方形成第二聚合物層，以及圖案化第二聚合物層，以形成複數個第二開口與複數個第一溝槽環，複數個第一溝槽環係各自包圍複數個元件晶粒之一。複數個第一溝槽環係藉由切割線而彼此分離。形成複數個UBM，其係延伸至第二聚合物層中。
前述內容概述一些實施方式的特徵，因而熟知此技藝之人士可更加理解本申請案揭示內容之各方面。熟知此技藝之人士應理解可輕易使用本申請案揭示內容作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施方式具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本申請案揭示內容的精神與範圍，以及熟知此技藝之人士可進行各種變化、取代與替換，而不脫離本申請案揭示內容之精神與範圍。
20‧‧‧載體
24‧‧‧介電層
26‧‧‧重佈線(RDL)
36‧‧‧元件晶粒
28‧‧‧介電層
32‧‧‧貫穿通路
45‧‧‧晶粒附接膜(DAF)
40‧‧‧頂部介電層
44‧‧‧成型材料
46‧‧‧介電層
52‧‧‧切割線
54‧‧‧封裝
58‧‧‧重佈線
38‧‧‧金屬柱
60‧‧‧聚合物層
100‧‧‧複合封裝
66‧‧‧RDL
68‧‧‧聚合物層
74‧‧‧凸塊下金屬層(UBM)
76‧‧‧電連接物
67‧‧‧路徑
200‧‧‧封裝
202‧‧‧元件晶粒
204‧‧‧封裝基板
64B、72B‧‧‧溝槽環

Claims (10)

  1. 一種封裝，其包括：元件晶粒；成型材料，其包圍該元件晶粒，其中該成型材料的頂部表面係與該元件晶粒的頂部表面實質齊平；底部介電層，其係位於該元件晶粒與該成型材料上方；複數個重佈線，其延伸至該底部介電層中並且電性耦合至該元件晶粒；頂部聚合物層，其位於底部介電層上方；在該頂部聚合物層與該底部介電層之間的中間聚合物層，一溝槽環穿過該中間聚合物層，該溝槽環係與該封裝的邊緣相鄰，並且該頂部聚合物層填充該溝槽環；以及凸塊下金屬層(UBM)，其係延伸至該頂部聚合物層中。
  2. 如請求項1所述之封裝，其中該溝槽環係藉由該中間聚合物層的一部分而與該封裝的邊緣隔開，該中間聚合物層的該部分係形成包圍該溝槽環的環。
  3. 如請求項1所述之封裝，其中該溝槽環係延伸至該封裝的邊緣。
  4. 如請求項1所述之封裝，其中該溝槽環係延伸至該底部介電層的頂部表面。
  5. 如請求項1所述之封裝，進一步包括另一溝槽環穿過該頂部聚合物層，其中該另一溝槽環係與該封裝的邊緣相鄰。
  6. 如請求項1所述之封裝，進一步包括位於該中間聚合物層中的多個開口，一些該等重佈線延伸入該等開口，而該溝槽環係與該等開口同時形成。
  7. 一種封裝，其包括： 元件晶粒；成型材料，其包圍該元件晶粒，其中該成型材料的頂部表面係與該元件晶粒的頂部表面實質齊平；貫穿通路，其係穿過該成型材料，其中該貫穿通路的頂部表面係與該元件晶粒的該頂部表面實質共平面；第一聚合物層，其係位於該元件晶粒、該貫穿通路與該成型材料上方，並且接觸該元件晶粒、該貫穿通路與該成型材料；複數個重佈線，其係延伸至該第一聚合物層中並電性耦合至該元件晶粒與該貫穿通路；第二聚合物層，其係位於該第一聚合物層與該些複數個重佈線上方，其中第一溝槽環系從該第二聚合物層的頂部表面延伸至該第一聚合物層的頂部表面；第三聚合物層，其係位於該第二聚合物層上方並且接觸該第二聚合物層，其中第二溝槽環係從該第三聚合物層的頂部表面延伸至該第二聚合物層的頂部表面；以及凸塊下金屬層(UBM)，其係延伸至該第三聚合物層中。
  8. 如請求項7所述之封裝，其中該第一溝槽環係位於該第二溝槽環與該封裝的邊緣之間。
  9. 如請求項7所述之封裝，其中該第一溝槽環係停止於該第一聚合物層的頂部表面，以及該第二溝槽環係停止於該第二聚合物層的頂部表面。
  10. 一種形成半導體封裝的方法，其包括：在成型材料中，成型複數個元件晶粒；平坦化該複數個元件晶粒與該成型材料，其中該元件晶粒的頂部表面係與該成型材料的頂部表面齊平；形成第一聚合物層，其係位於該複數個元件晶粒與該成型材料 上方，並且接觸該複數個元件晶粒與該成型材料；圖案化該第一聚合物層，以形成第一複數個開口，該元件晶粒的金屬柱係經由該第一複數個開口而暴露，其中藉由圖案化該第一聚合物層而形成切割線；形成複數個重佈線，其包括穿過該第一聚合物層的通路部分；形成第二聚合物層，其係位於該第一聚合物層上方；以及圖案化該第二聚合物層，以形成複數個第二開口與複數個第一溝槽環，該些複數個第一溝槽環各自包圍該些複數個元件晶粒之一，並且該些複數第一個溝槽環係藉由該切割線而彼此分離；以及形成複數個凸塊下金屬層(UBM)，其係延伸至該第二聚合物層中。
TW104137132A 2015-03-16 2015-11-11 半導體封裝及其形成方法 TWI584423B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562133770P 2015-03-16 2015-03-16
US14/713,935 US9589903B2 (en) 2015-03-16 2015-05-15 Eliminate sawing-induced peeling through forming trenches

Publications (2)

Publication Number Publication Date
TW201642408A TW201642408A (en) 2016-12-01
TWI584423B true TWI584423B (zh) 2017-05-21

Family

ID=56852979

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104137132A TWI584423B (zh) 2015-03-16 2015-11-11 半導體封裝及其形成方法

Country Status (5)

Country Link
US (5) US9589903B2 (zh)
KR (1) KR101962508B1 (zh)
CN (1) CN105990272B (zh)
DE (1) DE102015108684B4 (zh)
TW (1) TWI584423B (zh)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9589903B2 (en) 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
JP6640780B2 (ja) * 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
US10522526B2 (en) 2017-07-28 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. LTHC as charging barrier in InFO package formation
US10453821B2 (en) * 2017-08-04 2019-10-22 Samsung Electronics Co., Ltd. Connection system of semiconductor packages
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US10790244B2 (en) 2017-09-29 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10529650B2 (en) * 2017-11-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
DE102018122228B4 (de) * 2017-11-15 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integriertes Multichip-Fan-Out-Package sowie Verfahren zu dessen Herstellung
US11177201B2 (en) 2017-11-15 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages including routing dies and methods of forming same
US10396053B2 (en) 2017-11-17 2019-08-27 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10566301B2 (en) * 2017-11-17 2020-02-18 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10607941B2 (en) 2018-04-30 2020-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device
US11056459B2 (en) * 2018-08-14 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10522488B1 (en) * 2018-10-31 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning polymer layer to reduce stress
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 芯片封装结构及其制作方法
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US20220167499A1 (en) * 2019-05-06 2022-05-26 3M Innovative Properties Company Patterned conductive article
US11088094B2 (en) * 2019-05-31 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Air channel formation in packaging process
US11133282B2 (en) * 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
KR20210023021A (ko) 2019-08-21 2021-03-04 삼성전자주식회사 반도체 패키지
CN114556409A (zh) * 2019-10-11 2022-05-27 应用材料公司 比较对准向量的裸片系统和方法
US11862594B2 (en) * 2019-12-18 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure with solder resist underlayer for warpage control and method of manufacturing the same
KR20210087337A (ko) 2020-01-02 2021-07-12 삼성전자주식회사 반도체 패키지와 이를 구비하는 전자 장치 및 반도체 패키지의 제조방법
KR102517379B1 (ko) 2020-02-14 2023-03-31 삼성전자주식회사 반도체 패키지의 제조 방법
KR20210141821A (ko) 2020-05-13 2021-11-23 삼성디스플레이 주식회사 디스플레이 장치
KR102610247B1 (ko) * 2020-11-11 2023-12-06 주식회사 네패스 반도체 패키지 및 이의 제조 방법
TWI775280B (zh) * 2021-01-20 2022-08-21 力晶積成電子製造股份有限公司 電容集成結構、電容單元及其製造方法
US11842935B2 (en) * 2021-02-18 2023-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a reconstructed package substrate comprising substrates blocks
TWI829396B (zh) * 2022-10-21 2024-01-11 欣興電子股份有限公司 電路板結構及其製作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090115024A1 (en) * 2007-11-01 2009-05-07 Jeng Shin-Puu Seal ring structure with improved cracking protection and reduced problems
US20090321890A1 (en) * 2008-06-26 2009-12-31 Jeng Shin-Puu Protective Seal Ring for Preventing Die-Saw Induced Stress
US20130001776A1 (en) * 2011-06-28 2013-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Wafer Level Package

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8409926B2 (en) 2010-03-09 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer around semiconductor die
US9548240B2 (en) * 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
CN102859691B (zh) 2010-04-07 2015-06-10 株式会社岛津制作所 放射线检测器及其制造方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US20120326324A1 (en) * 2011-06-22 2012-12-27 Lee Hyungmin Integrated circuit packaging system with package stacking and method of manufacture thereof
US20120326300A1 (en) * 2011-06-24 2012-12-27 National Semiconductor Corporation Low profile package and method
US8643148B2 (en) 2011-11-30 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer structures and methods for forming the same
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US8871568B2 (en) * 2012-01-06 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and method of forming the same
US9406579B2 (en) * 2012-05-14 2016-08-02 STATS ChipPAC Pte. Ltd. Semiconductor device and method of controlling warpage in semiconductor package
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9337073B2 (en) * 2013-03-12 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3D shielding case and methods for forming the same
US20140264630A1 (en) * 2013-03-15 2014-09-18 Chao-Yuan Huang Integrated Structure
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9425121B2 (en) 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
US9589903B2 (en) 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090115024A1 (en) * 2007-11-01 2009-05-07 Jeng Shin-Puu Seal ring structure with improved cracking protection and reduced problems
US20090321890A1 (en) * 2008-06-26 2009-12-31 Jeng Shin-Puu Protective Seal Ring for Preventing Die-Saw Induced Stress
US20130001776A1 (en) * 2011-06-28 2013-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Wafer Level Package

Also Published As

Publication number Publication date
US20200111751A1 (en) 2020-04-09
US11018091B2 (en) 2021-05-25
US9589903B2 (en) 2017-03-07
KR20160111308A (ko) 2016-09-26
CN105990272B (zh) 2019-05-07
US20160276284A1 (en) 2016-09-22
KR101962508B1 (ko) 2019-03-26
US20190115304A1 (en) 2019-04-18
CN105990272A (zh) 2016-10-05
DE102015108684A1 (de) 2016-09-22
TW201642408A (en) 2016-12-01
US10510678B2 (en) 2019-12-17
DE102015108684B4 (de) 2022-11-17
US10157854B2 (en) 2018-12-18
US20170170128A1 (en) 2017-06-15
US9947626B2 (en) 2018-04-17
US20180218983A1 (en) 2018-08-02

Similar Documents

Publication Publication Date Title
TWI584423B (zh) 半導體封裝及其形成方法
TWI663699B (zh) 半導體封裝及其形成方法
US20200350279A1 (en) Integrated Fan-Out Package Structures with Recesses in Molding Compound
TWI625831B (zh) 具有不連續聚合物層之扇出型堆疊式封裝結構
TWI550787B (zh) 晶粒中的環狀結構
US10032704B2 (en) Reducing cracking by adjusting opening size in pop packages
TWI618209B (zh) 封裝體
TWI696252B (zh) 封裝體及其製造方法
CN110416095B (zh) 封装件及其形成方法
TW201826408A (zh) 具有相反輪廓銅柱的整合扇出結構
US9484227B1 (en) Dicing in wafer level package
KR102293695B1 (ko) 스트레스를 감소시키기 위한 폴리머 층의 패터닝
CN110660683B (zh) 支撑info封装件以减小翘曲
TWI575664B (zh) 封裝結構及其形成方法
TW201740443A (zh) 封裝體及其形成方法
TW201639093A (zh) 扇出型封裝物中之分離聚合物
TW201824488A (zh) 封裝結構
TWI683411B (zh) 半導體封裝結構及其製造方法
TW201906033A (zh) 封裝結構及其製造方法
TWI587464B (zh) 封裝結構及其製造方法
TWI707428B (zh) 積體電路元件的封裝體及其形成方法