TWI625831B - 具有不連續聚合物層之扇出型堆疊式封裝結構 - Google Patents

具有不連續聚合物層之扇出型堆疊式封裝結構 Download PDF

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TWI625831B
TWI625831B TW104139368A TW104139368A TWI625831B TW I625831 B TWI625831 B TW I625831B TW 104139368 A TW104139368 A TW 104139368A TW 104139368 A TW104139368 A TW 104139368A TW I625831 B TWI625831 B TW I625831B
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die
dielectric layer
layer
attach film
semiconductor package
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TW104139368A
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TW201639091A (zh
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蔡宜霖
張智堯
林俊成
劉乃瑋
符策忠
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台灣積體電路製造股份有限公司
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Abstract

封裝物包括裝置晶粒、用以使其中之裝置晶粒的至少一部分成型之模塑料、以及實質上貫穿模塑料之貫穿通路。所述封裝物進一步包括與貫穿通路及模塑料接觸之介電層，以及附接至裝置晶粒背側之晶粒附接膜。晶粒附接膜包括延伸至介電層中的一部分。

Description

具有不連續聚合物層之扇出型堆疊式封裝結構
本揭露是關於一半導體封裝物。
現代電路的製造涉及了多個步驟。首先，在半導體晶圓上製備積體電路，所述半導體晶圓有多個相同的半導體晶片，分別包括多個積體電路。之後將半導體晶片由晶圓上鋸切出來，並將其封裝。封裝製程有兩個主要的目的：保護精密的半導體晶片，以及將內部的積體電路連接至外部接腳。
由於本領域要求積體電路應具備更多功能，發展出了堆疊式封裝(package-on-package，簡稱PoP)技術，此技術將二或更多個封裝物接合，以便提升封裝物之集成能力。隨著集成程度的提升，元件之間的連接路徑變短，使所得PoP封裝物之電性效能能夠提升。藉由利用PoP技術，封裝物設計變得更有彈性且較不複雜。上市時間亦可縮短。
本揭露某些實施方式提出一封裝物，根據本揭露某些實施方式，一封裝物包括裝置晶粒、使其中之該裝置晶粒的至少一部分成型之模塑料、以及實質上貫穿模塑料之貫穿通路。所述封裝物進一步包括與貫穿通路及模塑料接觸之介電層、以及附接至裝置晶粒背 側的晶粒附接膜。晶粒附接膜有一部分延伸至介電層中。
根據本揭露可替代的實施方式，一封裝物包括其中有一貫穿開孔之聚合物層、至少一部分位於貫穿開孔中之晶粒附接膜、背側附接至晶粒附接膜之裝置晶粒、以及模塑料。裝置晶粒於模塑料中成型，且聚合物層與模塑料相接觸。
根據本揭露可替代的實施方式，一種方法包括形成一聚合物層於一載板上，圖樣化該聚合物層，以形成一第一開孔，形成一貫穿通路於該圖樣化聚合物層上，以及放置一裝置晶粒，使一晶粒附接膜之至少一部分附接至位於該第一開孔中之該裝置晶粒。所述方法進一步包括使該裝置晶粒及該貫穿通路於一模塑料中成型，形成重佈線，其係電性耦接至該裝置晶粒及該貫穿通路，自該聚合物層移除該載板，以及於該聚合物層中形成一第二開孔，以使該貫穿通路裸露。
30‧‧‧載板
32‧‧‧黏著層
34‧‧‧介電層
38、44‧‧‧開孔
40‧‧‧導電性晶種層
42‧‧‧光阻
46‧‧‧貫穿通路
48、304‧‧‧裝置晶粒
50‧‧‧晶粒附接膜
52‧‧‧模塑料
54‧‧‧金屬柱
55、56‧‧‧介電層
58‧‧‧重佈線(RDL)
60‧‧‧電連接件
62、162、300‧‧‧封裝物
63‧‧‧開孔
64‧‧‧切割膠帶
66‧‧‧切割框
70‧‧‧焊料區域
72‧‧‧底膠
在閱讀了下文實施方式以及附隨圖式時，能夠最佳地理解本揭露的多種態樣。應注意到，根據本領域的標準作業習慣，圖中的各種構件並未依比例繪製。事實上，為了能夠清楚地進行描述，可能會刻意地放大或縮小某些構件的尺寸。
圖1至圖15A繪示根據某些實施方式，於形成扇出型堆疊式封裝(PoP)封裝物之中間階段的剖面圖；圖15B繪示根據可替代的實施方式，扇出型PoP封裝物的剖面圖；圖16A及圖16B繪示根據某些實施方式，扇出型PoP封裝物的上視圖；以及圖17繪示根據某些實施方式，用以形成PoP封裝物之方法的流程圖。
以下揭示內容提供了多種實施方式或例示，其能用以實現本揭示內容的不同特徵。下文所述之元件與配置的具體例子係用以簡化本揭示內容。當可想見，這些敘述僅為例示，其本意並非用於限制本揭示內容。舉例來說，在下文的描述中，將一第一構件形成於一第二構件上或之上，可能包含某些實施例其中所述的第一與第二構件彼此直接接觸；且也可能包含某些實施例其中還有而外的元件形成於上述第一與第二構件之間，而使得第一與第二構件可能沒有直接接觸。此外，本揭示內容可能會在多個實施例中重複使用元件符號和/或標號。此種重複使用乃是基於簡潔與清楚之目的，且其本身不代表所討論的不同實施例和/或組態之間的關係。
再者，在此處使用空間上相對的詞彙，譬如「之下」、「下方」、「低於」、「之上」、「上方」及與其相似者，可能是為了方便說明圖中所繪示的一元件或構件相對於另一或多個元件或構件之間的關係。這些空間上相對的詞彙其本意除了圖中所繪示的方位之外，還涵蓋了裝置在使用或操作中所處的多種不同方位。可能將所述設備放置於其他方位(如，旋轉90度或處於其他方位)，而這些空間上相對的描述詞彙就應該做相應的解釋。
根據多種例示性的實施方式，提出了一種多層堆疊扇出型封裝物及其形成方法。繪示了形成多層堆疊扇出型封裝物之中間階段，討論實施方式之變形。在不同的圖式與多個說明性的實施方式中，使用類似的元件符號來指稱相似的部件。
根據多種例示性之實施方式，提出了扇出型堆疊式封裝(PoP)結構/封裝物以及形成所述封裝物之方法。下文討論了多種實施方式。在多個圖式與例示性的實施方式中，以相似的元件符號來指稱相似的部件。
圖1至圖15A繪示根據某些實施方式，於形成扇出型堆疊式封裝(PoP)封裝物之中間階段的剖面圖。圖1至圖15A中所示的步驟亦概要地繪示於圖17所示之製程200的流程圖中。在下文的討論中，會參照圖17所示的製程步驟來說明圖1至圖15A中所示的製程步驟。
參照圖1，提供載板30，且於載板30上設有黏著層32。載板30可以是空白玻璃載板、空白陶瓷載板或與其相似者，且其形狀可如半導體晶圓，一般由上方看來成圓形。載板30有時亦稱為載板晶圓。可利用譬如光熱轉換(Light-to-Heat Conversion，LTHC)材料來形成黏著層32，且亦可使用其他種類的黏著劑。根據本揭露某些實施方式，黏著層32會在光的熱能影響下分解，且能夠使載板30與形成於其上之結構分離。
於黏著層32上形成介電層34。此步驟如圖17之流程圖之步驟202所示。根據本揭露某些實施方式，介電層34可以是由一聚合物所形成之聚合物層，所述聚合物可以是光敏聚合物，譬如苯并口咢唑(polybenzoxazole，PBO)、聚醯亞胺或與其相似者。根據可替代的實施方式，介電層34是由以至少一種下材料所形成：氮化物(如氮化矽)、氧化物(如氧化矽)、磷矽酸鹽玻璃(PhosphoSilicate Glass，PSG)、硼矽酸鹽玻璃(BoroSilicate Glass，BSG)、硼磷矽酸鹽玻璃(Boron-doped PhosphoSilicate Glass，BPSG)或與其相似者。
參照圖2，將介電層34圖樣化，以在其中形成開孔38。此步驟如圖17流程圖之步驟204所示。開孔38是貫穿開孔。因此，根據本揭露某些實施方式，黏著層32經由開孔38而裸露。當可理解，雖然圖2僅繪示了一個開孔38，但可於介電層34中形成複數個開孔38，而每一個開孔38可供放置一或多個裝置晶粒於其中。再者，可 將多個開孔38配置為一陣列。在介電層34是由光敏材料所形成的實施方式中，介電層34之圖樣化可利用如下的方式進行：譬如利用一圖樣化光微影遮罩(圖中未繪示)以光線照射介電層34，之後再將介電層34顯影。根據可替代的實施方式，介電層34之圖樣化包括將一光阻(圖中未繪示)施佈於介電層34上、圖樣化所述光阻，且之後再利用光阻作為蝕刻遮罩來蝕刻介電層34。
參照圖3，利用譬如物理氣相沈積(Physical Vapor Deposition，PVD)，於介電層34上形成導電性晶種層40。此步驟如圖17流程圖之步驟206所示。導電性晶種層40可以是一金屬晶種層，其包括銅、鋁、鈦、上述金屬之合金或由其組成之多層結構。根據本揭露某些實施方式，導電性晶種層40包括第一金屬層(例如鈦層；圖中未繪示)以及設於第一金屬層上之第二金屬層(例如銅層；圖中未繪示)。在這些實施方式中，導電性晶種層40有一部分延伸至開孔38中，且上述部分可和黏著層32相接觸。根據本揭露可替代的實施方式，導電性晶種層40包括一單一金屬層，例如一銅層，其可實質上由純銅或銅合金所形成。
圖4至圖7繪示貫穿通路之形成。如圖4所示，將圖樣化遮罩層42(例如光阻)設於導電性晶種層40上，且之後利用光微影遮罩將其圖樣化。此步驟如圖17流程圖之步驟208所示。根據本揭露某些實施方式，光阻42是乾式膜，可將其層疊至導電性晶種層40上。根據可替代的實施方式，光阻42是藉由旋塗法形成。由於圖樣化(曝光與顯影)的關係，會在光阻42中形成開孔44，導電性晶種層40的某些部分會經由這些開孔44而裸露。光阻42之厚度取決於後續設置於其上之裝置晶粒48之厚度(圖8)。根據本揭露某些實施方式，光阻42之厚度大於裝置晶粒48之之厚度。
如圖5所示，藉由鍍覆法在開孔44中形成貫穿通路 46，所述鍍覆法可以是電鍍或無電電鍍。此步驟如圖17流程圖之步驟210所示。將貫穿通路46鍍覆於導電性晶種層40之裸露部分上。貫穿通路46有導電性，且可為金屬通路，包括銅、鋁、鎢、鎳或其合金。貫穿通路46之上視形狀包括，且不限於：矩形、正方形、圓形及與其相似者。貫穿通路46之高度取決於後續設置於其上之裝置晶粒48之高度(圖8)，而根據本揭露某些實施方式，貫穿通路46之高度略高於或等於裝置晶粒48之厚度。
在鍍覆貫穿通路46之後，移除光阻42，所得結構如圖6所示。此步驟如圖17流程圖之步驟212所示。因此，導電性晶種層40原本被光阻42覆蓋的部分得以裸露。
接著如圖7所示，進行蝕刻步驟以移除導電性晶種層40的裸露部分，其中所述蝕刻可以是非等向性或等向性蝕刻。此步驟如圖17流程圖之步驟212所示。另一方面，導電性晶種層40與貫穿通路46重疊之部分則仍然未被蝕刻。在本說明書中，留存之導電性晶種層40的下部稱為貫穿通路46之底部部分。雖然圖中所示之導電性晶種層40和位於其上之貫穿通路46的部分有可區分的介面，當導電性晶種層40是由和個別之上方貫穿通路46類似或相同的材料所形成時，導電性晶種層40可和貫穿通路46合併，而兩者間沒有可區分的介面。譬如，導電性晶種層40之銅層可和貫穿通路46合併而不會形成可區分介面。根據可替代的實施方式，在導電性晶種層40和位於上方之各別貫穿通路46之鍍覆部分之間存在可區分介面。譬如，導電性晶種層40中之鈦層和含銅貫穿通路46是可以區分的。對導電性晶種層40之蝕刻會導致介電層34裸露。此外，開孔38也會露出，且位於介電層34下方之層(譬如黏著層32)會經由開孔38而裸露。
圖8繪示將裝置晶粒48放置於黏著層32上。此步驟如圖17流程圖之步驟214所示。可透過晶粒附接膜50，將裝置晶粒48接 著至黏著層32。晶粒附接膜50之邊緣與覆設於其上之各別裝置晶粒48的邊緣共端點(對齊)。晶粒附接膜50為黏性膜。雖然圖8僅繪示放置單一裝置晶粒48，可將和裝置晶粒48相同的複數個裝置晶粒放置於黏著層32上，且每一裝置晶粒係設於一對應至開孔38中。再者，每一開孔38中可放置單一個或超過一個的裝置晶粒。可將所放置之該些裝置晶粒48排列為包括複數個行與複數個列之陣列。裝置晶粒48可包括一半導體基板，其有一後表面(朝下之表面)與各別晶粒附接膜50物理接觸。裝置晶粒48進一步包括積體電路裝置(譬如主動元件，其包括如電晶體；圖中未繪示)，其位於半導體基板之前表面(朝上之表面)。裝置晶粒48可包括包括邏輯晶粒，譬如中央處理單元(Central Processing Unit，CPU)晶粒、圖形處理單元(Graphic Processing Unit，GPU)晶粒、行動應用晶粒或與其相似者。。
裝置晶粒48之頂面可包括金屬柱54。金屬柱54係電性耦接至位於裝置晶粒48內之積體電路。根據本揭露某些例示性之實施方式，如圖8所示，金屬柱54之頂面為裸露的。金屬柱54可以是銅柱，且亦可包括其他導電性/金屬材料，如鋁、鎳或與其相似者。根據本揭露某些實施方式，金屬柱54之頂面與介電層55之頂面共平面。根據本揭露可替代的實施方式，金屬柱54嵌於介電層55內，且介電層55之頂面高於金屬柱54之頂面。介電層55可由聚合物所形成，其可包括PBO、聚醯亞胺或與其相似者。
參照圖9，模塑料52於裝置晶粒48及貫穿通路46上成型。此步驟如圖17流程圖之步驟216所示。以液體形式施佈模塑料52，且之後利用譬如熱固化製程使其固化。模塑料52可填充於裝置晶粒48與貫穿通路46之間的間隙，且可和介電層34接觸。模塑料52可包括模塑料、成型底膠、環氧樹脂或樹脂。在成型製程之後，模塑料52之頂面高於金屬柱54及貫穿通路46的上端。
接著進行平坦化步驟例如化學機械研磨(Chemical Mechanical Polish，CMP)步驟或研磨步驟，以使模塑料52平坦化，直到貫穿通路46裸露為止。此步驟如圖17流程圖之步驟216所示。所得到之結構如圖10所示。由於平坦化作業的關係，貫穿通路46之頂面實質上和金屬柱54之頂面齊平(共平面)，且實質上和模塑料52之頂面齊平(共平面)。
參照圖11，於模塑料52、貫穿通路46與金屬柱54上形成一或更多層的介電層56與各別的重佈線(Redistribution Line，RDL)58。此步驟如圖17流程圖之步驟218所示。將RDL 58稱為前側RDL，因為這些元件係位於裝置晶粒48之前側上。根據本揭露某些實施方式，介電層56係由一或多種聚合物所形成，譬如PBO、聚醯亞胺或與其相似者。根據本揭露可替代的實施方式，介電層56係由一或多種無機介電材料所形成，譬如氮化矽、氧化矽、矽氮氧化物或與其相似者。
RDL 58經形成而能夠電性耦接至金屬柱54及貫穿通路46。RDL 58亦可將金屬柱54與貫穿通路46彼此互連。RDL 58可包括金屬導線與通路，所述通路位於金屬導線下方並連接至金屬導線。根據本揭露某些實施方式，經由鍍覆製程來形成RDL 58，其中每一RDL 58包括一晶種層(圖中未繪示)及設於晶種層上之經鍍覆之金屬材料。可利用相同或不同的材料來形成晶種層及經鍍覆之金屬材料。
圖12繪示根據本揭露某些例示性之實施方式，電連接件60之形成。電連接件60係電性耦接至RDL 58、金屬柱54，和/或貫穿通路46。電連接件60之形成可包括將焊球放置於RDL 58上，且之後使焊球回流。根據本揭露可替代的實施方式，電連接件60之形成包括進行鍍覆步驟以於RDL 58上形成焊料區域，且之後回流焊料區 域。電連接件60亦可包括金屬柱或金屬柱與焊料帽，其亦可經由鍍覆而形成。在本說明書中，包括裝置晶粒48、貫穿通路46、模塑料52、RDL 58及介電層56之總體結構稱為封裝物62，其可以是包括複數個裝置晶粒48之複合晶圓。
接著進行測試，以決定封裝物162是否可正常發揮功能而沒有缺陷。可利用探針卡(圖中未繪示)來測試電連接件60，以近行上述測試。經過上述測試，可找出封裝物162中有缺陷的封裝物，而使得在將封裝物162鋸切為個別的封裝物之後，不會使用有缺陷的封裝物來形成PoP封裝物。
圖12繪示了兩層RDL層58。根據可替代的實施方式，可以有單一層的RDL 58或超過兩層的RDL 58，其層數可取決於各別封裝物之佈線需求。根據本揭露又一些可替代的實施方式，沒有RDL，而是將電性連接件60直接形成在貫穿通路46與金屬柱54上，且連接件60和下方貫穿通路46及金屬柱54之間並未形成RDL。
接著使封裝物62由載板30脫離。根據某些例示性之脫離製程，將切割膠帶64(圖13)接著至封裝物62以保護電連接件60，其中切割膠帶64係固定於切割框66。可藉由譬如在黏著層32(圖12)投射UV光線或雷射，以進行脫離作業。譬如，當黏著層32是由LTHC所形成時，光線或雷射所產生的熱會使得LTHC分解，且因而載板30會由封裝物62脫離。所得到之結構如圖13所示。
圖14繪示用以在介電層34中形成開孔63之圖樣化步驟。此步驟如圖17流程圖之步驟220所示。譬如，當介電層34為聚合物層時，可利用雷射鑽孔進行圖樣化，以移除與貫穿通路46重疊之部分，而使得貫穿通路46經由開孔63而裸露。
在某些實施方式中，導電性晶種層40的一部分是由鈦所形成的，此時亦可移除導電性晶種層40中之鈦層。譬如，可利用氫 氟酸(HF)氣體或稀釋的HF溶液來蝕刻鈦。導電性晶種層40中的銅會裸露出來，且因此，可於其上形成後續步驟中形成之背側RDL或電連接件譬如焊料區域。
根據本揭露某些實施方式，此時(在鋸切晶粒之前)不會在封裝物62背側上形成焊料區域。再者，並未形成背側RDL。根據本揭露可替代的實施方式，在裝置晶粒48的背側(圖14中所繪示之上側)上形成RDL(圖中未繪示)和/或電連接件，其中背側RDL電性耦接至貫穿通路46。根據本揭露某些例示性之實施方式，背側RDL層為單一層。根據可替代的實施方式，有複數個RDL層，其中可形成貫穿通路以將位於不同RDL層中之不同金屬導線互相連接。背側介電層亦可由聚合物形成，譬如PBO、BCB、聚醯亞胺；或是由無機材料所形成，譬如氧化矽、氮化矽、矽氮氧化物或與其相似者。亦可形成電連接件譬如焊料區域、金屬柱與焊料帽、或與其相似者。
在後續的步驟中，鋸切封裝物62以將其分成複數個封裝物162，每一個封裝物包括一裝置晶粒48以及相應的貫穿通路46。此步驟如圖17流程圖之步驟222所示。圖15A繪示了一個封裝物162。
圖15A繪示將封裝物300接合至封裝物162，因而形成了PoP封裝物20。此步驟如圖17流程圖之步驟224所示。封裝物300與162亦分別稱為PoP封裝物20之頂部封裝物與底部封裝物。在如圖15A所示之例示性實施方式中，並未繪示背側RDL，但可根據替代性的實施方式形成背側RDL。透過焊料區域70來進行接合，其可將貫穿通路46連接至上方封裝物300之金屬墊。於某些實施方式中，封裝物300包括裝置晶粒(們)304，其可以是記憶體晶粒，譬如靜態隨機存取記憶體(Static Random Access Memory，SRAM)晶粒、動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)晶粒或與其相似者。於某些例示性之實施方式中，亦可將記憶體晶粒接合至封裝物基 板302。
在將頂部封裝物300接合至底部封裝物162之後，將底膠72施佈於頂部封裝物300及底部封裝物162之間的間隙中，且之後將其固化。因此，所得到之底膠72會和晶粒附接膜50接觸。
如圖15A所示，介電層34之頂面和晶粒附接膜50之頂面共平面。根據本揭露某些實施方式，貫穿通路46有某些部分的頂面和介電層34的底面接觸。晶粒附接膜50與裝置晶粒48延伸至介電層34中，且介電層34之邊緣和晶粒附接膜50的邊緣物理接觸。可藉由正確地設計開孔38(參照圖7及圖8)的尺寸，而使得晶粒附接膜50與裝置晶粒48正確地剛好置入開孔38中，且沒有額外的空間將晶粒附接膜50的邊緣和介電層34的各別邊緣分隔開來，以實現這些實施方式。當晶粒附接膜50比介電層34來得薄時，介電層34之邊緣亦可和裝置晶粒48的邊緣物理接觸。
根據本揭露可替代的實施方式，開孔38之尺寸(參照圖7)大於晶粒附接膜50及裝置晶粒48之尺寸，如圖15B所示。因此，剩餘了某些空間能夠將晶粒附接膜50及裝置晶粒48的邊緣和介電層34的各別邊緣分隔開來。如圖15B所示，底膠72可和模塑料52延伸進入介電層34中之部分物理接觸。
圖16A及圖16B分別繪示圖15A及圖15B之PoP封裝物20的某些部分的上視圖。參照圖16A，介電層34環繞晶粒附接膜50及裝置晶粒48。此外，貫穿通路46及焊料區域70與環繞晶粒附接膜50及裝置晶粒48的環對齊。晶粒附接膜50之邊緣(且也可能有裝置晶粒48之邊緣)與介電層34之內邊緣相接觸，其中所述的內邊緣面向開孔。參照圖16B，介電層34同樣環繞晶粒附接膜50及裝置晶粒48，且有一些空間將介電層34和晶粒附接膜50及裝置晶粒48分隔開來。模塑料52填充上述空間。根據本揭露某些實施方式，所述空間形成環繞晶粒附 接膜50及裝置晶粒48之一環。根據本揭露可替代的實施方式，晶粒附接膜50的一個或兩個邊緣可和介電層34之各別內邊緣(們)相接觸，而晶粒附接膜50之其他邊緣可和介電層34之各別內邊緣(們)相間隔。
本揭露之實施方式有許多優點。藉由圖樣化設於黏著層上之介電層(聚合物層)，聚合物層中有一較大的開孔。這使得聚合物層中出現了不連續的現象，而能夠降低聚合物層對所得之PoP封裝物所造成的應力。且因此可以減少封裝物的翹曲現象。此外，聚合物層是相對較軟的材料，且因此若將裝置晶粒放置於聚合物層上，由於在聚合物不同部分上施加的壓力可能不一樣，所得之聚合物層的厚度可能不均一，且因此所得裝置晶粒的頂面可能不會和載板表面平行，這會對後續製程帶來困難。然而，在本揭露的實施方式中，裝置晶粒並非放置於聚合物層上，且因此可避免上述問題。此外，聚合物層中的開孔能夠限制裝置晶粒及晶粒附接膜的移動，而使得晶粒偏移的發生機率降低。
本揭露某些實施方式提出一封裝物，根據本揭露某些實施方式，一封裝物包括裝置晶粒、使其中之該裝置晶粒的至少一部分成型之模塑料、以及實質上貫穿模塑料之貫穿通路。所述封裝物進一步包括與貫穿通路及模塑料接觸之介電層、以及附接至裝置晶粒背側的晶粒附接膜。晶粒附接膜有一部分延伸至介電層中。
根據本揭露可替代的實施方式，一封裝物包括其中有一貫穿開孔之聚合物層、至少一部分位於貫穿開孔中之晶粒附接膜、背側附接至晶粒附接膜之裝置晶粒、以及模塑料。裝置晶粒於模塑料中成型，且聚合物層與模塑料相接觸。
根據本揭露可替代的實施方式，一種方法包括形成一聚合物層於一載板上，圖樣化該聚合物層，以形成一第一開孔，形成 聚合物層於一載板上，圖樣化該聚合物層，以形成一第一開孔，形成一貫穿通路於該圖樣化聚合物層上，以及放置一裝置晶粒，使一晶粒附接膜之至少一部分附接至位於該第一開孔中之該裝置晶粒。所述方法進一步包括使該裝置晶粒及該貫穿通路於一模塑料中成型，形成重佈線，其係電性耦接至該裝置晶粒及該貫穿通路，自該聚合物層移除該載板，以及於該聚合物層中形成一第二開孔，以使該貫穿通路裸露。
上文的敘述簡要地提出了本發明某些實施例之特徵，而使得本發明所屬技術領域具有通常知識者能夠更全面地理解本揭示內容的多種態樣。本發明所屬技術領域具有通常知識者當可明瞭，其可輕易地利用本揭示內容作為基礎，來設計或更動其他製程與結構，以實現與此處所述之實施方式相同的目的和/或達到相同的優點。本發明所屬技術領域具有通常知識者應當明白，這些均等的實施方式仍屬於本揭示內容之精神與範圍，且其可進行各種變更、替代與更動，而不會悖離本揭示內容之精神與範圍。

Claims (10)

  1. 一種半導體封裝物，其包括：一裝置晶粒；一模塑料，使其中之該裝置晶粒的至少一部分成型；一貫穿通路，實質上貫穿該模塑料；一介電層，與該貫穿通路及該模塑料接觸；以及一晶粒附接膜，附接至該裝置晶粒之一背側，其中該晶粒附接膜包括延伸於該介電層中之一部分，且該晶粒附接膜設置在該半導體封裝物的最表層。
  2. 如請求項1所述的半導體封裝物，其中該介電層包括一貫穿開孔，且該晶粒附接膜延伸至該貫穿開孔中。
  3. 如請求項2所述的半導體封裝物，其中該介電層包括邊緣，其係裸露於該貫穿開孔，且其中該晶粒附接膜包括邊緣，其接觸該介電層之該邊緣。
  4. 如請求項2所述的半導體封裝物，其中該介電層包括邊緣，其係裸露於該貫穿開孔，且其中該晶粒附接膜包括邊緣，其與該介電層之該邊緣以間隔相隔開，而該模塑料填充於該開孔。
  5. 如請求項1所述的半導體封裝物，進一步包括一焊料區域，延伸至該介電層中以接觸該貫穿通路。
  6. 如請求項5所述的半導體封裝物，進一步包括一頂部封裝物，接著至該焊料區域。
  7. 如請求項1所述的半導體封裝物，其中該介電層包括一聚合物。
  8. 如請求項1所述的半導體封裝物，進一步包括另一介電層與該裝置晶粒中之金屬柱接觸。
  9. 一種半導體封裝物，其包括：一聚合物層，其中有一貫穿開孔；一晶粒附接膜，其至少一部分位於該貫穿開孔中，且該晶粒附接膜設置在該半導體封裝物的最表層；一裝置晶粒，有一背側附接至該晶粒附接膜；以及一模塑料，該裝置晶粒係於該模塑料中成型，其中該聚合物層接觸該模塑料。
  10. 一種形成半導體封裝物的方法，其包括：形成一聚合物層於一載板上；圖樣化該聚合物層，以形成一第一開孔；形成一貫穿通路於該圖樣化聚合物層上；放置一裝置晶粒，使一晶粒附接膜之至少一部分附接至位於該第一開孔中之該裝置晶粒；使該裝置晶粒及該貫穿通路於一模塑料中成型；形成重佈線，其係電性耦接至該裝置晶粒及該貫穿通路；自該聚合物層移除該載板；以及於該聚合物層中形成一第二開孔，以使該貫穿通路裸露。
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