CN105990272A - 通过形成沟槽消除锯切引起的剥离 - Google Patents

通过形成沟槽消除锯切引起的剥离 Download PDF

Info

Publication number
CN105990272A
CN105990272A CN201510759360.4A CN201510759360A CN105990272A CN 105990272 A CN105990272 A CN 105990272A CN 201510759360 A CN201510759360 A CN 201510759360A CN 105990272 A CN105990272 A CN 105990272A
Authority
CN
China
Prior art keywords
layer
grooved ring
component pipe
face
polymeric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510759360.4A
Other languages
English (en)
Other versions
CN105990272B (zh
Inventor
陈洁
陈宪伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN105990272A publication Critical patent/CN105990272A/zh
Application granted granted Critical
Publication of CN105990272B publication Critical patent/CN105990272B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明实施例提供一种封装件，包括器件管芯、环绕器件管芯的成型材料、以及位于器件管芯和成型材料上方的底部介电层，其中，成型材料的顶面与器件管芯的顶面基本齐平。多个再分布衬里(RDL)延伸至底部介电层内并且电耦接至器件管芯。顶部聚合物层位于底部介电层上方，其中，沟槽环穿过顶部聚合物层。沟槽环邻近封装件的边缘。封装件还包括延伸至顶部聚合物层内的凸块下金属(UBM)。本发明实施例还提供一种方法。

Description

通过形成沟槽消除锯切引起的剥离
相关申请的交叉参考
本申请要求于2015年3月16日提交的标题为“EliminateSawing-Induced Peeling Through Forming Trenches”的美国临时申请第62/133,770号的权益，其内容结合于此作为参考。
技术领域
本发明实施例涉及半导体领域，更具体地涉及通过形成沟槽消除锯切引起的剥离。
背景技术
随着半导体技术的发展，半导体芯片/管芯变得越来越小。同时，更多功能需要集成至半导体管芯内。因此，半导体管芯需要将越来越多的I/O衬垫封装至更小的面积内，并且I/O衬垫的密度随着时间迅速提升。结果，半导体管芯的封装变得更加困难，这会不利地影响封装的产量。
传统的封装技术可以划分为两类。在第一类中，在锯切晶圆上的管芯之前对它们进行封装。这种封装技术具有一些有利的特征，诸如更大的产量和更低的成本。此外，需要较少的底部填充物或成型料。然而，这种封装技术还具有缺陷。由于管芯的尺寸变得越来越小，并且相应的封装件仅可以是多输入型封装件，其中，每个管芯的I/O衬垫都限制于直接位于相应的管芯的表面上方的区域。根据管芯的有限的面积，由于I/O衬垫的间距的限制，所以I/O衬垫的数量受到限制。如果衬垫的间距减小，那么可能发生焊料桥接。附加地，在固定的焊球尺寸要求下，焊球必须具有特定的尺寸，这反而限制了可以封装在管芯表面上的焊球的数量。
在另一类封装中，在封装管芯之前从晶圆锯切管芯。该封装技术的有利特征是有可能形成多输出型封装件，这意味着管芯上的I/O衬垫可以分布至比管芯更大的面积，并且因此可以增大封装在管芯的表面上的I/O衬垫的数量。该封装技术的另一有利特征是封装“已知良好管芯”，以及丢弃缺陷管芯，并且因此不会在缺陷管芯上浪费成本和精力。
发明内容
本发明实施例提供一种封装件，包括：器件管芯；成型材料，环绕所述器件管芯，其中，所述成型材料的顶面与所述器件管芯的顶面基本齐平；底部介电层，位于所述器件管芯和所述成型材料上方；多个再分布衬里(RDL)，延伸至所述底部介电层内并且电耦接至所述器件管芯；顶部聚合物层，位于所述底部介电层上方，沟槽环穿过所述顶部聚合物层，其中，所述沟槽环邻近所述封装件的边缘；以及凸块下金属(UBM)，延伸至所述顶部聚合物层内。
本发明实施例还提供一种封装件，包括：器件管芯；成型材料，环绕所述器件管芯，其中，所述成型材料的顶面与所述器件管芯的顶面基本齐平；贯通孔，穿过所述成型材料，其中，所述贯通孔的顶面与所述器件管芯的顶面基本共面；第一聚合物层，位于所述器件管芯、所述贯通孔和所述成型材料上方并且与所述器件管芯、所述贯通孔和所述成型材料接触；多个再分布衬里(RDL)，延伸至所述第一聚合物层内以电耦接至所述器件管芯和所述贯通孔；第二聚合物层，位于所述第一聚合物层和所述多个RDL上方，其中，第一沟槽环从所述第二聚合物层的顶面延伸至所述第一聚合物层的顶面；第三聚合物层，位于所述第二聚合物层上方并且与所述第二聚合物层接触，其中，第二沟槽环从所述第三聚合物层的顶面延伸至所述第二聚合物层的顶面；以及凸块下金属(UBM)，延伸至所述第三聚合物层内。
本发明实施例还提供一种方法，包括：在成型材料中对多个器件管芯进行成型；平坦化所述多个器件管芯和所述成型材料，其中，所述器件管芯的顶面与所述成型材料的顶面齐平；在所述多个器件管芯和所述成型材料上方形成第一聚合物层，并且所述第一聚合物层与所述多个器件管芯和所述成型材料接触；图案化所述第一聚合物层以形成多个第一开口，通过所述多个第一开口暴露所述器件管芯的金属支柱，其中，通过图案化所述第一聚合物层形成划线；形成包括穿过所述第一聚合物层的通孔部分的多个再分布衬里；在所述第一聚合物层上方形成第二聚合物层；以及图案化所述第二聚合物层以形成多个第二开口和多个第一沟槽环，所述多个第一沟槽环的每个均环绕所述多个器件管芯中的一个，并且所述多个第一沟槽环通过所述划线彼此分离；以及形成延伸至所述第二聚合物层内的多个凸块下金属(UBM)。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，没有按比例绘制各种部件。实际上，为了清楚地讨论，可以任意地增加或减小各种部件的尺寸。
图1至图16是根据一些实施例的封装件的制造的中间阶段的截面图和顶视图；
图17至图20是根据可选实施例的封装件的截面图；
图21示出了根据一些实施例的封装件的顶视图；
图22示出了根据一些实施例的锯切的封装件的顶视图；以及
图23示出了根据一些实施例的封装件的形成的工艺流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，也可以包括在第一部件和第二部件之间可以形成附加的部件，从而使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在各个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，并且其本身不表示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文可以使用诸如“在…下面”、“在…下方”、“下部”、“在…上面”、“上部”等空间关系术语以描述如图所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且本文使用的空间关系描述符可以同样地作相应的解释。
根据各个示例性实施例，提供了一种封装件及其形成方法。示出了形成封装件的中间阶段。讨论了实施例的变型。在通篇的各个视图和说明性实施例中，类似的参考标号用于指示类似的元件。
图1至图16示出了根据一些实施例的封装件的形成的中间阶段的截面图。在如图23所示的工艺流程图300中也示意性地示出了图1至图16中示出的步骤。在随后的讨论中，参考图23中的工艺步骤讨论了图1至图16所示的工艺步骤。
图1示出了载体20和形成在载体20上的释放层22。载体20可以是玻璃载体、陶瓷载体等。载体20可以具有圆形顶视图形状并且可以具有硅晶圆的尺寸。例如，载体20可以具有8英寸的直径、12英寸的直径等。释放层22可以由聚合物基材料(诸如光热转换(LTHC)材料)形成，该释放层可以与载体20一起从将在随后步骤中形成的上面的结构去除。在一些实施例中，释放层22由环氧树脂基热释放材料形成。在其他的实施例中，释放层22由紫外(UV)胶形成。释放层22可以作为液体分配并且被固化。在可选的实施例中，释放层22是层压膜并且层压在载体20上。释放层22的顶面是水平的并且具有高度的共面性。
在释放层22上形成介电层24。根据本发明的一些实施例，介电层24由聚合物形成，该聚合物也可以是使用光刻工艺可以容易地图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺等的光敏材料。在可选的实施例中，介电层24由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)等形成。
参考图2，在介电层24上方形成再分布衬里(RDL)26。相应的步骤示出为图23中示出的工艺流程图中的步骤310。由于RDL 26位于器件管芯36(图5)的背侧上，所以其也称为背侧RDL。RDL 26的形成可以包括：在介电层24上方形成晶种层(未示出)，在晶种层上方形成诸如光刻胶的图案化的掩模(未示出)，以及然后对暴露的晶种层实施金属镀敷。然后去除图案化的掩模和晶种层的被图案化的掩模覆盖的部分，从而留下如图2中的RDL 26。根据一些实施例，晶种层包括钛层和位于钛层上方的铜层。例如，可以使用物理汽相沉积(PVD)形成晶种层。例如，可以使用化学镀实施该镀敷。
参考图3，在RDL 26上形成介电层28。介电层28的底面与RDL 26和介电层24的顶面接触。根据本发明的一些实施例，介电层28由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺等的光敏聚合物。在可选的实施例中，介电层28由诸如氮化硅的氮化物、诸如氧化硅的氧化物、PSG、BSG、BPSG等形成。然后图案化介电层28以在该介电层中形成开口30。因此，通过介电层28中的开口30暴露RDL 26。
参考图4，形成金属柱32。在通篇说明书中，由于金属柱32穿过随后形成的成型材料，所以金属柱32可选地称为贯通孔32。相应的步骤示出为图23中示出的工艺流程图中的步骤312。根据本发明的一些实施例，通过镀敷形成贯通孔32。贯通孔32的镀敷可以包括：在层28上方形成毯状晶种层(未示出)并且该晶种层延伸至开口30(图3)内，形成并且图案化光刻胶(未示出)，以及在晶种层的通过光刻胶中的开口暴露的部分上镀敷贯通孔32。然后去除光刻胶和晶种层的被光刻胶覆盖的部分。贯通孔32的材料可以包括铜、铝等。贯通孔32具有杆的形状。贯通孔32的顶视图形状可以是圆形、矩形、正方形、六边形等。
图5示出了器件管芯36的放置。相应的步骤示出为图23中示出的工艺流程图中的步骤314。通过管芯附接膜(DAF)45将器件管芯36粘合至介电层28，该管芯附接膜可以是粘合膜。器件管芯36可以是逻辑器件管芯，该器件管芯中包括逻辑晶体管。在一些示例性实施例中，器件管芯36设计为用于移动应用，并且可以使电源管理集成电路(PMIC)管芯、收发器(TRX)管芯等。
在一些示例性实施例中，金属支柱38(诸如铜柱)预形成为器件管芯36的最顶部部分，其中，金属支柱38电耦接至诸如器件管芯36中的晶体管的集成电路器件。根据本发明的一些实施例，聚合物填充相邻的金属支柱38之间的间隙以形成顶部介电层40，其中，顶部介电层40也可以位于下面的钝化层的顶部上，并且可以与或者可以不与下面的钝化层接触，其可以包括氮化硅、氮氧化硅、氧化硅或它们的多层。根据一些示例性的实施例，聚合物层40可以由PBO形成。
接下来，如图6所示，将成型材料44成型在器件管芯36上。相应的步骤示出为图23中示出的工艺流程图中的步骤316。成型材料44填充相邻的贯通孔32之间的间隙以及贯通孔32和器件管芯36之间的间隙。成型材料44可以包括成型料、成型底部填充物、环氧树脂或树脂。成型材料44的顶面比金属支柱38的顶端高。
还参考图6，实施诸如化学机械抛光(CMP)步骤或研磨步骤的平坦化以减薄成型材料44，直到暴露贯通孔32和金属支柱38。相应的步骤示出为图23中示出的工艺流程图中的步骤318。由于研磨，所以贯通孔32的顶端与金属支柱38的顶面基本齐平(共面)，并且与成型材料44的顶面基本共面。
参考图7，形成介电层46。相应的步骤示出为图23中示出的工艺流程图中的步骤320。根据本发明的一些实施例，介电层46由聚合物形成，该聚合物也可以是根据本发明的一些实施例的光敏介电材料。例如，介电层46可以由PBO、聚酰亚胺等形成。在可选的实施例中，介电层46由氮化硅、氧化硅等形成。在通篇说明书中，介电层46可选地称为底部RDL嵌入聚合物层。
参考图7，在光刻工艺中图案化介电层46。相应的步骤示出为图23中示出的工艺流程图中的步骤322。例如，在介电层46是由光敏材料形成的实施例中，光刻掩模48用于曝光。光刻掩模48包括允许光穿过的透明的部分和用于阻挡光的不透明的部分。然后实施曝光，其中，投射光(箭头)以使光敏介电层46曝光。如图8所示，在显影和烘焙工艺之后，形成开口50。
如图8所示，通过开口50暴露贯通孔32和金属支柱38。在随后的段落中，结构的位于释放层22上方的包括管芯36、贯通孔32和对应的RDL等(其中一些在随后的步骤中形成)的部分组合称为封装件100，该封装件包括多个封装件54。另外，划线52位于封装件54之间，并且底部RDL嵌入聚合物层46的边缘限定封装件54的边界。划线52是在随后管芯锯切工艺中锯片将穿过的区域。因此，RDL嵌入聚合物层46未延伸至划线52内，但是将位于封装件54中。作为图案化的结果，在划线52中暴露成型材料44。
图21示出了封装件54和划线52的顶视图。如图21所示，划线52形成为栅格图案以将封装件54分离。
接下来，参考图9，形成连接至金属支柱38和贯通孔32的再分布衬里(RDL)58。相应的步骤示出为图23中示出的工艺流程图中的步骤324。RDL 58也可以互连金属支柱38和贯通孔32。RDL 58包括位于介电层46上方的金属迹线(金属线)以及延伸至开口50(图8)内以电连接至贯通孔32和金属支柱38的通孔。根据本发明的一些实施例，在镀敷工艺中形成RDL 58，其中，每个RDL 58均包括晶种层(未示出)和位于晶种层上方的镀敷的金属材料。晶种层和镀敷的材料可以由相同材料或不同材料形成。RDL 58可以包括包含铝、铜、钨和它们的合金的金属或金属合金。在形成RDL 58之后，划线52中的开口50(图8)保持为不被RDL 58填充。
参考图10，例如，通过旋涂在RDL 58和介电层46上方形成聚合物层60。相应的步骤示出为图23中示出的工艺流程图中的步骤326。可以使用聚合物形成聚合物层60，该聚合物选自与介电层46的材料相同的候选材料。例如，聚合物层60可以包括PBO、聚酰亚胺等。在形成之后，聚合物60填充位于划线52中的开口50(图9)并且覆盖RDL 58。
接下来，还如图10所示，光刻掩模61放置在复合封装件100上方。然后实施曝光，其中，投射光(箭头)以使聚合物层60曝光。如图11所示，在显影和烘焙工艺之后，形成开口64(包括64A、64B和64C)。相应的步骤示出为图23中示出的工艺流程图中的步骤328。通过开口64C暴露RDL 58的衬垫部分，该开口为封装件54中离散的开口。开口64B也位于封装件54中，并且从聚合物层60的顶面延伸至介电/聚合物层46的顶面，并且因此通过开口64B暴露介电层46。根据一些实施例，如图21所示，开口64B形成邻近划线52的沟槽环，例如，其中，开口64B和相应的划线52之间的距离小于约100μm。此外，可以形成开口64B以环绕相应的封装件54中的相应的管芯36和导电部件，并且因此不与它们重叠。可选地陈述，根据本发明的一些实施例，管芯36和导电部件不在沟槽环64B下面直接延伸，并且被限制在由沟槽环64B环绕的区域中。
如图11所示，聚合物60的位于划线52中的部分比聚合物60的位于封装件54中的部分厚得多。结果，在图案化聚合物60的光刻工艺中，由于聚合物60的位于划线52中的底部部分曝光不充分，所以在图案化之后可能留下剩余物60'。在划线52中没有留下聚合物60的剩余物也是有可能的。应该理解，是否有剩余物60'留下受到包括层46和60的厚度和材料、暴露条件等各个因素的影响。
接下来，参考图12，形成RDL 66以连接至RDL 58。相应的步骤示出为图23中示出的工艺流程图中的步骤330。RDL 66也包括位于聚合物层60上方的金属迹线(金属线)以及延伸至开口64C(图11)内以电连接至RDL 58的通孔。RDL 66的材料和形成工艺可以与RDL 58的材料和形成工艺相似。沟槽环64B和划线52保持为不被RDL 66填充。
参考图13，例如，通过旋涂在RDL 66上方形成聚合物层68。相应的步骤示出为图23中示出的工艺流程图中的步骤332。聚合物层68在下文中称为顶部聚合物层。尽管示出的示例性实施例示出了三个介电(聚合物)层和对应的RDL，但是在其他实施例中，层的数量可以比示出的多或少。也可以使用聚合物形成聚合物层68，该聚合物可以选自与介电层46的材料相同的候选材料。例如，聚合物层68可以包括PBO、聚酰亚胺等。在形成之后，聚合物层68填充开口64A和64B(图12)并且覆盖RDL 66。
接下来，还如图13所示，图案化聚合物层68。相应的步骤示出为图23中示出的工艺流程图中的步骤334。光刻掩模70放置在复合封装件100上方。然后实施曝光，其中，投射光(箭头)以使聚合物层68曝光。如图14所示，在显影和烘焙工艺之后，形成开口72(包括72A、72B和72C)。通过开口72C暴露RDL 66的衬垫部分，该开口是封装件54中离散的开口。开口72B也位于封装件54中，并且从聚合物层68的顶面延伸至聚合物层60的顶面，并且因此通过开口72B暴露聚合物层60。根据一些实施例，开口72B形成邻近划线52的沟槽环(也参考图22)。此外，可以形成开口72B以环绕相应的封装件54中的相应的管芯36和导电部件，并且因此不与它们重叠。可选地陈述，根据本发明的一些实施例，封装件54中的管芯36和导电部件不在沟槽环72B下面直接延伸，并且被限制在由沟槽环72B环绕的区域中。在一些示例性实施例中，如图14所示，沟槽环72B形成在沟槽环64B(其被聚合物层68填充)的内侧上。
如图13所示，聚合物68的位于划线52中的部分比聚合物68的位于封装件54中的部分厚得多。结果，如图14所示，在图案化聚合物68的光刻工艺后，剩余部分68'(图14)留在划线52中。剩余部分68'的厚度可以大于、等于或小于聚合物层68的位于封装件54中的部分。
根据一些示例性实施例，沟槽环64B与最近的划线52的距离为D1。距离D1可以大于约10μm并且可以小于约50μm。沟槽环64B的宽度W1可以大于约10μm并且小于约50μm。沟槽环64B与沟槽环72B之间的距离D2可以在约10μm和约50μm之间的范围内。沟槽环72B的宽度W2也可以在约10μm和约50μm之间的范围内。
图15示出了根据一些示例性实施例的凸块下金属(UBM)74和电连接件76的形成。相应的步骤示出为图23中示出的工艺流程图中的步骤336。UBM 74的形成可以包括沉积和图案化。电连接件76的形成可以包括将焊球放置在UBM 74的暴露部分上以及然后回流焊球。在可选的实施例中，电连接件76的形成包括实施镀敷步骤以在RDL 66上方形成焊料区域以及然后回流焊料区域。电连接件76也可以包括金属支柱或者金属支柱和焊帽，其也可以通过镀敷来形成。
接下来，封装件100从载体20脱粘。可以通过将诸如UV光或激光的光投射到释放层22上以分解释放层22来实施该脱粘。在脱粘中，胶带(未示出)可以粘合至聚合物层68和电连接件76上。在随后的步骤中，从封装件100去除载体20和释放层22。图16中示出产生的结构。
如图16所示，实施管芯锯切步骤以将封装件100锯切成多个封装件54，每个封装件均包括器件管芯36和贯通孔32。锯片穿过的路径标示为路径67。相应的步骤示出为图23中示出的工艺流程图中的步骤338。图22示出了从封装件100锯切的一个封装件54的顶视图。应该理解，由于锯片的宽度通常小于图15所示的划线52的宽度，所以产生的封装件54可以包括原划线52的一小部分。
再次参考图16，在封装件100的锯切中，由于划线中的剩余物，所以相邻的介电/聚合物层46、60和/或68可以被锯穿。由于相邻的介电/聚合物层46、60和68与成型材料44之间的界面为薄弱部分，所以介电/聚合物层46、60和68中的上部的层可能从介电/聚合物层46、60和68中的下面的层以及成型材料44分层。分层趋向于通过界面扩展至封装件54内。通过形成沟槽环64B和72B，如果发生分层，将通过沟槽环停止分层。例如，假设分层发生在聚合物层46和60之间的界面处，并且通过该界面扩展，分层将结束在标示为63的位置处，该位置也是环。如果分层发生在聚合物层60和68之间的界面处，并且通过该界面扩展，分层将结束在标示为65的位置处，该位置也是环。
图16还示出了封装件54与另一封装件200的接合。根据本发明的一些实施例，通过焊料区域98实施接合，该焊料区域将RDL 26的金属衬垫部分连接至封装件200中的金属衬垫。根据本发明的一些实施例，封装件200包括器件管芯202，该器件管芯可以是诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。在一些示例性实施例中，存储器管芯也可以接合至封装件衬底204。
图21示出了封装件100和划线52的顶视图。如图21所示，沟槽环72B形成环绕器件管芯36、电连接件76以及RDL 58和66的环。沟槽环64B也形成环。根据本发明的一些实施例，如图21所示，沟槽环72B环绕沟槽环64B。在可选实施例(未示出)中，沟槽环72B可以被沟槽环64B环绕。图22中示出了锯切封装件100之后获得的封装件54。
图17至图20示出了根据可选实施例的封装件100(以及其中的封装件54)的截面图。在图17至图20的每幅图中，沟槽64B和72B均可以形成邻近封装件的相应边缘的全环。如图17所示，沟槽环64B和沟槽环72B彼此重叠，其中，沟槽环72B的宽度W2小于沟槽环64B的宽度W1。因此，沟槽环72B延伸至聚合物层68的延伸至沟槽环64B内的部分内。
图18示出了根据可选实施例的封装件100(以及其中的封装件54)的截面图。在这些实施例中，沟槽环64B和沟槽环72B也彼此重叠，其中，沟槽环72B的宽度W2大于沟槽环64B的宽度W1。因此，聚合物层68未延伸至沟槽环64B内。这些实施例中的沟槽环64B和72B合并为较大的沟槽环。
图19示出了根据可选实施例的封装件100(以及其中的封装件54)的截面图。在这些实施例中，没有沟槽环形成在聚合物层60中。在图11所示的步骤之后，当没有聚合物层60的剩余部分留在划线52中时，可以使用这些实施例，并且因此没有必要在聚合物层60中形成沟槽环。然而，随着形成更多的聚合物层，划线52中的沟槽变得越来越深，并且因此，诸如聚合物层68的上部聚合物层更可能具有剩余部分。因此，在这些实施例中，沟槽环72B形成在聚合物层68中。
图20示出了根据可选实施例的封装件100(以及其中的封装件54)的截面图。在这些实施例中，沟槽环64B和沟槽环72B彼此重叠，其中，沟槽环72B的宽度W2'小于沟槽环64B的宽度W1。因此，沟槽环72B延伸至聚合物层68的延伸至沟槽环64B内的部分内。另外，位于划线52的相对侧上的两个封装件的沟槽环72B延伸至划线52内并且合并在一起。结果，在锯切开封装件100之后的最后的结构中，沟槽环72B延伸至封装件54的边缘。
本发明的实施例具有一些有利的特征。沟槽环形成在InFO封装件的聚合物层中。沟槽环可以在封装件的锯切中用作分层停止件以防止聚合物层之间的分层扩展至封装件的内部内。本发明的实施例的一个有利特征是在形成用于UBM和RDL的开口的同时实现沟槽环的形成，并且因此不涉及附加的制造成本。
根据本发明的一些实施例，一种封装件包括器件管芯、环绕器件管芯的成型材料、以及位于器件管芯和成型材料上方的底部介电层，其中，成型材料的顶面与器件管芯的顶面基本齐平。多个RDL延伸至底部介电层内并且电耦接至器件管芯。顶部聚合物层位于底部介电层上方，其中，沟槽环穿过顶部聚合物层。沟槽环邻近封装件的边缘。封装件还包括延伸至顶部聚合物层内的UBM。
根据本发明的可选实施例，一种封装件包括器件管芯和环绕器件管芯的成型材料，其中，成型材料的顶面与器件管芯的顶面基本齐平。贯通孔穿过成型材料，其中，贯通孔的顶面与器件管芯的顶面基本共面。封装件还包括第一聚合物层，该第一聚合物层位于器件管芯、贯通孔和成型材料上方并且与器件管芯、贯通孔和成型材料接触。多个RDL延伸至第一聚合物层内以电耦接至器件管芯和贯通孔。第二聚合物层位于第一聚合物层和多个RDL上方，其中，第一沟槽环从第二聚合物层的顶面延伸至第一聚合物层的顶面。封装件还包括第三聚合物层，该第三聚合物层位于第二聚合物层上方并且与第二聚合物层接触，其中，第二沟槽环从第三聚合物层的顶面延伸至第二聚合物层的顶面。UBM延伸至第三聚合物层内。
根据本发明的又一可选实施例，一种方法包括：在成型材料中对多个器件管芯进行成型，并且平坦化多个器件管芯和成型材料，其中，器件管芯的顶面与成型材料的顶面齐平。该方法还包括：在多个器件管芯和成型材料上方形成第一聚合物层，并且第一聚合物层与多个器件管芯和成型材料接触，以及图案化第一聚合物层以形成多个第一开口，其中，通过多个第一开口暴露器件管芯的金属支柱。通过图案化第一聚合物层的步骤形成划线。该方法还包括：形成具有穿过第一聚合物层的通孔部分的多个再分布衬里，在第一聚合物层上方形成第二聚合物层，并且图案化第二聚合物层以形成多个第二开口和多个第一沟槽环，其中，多个第一沟槽环的每个均环绕多个器件管芯中的一个。多个第一沟槽环通过划线彼此分离。形成多个UBM以延伸至第二聚合物层内。
本发明实施例提供一种封装件，包括：器件管芯；成型材料，环绕所述器件管芯，其中，所述成型材料的顶面与所述器件管芯的顶面基本齐平；底部介电层，位于所述器件管芯和所述成型材料上方；多个再分布衬里(RDL)，延伸至所述底部介电层内并且电耦接至所述器件管芯；顶部聚合物层，位于所述底部介电层上方，沟槽环穿过所述顶部聚合物层，其中，所述沟槽环邻近所述封装件的边缘；以及凸块下金属(UBM)，延伸至所述顶部聚合物层内。
在一实施例中，所述沟槽环通过所述顶部聚合物层的一部分与所述封装件的边缘间隔开，所述顶部聚合物层的所述部分形成环绕所述沟槽环的环。
在一实施例中，所述沟槽环延伸至所述封装件的边缘。
在一实施例中，所述沟槽环延伸至所述底部介电层的顶面。
在一实施例中，封装件还包括：中间聚合物层，位于所述顶部聚合物层和所述底部介电层之间，附加的沟槽环穿过所述中间聚合物层。
在一实施例中，所述附加的沟槽环被所述顶部聚合物层填充。
在一实施例中，所述附加的沟槽环被所述顶部聚合物层完全填充。
在一实施例中，所述附加的沟槽环被所述顶部聚合物层部分填充。
在一实施例中，所述附加的沟槽环未被所述顶部聚合物层填充。
在一实施例中，封装件还包括：中间聚合物层，位于所述顶部聚合物层和所述底部介电层之间，其中，没有沟槽环形成在所述中间聚合物层中。
在一实施例中，封装件还包括：贯通孔，穿过所述成型材料，其中，所述贯通孔的顶面与所述器件管芯的顶面基本共面。
本发明实施例还提供一种封装件，包括：器件管芯；成型材料，环绕所述器件管芯，其中，所述成型材料的顶面与所述器件管芯的顶面基本齐平；贯通孔，穿过所述成型材料，其中，所述贯通孔的顶面与所述器件管芯的顶面基本共面；第一聚合物层，位于所述器件管芯、所述贯通孔和所述成型材料上方并且与所述器件管芯、所述贯通孔和所述成型材料接触；多个再分布衬里(RDL)，延伸至所述第一聚合物层内以电耦接至所述器件管芯和所述贯通孔；第二聚合物层，位于所述第一聚合物层和所述多个RDL上方，其中，第一沟槽环从所述第二聚合物层的顶面延伸至所述第一聚合物层的顶面；第三聚合物层，位于所述第二聚合物层上方并且与所述第二聚合物层接触，其中，第二沟槽环从所述第三聚合物层的顶面延伸至所述第二聚合物层的顶面；以及凸块下金属(UBM)，延伸至所述第三聚合物层内。
在一实施例中，所述第一沟槽环位于所述第二沟槽环和所述封装件的边缘之间。
在一实施例中，所述第一沟槽环停止在所述第一聚合物层的顶面上，并且所述第二沟槽环停止在所述第二聚合物层的顶面上。
在一实施例中，所述第一沟槽环被所述第三聚合物层填充。
本发明实施例还提供一种方法，包括：在成型材料中对多个器件管芯进行成型；平坦化所述多个器件管芯和所述成型材料，其中，所述器件管芯的顶面与所述成型材料的顶面齐平；在所述多个器件管芯和所述成型材料上方形成第一聚合物层，并且所述第一聚合物层与所述多个器件管芯和所述成型材料接触；图案化所述第一聚合物层以形成多个第一开口，通过所述多个第一开口暴露所述器件管芯的金属支柱，其中，通过图案化所述第一聚合物层形成划线；形成包括穿过所述第一聚合物层的通孔部分的多个再分布衬里；在所述第一聚合物层上方形成第二聚合物层；以及图案化所述第二聚合物层以形成多个第二开口和多个第一沟槽环，所述多个第一沟槽环的每个均环绕所述多个器件管芯中的一个，并且所述多个第一沟槽环通过所述划线彼此分离；以及形成延伸至所述第二聚合物层内的多个凸块下金属(UBM)。
在一实施例中，方法还包括：沿着所述划线锯切所述第一聚合物层、所述第二聚合物层和所述成型材料。
在一实施例中，方法还包括：在形成所述第一聚合物层之后并且在形成所述第二聚合物层之前，形成第三聚合物层，所述第三聚合物层形成在所述第一聚合物层上方；以及图案化所述第三聚合物层以形成多个第三开口和多个第二沟槽环，所述多个第二沟槽环的每个均环绕所述多个器件管芯中的一个，并且所述多个第二沟槽环通过所述划线彼此分离。
在一实施例中，所述第二聚合物层填充至所述多个第二沟槽环内。
在一实施例中，在所述成型材料中对多个贯通孔进行成型，并且，所述多个再分布衬里电连接至所述多个贯通孔。
以上论述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍的实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种封装件，包括：
器件管芯；
成型材料，环绕所述器件管芯，其中，所述成型材料的顶面与所述器件管芯的顶面基本齐平；
底部介电层，位于所述器件管芯和所述成型材料上方；
多个再分布衬里(RDL)，延伸至所述底部介电层内并且电耦接至所述器件管芯；
顶部聚合物层，位于所述底部介电层上方，沟槽环穿过所述顶部聚合物层，其中，所述沟槽环邻近所述封装件的边缘；以及
凸块下金属(UBM)，延伸至所述顶部聚合物层内。
2.根据权利要求1所述的封装件，其中，所述沟槽环通过所述顶部聚合物层的一部分与所述封装件的边缘间隔开，所述顶部聚合物层的所述部分形成环绕所述沟槽环的环。
3.根据权利要求1所述的封装件，其中，所述沟槽环延伸至所述封装件的边缘。
4.根据权利要求1所述的封装件，其中，所述沟槽环延伸至所述底部介电层的顶面。
5.根据权利要求1所述的封装件，还包括：中间聚合物层，位于所述顶部聚合物层和所述底部介电层之间，附加的沟槽环穿过所述中间聚合物层。
6.根据权利要求5所述的封装件，其中，所述附加的沟槽环被所述顶部聚合物层填充。
7.根据权利要求6所述的封装件，其中，所述附加的沟槽环被所述顶部聚合物层完全填充。
8.根据权利要求6所述的封装件，其中，所述附加的沟槽环被所述顶部聚合物层部分填充。
9.一种封装件，包括：
器件管芯；
成型材料，环绕所述器件管芯，其中，所述成型材料的顶面与所述器件管芯的顶面基本齐平；
贯通孔，穿过所述成型材料，其中，所述贯通孔的顶面与所述器件管芯的顶面基本共面；
第一聚合物层，位于所述器件管芯、所述贯通孔和所述成型材料上方并且与所述器件管芯、所述贯通孔和所述成型材料接触；
多个再分布衬里(RDL)，延伸至所述第一聚合物层内以电耦接至所述器件管芯和所述贯通孔；
第二聚合物层，位于所述第一聚合物层和所述多个RDL上方，其中，第一沟槽环从所述第二聚合物层的顶面延伸至所述第一聚合物层的顶面；
第三聚合物层，位于所述第二聚合物层上方并且与所述第二聚合物层接触，其中，第二沟槽环从所述第三聚合物层的顶面延伸至所述第二聚合物层的顶面；以及
凸块下金属(UBM)，延伸至所述第三聚合物层内。
10.一种方法，包括：
在成型材料中对多个器件管芯进行成型；
平坦化所述多个器件管芯和所述成型材料，其中，所述器件管芯的顶面与所述成型材料的顶面齐平；
在所述多个器件管芯和所述成型材料上方形成第一聚合物层，并且所述第一聚合物层与所述多个器件管芯和所述成型材料接触；
图案化所述第一聚合物层以形成多个第一开口，通过所述多个第一开口暴露所述器件管芯的金属支柱，其中，通过图案化所述第一聚合物层形成划线；
形成包括穿过所述第一聚合物层的通孔部分的多个再分布衬里；
在所述第一聚合物层上方形成第二聚合物层；以及
图案化所述第二聚合物层以形成多个第二开口和多个第一沟槽环，所述多个第一沟槽环的每个均环绕所述多个器件管芯中的一个，并且所述多个第一沟槽环通过所述划线彼此分离；以及
形成延伸至所述第二聚合物层内的多个凸块下金属(UBM)。
CN201510759360.4A 2015-03-16 2015-11-10 通过形成沟槽消除锯切引起的剥离 Active CN105990272B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562133770P 2015-03-16 2015-03-16
US62/133,770 2015-03-16
US14/713,935 US9589903B2 (en) 2015-03-16 2015-05-15 Eliminate sawing-induced peeling through forming trenches
US14/713,935 2015-05-15

Publications (2)

Publication Number Publication Date
CN105990272A true CN105990272A (zh) 2016-10-05
CN105990272B CN105990272B (zh) 2019-05-07

Family

ID=56852979

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510759360.4A Active CN105990272B (zh) 2015-03-16 2015-11-10 通过形成沟槽消除锯切引起的剥离

Country Status (5)

Country Link
US (5) US9589903B2 (zh)
KR (1) KR101962508B1 (zh)
CN (1) CN105990272B (zh)
DE (1) DE102015108684B4 (zh)
TW (1) TWI584423B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786350A (zh) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 半导体封装件和方法

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9589903B2 (en) 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
JP6640780B2 (ja) 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
US10522526B2 (en) 2017-07-28 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. LTHC as charging barrier in InFO package formation
US10453821B2 (en) * 2017-08-04 2019-10-22 Samsung Electronics Co., Ltd. Connection system of semiconductor packages
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US10790244B2 (en) 2017-09-29 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
DE102018122228B4 (de) * 2017-11-15 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integriertes Multichip-Fan-Out-Package sowie Verfahren zu dessen Herstellung
US11177201B2 (en) * 2017-11-15 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages including routing dies and methods of forming same
US10566301B2 (en) * 2017-11-17 2020-02-18 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10396053B2 (en) 2017-11-17 2019-08-27 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10607941B2 (en) * 2018-04-30 2020-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device
US11056459B2 (en) * 2018-08-14 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10522488B1 (en) 2018-10-31 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning polymer layer to reduce stress
WO2020129808A1 (ja) * 2018-12-21 2020-06-25 株式会社村田製作所 電子部品モジュールの製造方法及び電子部品モジュール
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 芯片封装结构及其制作方法
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
KR20220004152A (ko) * 2019-05-06 2022-01-11 쓰리엠 이노베이티브 프로퍼티즈 컴파니 전기 전도성 요소를 포함하는 패턴화된 물품
US11133282B2 (en) * 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
US11088094B2 (en) 2019-05-31 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Air channel formation in packaging process
KR20210023021A (ko) 2019-08-21 2021-03-04 삼성전자주식회사 반도체 패키지
KR20220079936A (ko) * 2019-10-11 2022-06-14 어플라이드 머티어리얼스, 인코포레이티드 정렬 벡터들을 비교하는 방법 및 다이 시스템
US11862594B2 (en) * 2019-12-18 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure with solder resist underlayer for warpage control and method of manufacturing the same
KR20210087337A (ko) 2020-01-02 2021-07-12 삼성전자주식회사 반도체 패키지와 이를 구비하는 전자 장치 및 반도체 패키지의 제조방법
KR102517379B1 (ko) 2020-02-14 2023-03-31 삼성전자주식회사 반도체 패키지의 제조 방법
KR20210141821A (ko) 2020-05-13 2021-11-23 삼성디스플레이 주식회사 디스플레이 장치
KR102610247B1 (ko) * 2020-11-11 2023-12-06 주식회사 네패스 반도체 패키지 및 이의 제조 방법
TWI775280B (zh) * 2021-01-20 2022-08-21 力晶積成電子製造股份有限公司 電容集成結構、電容單元及其製造方法
US11842935B2 (en) 2021-02-18 2023-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a reconstructed package substrate comprising substrates blocks
KR20220147922A (ko) 2021-04-28 2022-11-04 삼성전자주식회사 반도체 패키지
TWI829396B (zh) * 2022-10-21 2024-01-11 欣興電子股份有限公司 電路板結構及其製作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090115024A1 (en) * 2007-11-01 2009-05-07 Jeng Shin-Puu Seal ring structure with improved cracking protection and reduced problems
CN101615598A (zh) * 2008-06-26 2009-12-30 台湾积体电路制造股份有限公司 用于防止管芯切割引起的应力的保护密封环
US20130001776A1 (en) * 2011-06-28 2013-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Wafer Level Package
US20130300004A1 (en) * 2012-05-14 2013-11-14 Stats Chippac, Ltd. Semiconductor Device and Method of Controlling Warpage in Semiconductor Package

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8409926B2 (en) 2010-03-09 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer around semiconductor die
US9548240B2 (en) * 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
WO2011125277A1 (ja) 2010-04-07 2011-10-13 株式会社島津製作所 放射線検出器およびそれを製造する方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US20120326324A1 (en) * 2011-06-22 2012-12-27 Lee Hyungmin Integrated circuit packaging system with package stacking and method of manufacture thereof
US20120326300A1 (en) * 2011-06-24 2012-12-27 National Semiconductor Corporation Low profile package and method
US8643148B2 (en) 2011-11-30 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer structures and methods for forming the same
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US8871568B2 (en) * 2012-01-06 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and method of forming the same
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9337073B2 (en) * 2013-03-12 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3D shielding case and methods for forming the same
US20140264630A1 (en) * 2013-03-15 2014-09-18 Chao-Yuan Huang Integrated Structure
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9425121B2 (en) 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
US9589903B2 (en) 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090115024A1 (en) * 2007-11-01 2009-05-07 Jeng Shin-Puu Seal ring structure with improved cracking protection and reduced problems
CN101615598A (zh) * 2008-06-26 2009-12-30 台湾积体电路制造股份有限公司 用于防止管芯切割引起的应力的保护密封环
US20130001776A1 (en) * 2011-06-28 2013-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Wafer Level Package
US20130300004A1 (en) * 2012-05-14 2013-11-14 Stats Chippac, Ltd. Semiconductor Device and Method of Controlling Warpage in Semiconductor Package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786350A (zh) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 半导体封装件和方法
CN109786350B (zh) * 2017-11-15 2021-02-09 台湾积体电路制造股份有限公司 半导体封装件和方法
US11062978B2 (en) 2017-11-15 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11728249B2 (en) 2017-11-15 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method

Also Published As

Publication number Publication date
DE102015108684B4 (de) 2022-11-17
KR20160111308A (ko) 2016-09-26
US20160276284A1 (en) 2016-09-22
KR101962508B1 (ko) 2019-03-26
US11018091B2 (en) 2021-05-25
TWI584423B (zh) 2017-05-21
US9947626B2 (en) 2018-04-17
CN105990272B (zh) 2019-05-07
US20170170128A1 (en) 2017-06-15
US20190115304A1 (en) 2019-04-18
US10510678B2 (en) 2019-12-17
US9589903B2 (en) 2017-03-07
US10157854B2 (en) 2018-12-18
US20200111751A1 (en) 2020-04-09
US20180218983A1 (en) 2018-08-02
TW201642408A (en) 2016-12-01
DE102015108684A1 (de) 2016-09-22

Similar Documents

Publication Publication Date Title
CN105990272A (zh) 通过形成沟槽消除锯切引起的剥离
CN106057768B (zh) 具有不连续聚合物层的扇出pop结构
CN105321913B (zh) 器件管芯中的环形件结构
CN105895596B (zh) 通过调整PoP封装件中的开口尺寸来减少裂痕
CN105990291B (zh) 用于管芯探测的结构
KR101759770B1 (ko) 정렬 마크 설계를 위한 패키지 제조 방법
CN103515362B (zh) 堆叠式封装器件和封装半导体管芯的方法
CN106486383A (zh) 封装结构及其制造方法
KR102159213B1 (ko) 격자 패턴을 갖는 정렬 마크 및 그 형성 방법
CN105990290A (zh) 封装件中的非垂直贯通孔
CN106257644A (zh) 晶圆级封装件的切割
CN105225967B (zh) 封装半导体器件的方法和封装的半导体器件
TWI616958B (zh) 具有空腔之聚合物系半導體結構
CN103050486A (zh) 形成封装堆叠结构的工艺
CN105720018B (zh) 在缓冲层中具有开口的集成扇出结构
KR20210040341A (ko) Info 구조물 및 그 형성 방법
KR20220050121A (ko) 임베딩된 코어 프레임을 사용하는 패키지의 휨 제어
KR102303958B1 (ko) 패키징 공정에서의 에어 채널 형성

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant