CN100375232C - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN100375232C CN100375232C CNB2004100960178A CN200410096017A CN100375232C CN 100375232 C CN100375232 C CN 100375232C CN B2004100960178 A CNB2004100960178 A CN B2004100960178A CN 200410096017 A CN200410096017 A CN 200410096017A CN 100375232 C CN100375232 C CN 100375232C
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
半导体器件及其制造方法。通过研磨半导体晶片的背面(与形成多个器件并进而形成金属柱的一面相对)而将其减薄到预定厚度,然后在研磨后的一面形成由具有与半导体晶片接近的线性热膨胀系数的金属构成的金属层。进而,利用树脂密封半导体晶片,把金属突起焊接到金属柱(势垒金属层)的顶部,然后把半导体晶片分割成各个半导体器件。使用硅作为半导体晶片的材料,使用钨或钼作为构成金属层的金属。
Description
技术领域
本发明涉及半导体器件及其制造方法。更具体的,本发明涉及半导体器件及其制造方法,其涉及在形成有多个器件的晶片级封装中用于减薄晶片的背面研磨处理。
需要注意的是,在下面的描述中,除另外说明以外,“半导体器件”指晶片中形成的仍处于未分割状态的单独半导体元件(器件),以及从晶片分割出的单独半导体芯片(器件)。
背景技术
近年来,随着电子仪器和设备小型化的需求,人们试图减小电子仪器和设备中使用的半导体器件并提高其密度。因此,开发并制造了各自具有芯片级封装(CSP)结构的半导体器件,其中通过使半导体器件的形状尽量接近于半导体元件(半导体芯片)的形状而实现了微型化。
在具有CSP结构的典型半导体器件中,在半导体晶片的形成器件的一侧表面上形成用作保护膜的钝化膜(绝缘膜),在绝缘膜上形成绕线层(rerouting layer)(绕线图案(rerouting pattern)),用于通过在绝缘膜的预定位置形成的通孔把各个器件的配线层(电极焊盘)连接到封装外部。另外,在绕线层的端子形成部分中提供了金属柱(metal post),并用密封树脂密封了形成金属柱的一侧的整个表面(然而,露出金属柱的顶部)。而且,在金属柱的顶部连接了用作外部连接端子的金属突起(metalbump)。
对于被当作具有上述CSP结构的半导体器件的应用的各种装置,包括闪存、DRAM等等,未来的趋势是在分割成单独半导体芯片之前的阶段使晶片级封装变薄的需求不断增加。就此而论,一般进行研磨晶片背面的处理以实现上面所述的变薄。
在晶片级封装的传统制造工艺中,在初始阶段进行晶片背面研磨的处理。即,在半导体晶片上形成了多个器件之后的阶段(在晶片表面形成钝化膜(绝缘膜)之前的阶段),使用晶片背面研磨机,通过背面研磨(BG)工艺来减薄晶片,这是一种典型的方法,然后将晶片送到后续步骤。
与上述用于减薄晶片的BG工艺相关的技术包括,例如,在树脂密封后研磨晶片背面的技术,如日本特开2002-270720号公报或特开2002-231854号公报中所述。
如上所述,在晶片级封装的传统制造工艺中,在初始阶段进行晶片背面研磨加工,并且晶片需要在减薄了的状态(薄晶片状态)下送到所有的后续步骤。因此,在制造过程中很可能会出现称为“晶片破裂”的致命缺陷。
而且,在晶片减薄了的制作过程中,还存在整个晶片发生翘曲的问题。例如,当用模压树脂进行密封并进行热固(硬化)时,在模压树脂的热缩影响下,很薄的晶片会被拉向树脂层一侧,因而整个晶片发生翘曲。因此,晶片肯定会以翘曲状态送入树脂密封步骤之后的步骤(焊球放置、回流、切割等等)。因而,在传统技术中,存在减薄晶片级封装时整个晶片发生翘曲的缺点。
解决这个问题的一个可能的办法为,例如,通过真空压合在晶片背面形成薄膜层(例如,由环氧树脂、硅树脂、聚酰亚胺树脂等制成的用于生长(buildup)的层间绝缘膜)以纠正翘曲。在这种情况下,在形成该薄膜层之后(进行硬化处理之后)基本上无法将环氧树脂、硅树脂、聚酰亚胺的膜层剥离下来,从而留下来成为永久膜。因而,需要在连接有该永久膜(用于翘曲修正的膜层)的晶片上进行各种可靠性测试,包括晶片粘附性的可靠性测试。
然而,在这种情况下,存在如下问题:当把晶片最终切割成单独的半导体芯片(器件)时,由于切割时的机械冲击会使各个芯片产生破碎和裂纹等,破碎等会引起永久膜(薄膜层)和器件界面(芯片背面)之间的脱离。即,由于在进行各种可靠性测试之后在永久膜和器件界面之间发生脱离,所进行的可靠性测试作废。
而且,在上述形成膜状环氧树脂材料以修正翘曲的方法中,存在步骤数目较多的缺点。即,这种膜状环氧树脂材料通常具有两层结构,其中,在聚酯树脂的基材(PET膜)上覆上环氧树脂。为了在晶片背面形成这一膜状环氧树脂材料,需要如下四个步骤:在晶片背面层叠膜状环氧树脂材料的步骤、去除环氧树脂材料的多余外围部分的步骤、剥去保护环氧树脂的基材(PET膜)的步骤,以及热固化环氧树脂的步骤。
进而,在晶片背面形成的膜层(环氧树脂等的绝缘树脂层)即使在切割之后(把晶片划分成芯片之后)也会原样地保留下来成为永久膜。因此,各个芯片(封装)的背面覆盖有绝缘树脂层。这影响了整个封装的散热特性。
发明内容
本发明的一个目的为提供一种半导体器件及其制作方法,其中,在实现晶片级封装的减薄时,避免了晶片破裂,修正了晶片翘曲,并可以避免已进行的各种可靠性测试作废,还可以简化制作工艺,并改善散热特性。
为了实现上述目的,根据本发明的一个方面,提供了一种制造半导体器件的方法,包括以下步骤:在半导体晶片的形成多个器件的一侧表面上形成绝缘膜,该薄膜具有露出各个器件的电极焊盘的开口部分;在该绝缘膜上形成导体层,该导体层被构图成所需的形状以覆盖露出电极焊盘的开口部分;在导体层上形成保护层(resist layer),该保护层具有露出导体层的端子形成部分的开口部分;使用保护层作为掩模,在导体层的端子形成部分中形成金属柱;通过研磨半导体晶片的与形成金属柱的表面相对的一面,把半导体晶片减薄到预定厚度;去除保护层之后,在半导体晶片的研磨后的表面上形成金属层,该金属层由具有与半导体晶片接近的线性热膨胀系数的金属构成;使用密封树脂密封晶片的表面,并露出金属柱的顶部;在金属柱的顶部连接金属突起;以及把连接了金属突起的半导体晶片分割成各个器件。
根据这个方面的制造半导体器件的方法,直到形成金属柱的步骤,都可在较厚的状态(厚晶片状态)下处理半导体晶片。而且,即使在研磨与形成金属柱的一面相对的表面(晶片背面)从而减薄半导体晶片之后,紧接着在晶片背面上形成的金属层也可使半导体晶片在厚晶片状态下进入各个步骤。即,由于金属层起到加强半导体晶片的作用,并可使半导体晶片在厚晶片状态下进入几乎所有的步骤,所以可在实现晶片级封装的减薄的同时避免晶片破裂。
而且,在半导体晶片背面形成的金属层是由具有与半导体晶片接近的线性热膨胀系数的金属构成的,因此,在较后的阶段,当进行树脂密封和热处理时,金属层也起到修正半导体晶片翘曲的作用。即,金属层具有在树脂密封步骤之后保持半导体晶片平整的作用。
与传统技术中一样,该金属层最终留下来成为永久膜。然而,由于金属层与半导体晶片之间的热膨胀系数的差别较小,当晶片最终切割成芯片(器件)时,不易在切割中的机械冲击下发生破碎、裂纹等。结果,永久膜(金属层)和器件界面(芯片背面)之间几乎从不发生脱离。因此,不存在本发明之前的因发生脱离而导致切割之前进行的各种可靠性测试(晶片粘附性的可靠性测试等)作废的缺点。
而且,由于金属层在一个步骤中形成,与本发明之前的通过较多的步骤(层叠环氧树脂材料、去除多余外围部分、剥去保护基材,以及固化的四个步骤)形成环氧树脂等的绝缘树脂层的情况相比,简化了制作工艺。
另外,各个器件(封装)具有金属层在其背面露出的结构。因此,直到此时,与本发明之前的封装背面覆盖有环氧树脂等的绝缘树脂层的结构相比,可以有更好的散热效果。即,金属层具有散热器的功能。
另外,根据本发明的另一方面,提供了一种具有芯片级封装结构的半导体器件,其中,半导体晶片的一面由密封树脂密封,并露出金属突起,金属突起形成在这一面上,该半导体器件包括由具有与半导体晶片接近的线性热膨胀系数的金属制成的金属层,该金属层形成于半导体晶片的另一面上。
根据这个方面的半导体器件的结构,半导体晶片具有金属层在另一面(晶片背面)暴露的结构,因此,具有散热效果好的优点。
附图说明
图1的剖面示意图示出了根据本发明一个实施例的具有CSP结构的半导体器件的构造;
图2A到2D的剖面图示出了图1所示半导体器件的制作工艺的步骤示例;
图3A到3C的剖面图示出了图2A到2D所示步骤之后的步骤;
图4A到4D的剖面图示出了图3A到3C所示步骤之后的步骤;
图5A到5D的剖面图(其中一部分为透视图)示出了图4A到4D所示步骤之后的步骤;以及
图6的表示出了与其它金属对比,构成图1所示半导体器件中的金属层的各种金属的物理特性。
具体实施方式
图1示出了根据本发明一个实施例的具有CSP结构的半导体器件的剖面结构。
在图1中,10指示根据本实施例的半导体器件(CSP),11指示其中形成了多个器件的硅(Si)衬底。硅衬底11是通过切割(分割)以后将描述的半导体(硅)晶片而得到的部分。还有,12指示电极焊盘,各个电极焊盘由器件上形成的绕线图案的部分区域界定;13指示硅衬底11的表面(附图所示示例中的上表面)上形成的用作保护膜的钝化膜;14指示钝化膜13上形成的绝缘膜(聚酰亚胺树脂层);15指示通过构图而在绝缘膜14上形成的具有所需形状从而覆盖露出电极焊盘12的开口的薄金属膜(供电层/电镀基膜);16指示薄金属膜15上形成的绕线层;17指示在绕线层16的端子形成部分中形成的金属柱;18指示在金属柱17顶端上形成的势垒金属层(barrier metal layer);19指示硅衬底11的背面(附图所示例子的下表面)上形成的金属层;20指示密封树脂层,其形成为覆盖硅衬底11上形成金属柱17的整个表面(然而,露出金属柱17(势垒金属层18)的顶部);以及21指示金属突起(本实施例中的焊料突起),它用作连接到金属柱17(势垒金属层18)露出的顶部上的外部连接端子。
除了如后所述的防止晶片破裂的加强作用之外,硅衬底11背面上形成的金属层19还具有修正作用(翘曲修正作用),使得在进行热处理时(例如密封树脂的硬化等)不会发生晶片翘曲。此处未描述各个部件(包括金属层19)的材料和厚度,但是在下面的制造方法中会在适当的地方进行解释。
以下将参考示出其制造工艺步骤的图2A到5D,描述根据本实施例的具有CSP结构的半导体器件10。需要注意的是,各个附图(图5D除外)所示的剖面结构示出了图1所示剖面结构放大后的一部分(左侧部分)。
首先,在第一步(图2A),使用众所周知的方法制备形成有多个器件的晶片30。即,在具有预定厚度(例如,在晶片具有8英寸直径的情况下,大约725微米的厚度)的晶片上进行所需的器件处理之后,在晶片的一面(附图所示例子的上表面)上形成由氮化硅(SiN)、磷硅玻璃(PSG)等构成的用作保护膜的钝化膜13,并去除与电极焊盘12对应的部分钝化膜13,各个电极焊盘12由相应器件上形成所需图案的铝(Al)配线层的部分区域界定(即,在钝化膜13的相关部分上开口)。利用例如YAG激光器、准分子激光器等,通过激光处理实现钝化膜13的开口。从而,如附图所示,得到了表面被钝化膜13覆盖并且露出电极焊盘12的晶片30。
在下一步(图2B),在晶片30的钝化膜13上形成绝缘膜14。例如,在通过光刻在晶片30上形成光敏聚酰亚胺树脂并对聚酰亚胺树脂进行软烤(预烤)之后,使用掩模(未示出)进行曝光和显影(对聚酰亚胺树脂层进行构图),进而,进行硬烤(曝后烤),从而形成如图所示在预定位置具有开口部分VH的绝缘膜(聚酰亚胺树脂层)14。此时,根据电极焊盘12的形状进行聚酰亚胺树脂层的构图。因此,如图所示,去除了与电极焊盘12对应的部分的聚酰亚胺树脂层14,由此,形成延伸到电极焊盘12的通孔(开口部分VH)。
在下一步(图2C),通过溅射在形成有绝缘膜(聚酰亚胺树脂层)14的整个表面上形成薄金属膜15。薄金属膜15具有两层结构,包括构成接触金属层的铬(Cr)层或者钛(Ti)层以及叠在接触金属层上的铜(Cu)层。可通过溅射在整个表面上淀积Cr或者Ti(接触金属层:Cr层或者Ti层),然后通过溅射在其上淀积Cu(Cu层),从而形成薄金属层15。如上所述的薄金属层15可用作以后进行的绕线步骤以及金属柱形成步骤所必须的电解电镀中的电镀基膜(供电层)。
在下一步(图2D),在对薄金属层15的表面(Cu层表面)进行脱水烤(dehydro-baking)以及施加液态光刻胶并烘干之后,使用掩模(未示出)进行曝光和显影(光刻胶构图),从而形成保护层R1。光刻胶的构图是根据下一步将形成的绕线图案的形状进行的。
在下一步(图3A),利用薄金属15作为供电层对薄金属15的表面进行Cu的电解电镀,并利用构图后的保护层R1作为掩模形成Cu绕线层(绕线图案)16。
在下一步(图3B),例如,使用含有有机溶剂的剥离剂,剥离和去除光刻胶(保护层R1)。
在下一步(图3C),在清洁薄金属膜15的表面和绕线层16的表面之后,在其上粘贴光敏干膜(厚度大约为100μm),进而,使用掩模(未示出)进行曝光和显影(干膜构图),从而形成保护层R2。这一干膜的构图是根据下一步骤将要形成的金属柱的形状进行的。
在下一步(图4A),如先前一样,使用薄金属膜15作为供电层在绕线层16的表面上电解电镀Cu,从而使用构图后的保护层R2作为掩模,在绕线层16的端子形成部分中形成Cu接线柱(金属柱)17。和干膜(保护层R2)的厚度一样,Cu接线柱17的高度约100微米。
接下来,通过电解电镀在Cu接线柱17的顶端形成势垒金属层18。势垒金属层18(Ni/Pd/Au)可通过,例如,利用Cu接线柱17作为供电层在Cu接线柱17的表面镀上镍(Ni),以提高粘附性,再在该Ni层的表面上镀钯(Pd)以提高电导率,然后在该Pd层的表面上镀金(Au)来形成。在这种情况下,可以不提供Pd层而直接在Ni层上形成Au层(Ni/Au)。此时,形成绕线层的一侧表面(附图所示例子的上表面)通过Cu接线柱17(势垒金属层18)的表面和干膜(保护层R2)的表面而变得基本上平坦。
在下一步(图4B),利用众所周知的研磨机研磨晶片的背面(附图所示例子的下表面),从而把晶片30减薄到预定厚度(例如,大约250微米到300微米)。此时,由于先前步骤制造的结构的图案表面(上表面)已经基本上平坦,在研磨前夹持相关结构时易于卡紧图案表面。因此,可以在卡紧状态下研磨晶片30的背面,直到达到图中箭头所表示的预定厚度。
在下一步(图4C),利用碱性化学溶液,例如,氢氧化钠(NaOH)溶液、单乙醇胺溶液等,剥离并去除干膜(保护层R2)
在下一步(图4D),通过湿法刻蚀去除露出的电镀基膜(薄金属膜15)。即,利用溶解Cu的腐蚀剂去除薄金属膜15的上部的Cu层,然后,利用溶解Cr或者Ti的腐蚀剂去除下部的接触金属层(Cr层或Ti层)。从而,如图所示,露出绝缘膜(聚酰亚胺树脂层)14。此后,进行预定的表面清洁等。
附带地,当使用溶解Cu的腐蚀剂时,好像也去除了构成绕线层16的Cu而破坏了绕线图案。然而,实际上不存在这个问题。原因如下:如前所述,由于薄金属膜15的上部是利用Cu通过溅射形成的,所以上部的厚度在微米或更小的量级上(大约0.5微米),而绕线层16是通过Cu电解电镀形成的,绕线层16的膜厚至少为大约10微米;因此,即使完全去除了薄金属膜15的Cu时,在绕线层16(Cu)中也只去除了其表面部分,而绕线图案不会被破坏。
在下一步(图5A),为了克服晶片破裂和晶片翘曲,在晶片30的背面上形成高应力强度的金属层19。金属层19可利用溅射或汽相淀积形成。
金属层19所需的条件如下:与晶片30相近的线性热膨胀系数;高弹性模量;高热导性。例如,参考图6所示各种金属的物理特性表,最好使用具有比较接近α≈2.6(K-1)(即接近晶片30的材料硅(Si)的线性热膨胀系数)的线性热膨胀系数的金属:例如,线性热膨胀系数α≈4.5(K-1)的钨(W),线性热膨胀系数α=3.7至5.3(K-1)的钼(Mo),等等。由于与其它代表性的金属相比,钨(W)和钼(Mo)的线性热膨胀系数很小,因此与晶片(Si)背面的粘附性应该是很好的。而且,钨(W)和钼(Mo)具有比其它代表性金属大一个数量级的弹性模量(E),并且具有次于铜(Cu)和金(Au)但和铝(Al)相当的较高热导率。
在下一步(图5B),利用密封树脂(形成密封树脂层20)进行密封,从而覆盖晶片30的形成有Cu接线柱17的一侧的整个表面(然而,露出Cu接线柱17(势垒金属层18)的顶部)。例如,这可以如下所述地进行。
第一,制备包括单独的上模和下模的密封模并加热到预定温度(大约175℃)。接着,在上模上粘附树脂膜,把晶片30放置在下模的凹部中,并在其上放置片状的高粘性热固树脂(例如环氧树脂)作为密封树脂。然后,通过密封模的热量并加压(大约3分钟),热固树脂熔化并扩展到晶片的整个表面,将晶片30保持在模具中,对热固树脂进行固化处理(大约4小时)。此后,从模具中取出晶片30。此时,由于晶片30已经与树脂膜结合为一体,因而从晶片30上剥离下树脂膜。从而得到了表面覆盖有密封树脂层20并且露出Cu接线柱17(势垒金属层18)的顶部的晶片30。
在下一步(图5C),在Cu接线柱17(势垒金属层18)露出的顶部上施加用作表面处理剂的焊剂之后,在大约240℃到260℃的温度下,通过回流在其上放置并固定用作外部连接端子的焊球(焊料突起21的焊接)。此后,清洗表面以去除焊剂。
在最后一步(图5D),利用切割机等(附图所示例子中的切割机刀片BL)切割在前一步骤中焊接了焊料突起21的晶片30(包括绝缘膜14、金属层19和密封树脂层20)并分割成单独的芯片(器件)。尽管未在附图特别示出,在晶片30的形成了金属层19的一侧表面粘结在切割带(dicing tape)上的状态下,把焊接了焊料突起21的晶片30放置在由切割架(dicing frame)支撑的切割带上,利用切割机的刀片BL沿着界定器件区域的线切割晶片30,然后拾取切割和分割得到的芯片(器件)。从而,制造了根据本实施例的具有CSP结构的半导体器件10(图1)。
如上所述,根据本实施例的具有CSP结构的半导体器件10(图1)及其制造方法(图2A到图5D),可在厚状态(在此为大约725微米的厚晶片状态)下处理晶片30,直到形成Cu接线柱17和势垒金属层18的步骤(图4A)。而且,即使在通过背部研磨(在剥去保护层R2并去除露出的薄金属膜15之后)减薄晶片30之后,紧接着在晶片背面形成的金属层19也使得晶片30可以在厚晶片状态下进入各个步骤。即,由于金属层19起到加强晶片30的作用,使得晶片30可以在厚晶片状态下进入几乎所有的步骤,因此可以防止在实现晶片级封装的减薄时发生传统技术中的“晶片破裂”。
而且,在晶片30背面形成的金属层19是由线性热膨胀系数与晶片30接近的金属(例如,钨(W)、钼(Mo)等)制成的,因此,可以避免在后面的步骤(图5B)中利用模压树脂及其热固(固化)进行密封时,晶片30在模压树脂的热缩效应下被拉向树脂层20。即,金属层19起到修正晶片30翘曲以及在树脂密封之后保持晶片30平整的作用。
与此相关,在传统技术中与金属层19(翘曲修正层)对应的是由环氧树脂等热固树脂形成的树脂膜层。在树脂膜层(翘曲修正层)和晶片(硅)的线性热膨胀系数之间存在较大的差异。因此,存在如下问题:由于切割时的机械冲击容易发生破碎等,这会引起树脂膜层和器件界面(芯片背面)之间的脱离。
与此相反,在本实施例中,在晶片背面形成的金属层19留下来成为永久膜。然而,由于金属层19(翘曲修正层)与晶片30(硅)之间的线性热膨胀系数的差异较小(图6),不易在切割中的机械冲击下发生破碎等。结果,金属层19和器件界面(芯片背面)之间几乎从不发生脱离。因此,不存在本发明之前的因发生脱离而导致切割之前进行的各种可靠性测试(晶片粘附性的可靠性测试等)作废的缺点。
而且,由于金属层19是通过溅射或气相淀积而在一个步骤中形成的,因此,与本发明之前的通过较多数目的步骤(层叠环氧树脂材料、去除多余外围部分、剥去保护基材,以及热固化的四个步骤)形成环氧树脂等的绝缘树脂层的情况相比,简化了制作工艺。
而且,各个器件(具有图1所示CSP结构的半导体器件10)具有金属层19在其背面露出的结构,因此,与本发明之前的封装背面覆盖有环氧树脂等绝缘树脂层的结构相比,具有散热效果方面的优点。即,金属层19具有散热器的功能。
在上述的实施例中,是在形成Cu接线柱17和势垒金属层18之后立即进行晶片30的背面研磨(图4B)。然而,晶片背面研磨的时间当然不限制于上述时间。关键的仅仅是在进行背面研磨之前的一刻,晶片表面基本上是平坦的,并且最晚到晶片级封装的制造处理。例如,可在形成绕线层16(图3A)之后立即进行晶片背面研磨。
还有,在上述的实施例中,在图2A的步骤中,在晶片一侧提供了用作保护膜的钝化膜13。然而,在一些情况下,可由后续步骤(图2B的步骤)中形成的绝缘膜(聚酰亚胺树脂层)14来提供钝化膜的功能,而不提供钝化膜13。做为选择,相反,可只提供钝化膜13而不提供绝缘膜14。而且,尽管在图2B的步骤中使用光敏聚酰亚胺树脂作为晶片30表面上的绝缘膜14,但是用于该绝缘膜的材料当然不限制于光敏树脂。例如,可使用非光敏聚酰亚胺树脂、环氧树脂等树脂。
Claims (6)
1.一种制造半导体器件的方法,包括以下步骤:
在半导体晶片的形成多个器件的一侧表面上形成绝缘膜,所述绝缘膜具有露出各个器件的电极焊盘的开口部分;
在所述绝缘膜上形成导体层,所述导体层被构图成所需的形状以覆盖露出电极焊盘的开口部分;
在所述导体层上形成保护层,所述保护层具有露出所述导体层的端子形成部分的开口部分;
使用所述保护层作为掩模,在所述导体层的端子形成部分中形成金属柱;
通过研磨所述半导体晶片的与形成所述金属柱的表面相对的一面,把所述半导体晶片减薄到预定厚度;
去除所述保护层之后,在所述半导体晶片的研磨后的表面上形成金属层,所述金属层由具有与所述半导体晶片接近的线性热膨胀系数的金属构成;
使用密封树脂密封所述半导体晶片的表面,并露出所述金属柱的顶部;
在所述金属柱的顶部焊接金属突起;以及
把焊接了金属突起的半导体晶片分割成各个器件。
2.根据权利要求1所述的方法,其中所述的金属层是通过溅射和气相淀积中的任意一种形成的。
3.根据权利要求1所述的方法,其中使用硅作为所述半导体晶片的材料,并且使用钨和钼中的任意一种作为构成所述金属层的金属。
4.根据权利要求1所述的方法,进一步包括在形成所述金属柱的步骤和减薄所述半导体晶片的步骤之间,在所述金属柱的顶部形成势垒金属层的步骤。
5.一种半导体器件,其具有芯片级封装结构,其中半导体晶片的一侧由密封树脂密封,并露出金属突起,该金属突起形成于所述的一侧,所述的半导体器件包括由具有与所述半导体晶片接近的线性热膨胀系数的金属制作的金属层,该金属层形成于所述半导体晶片的另一侧。
6.根据权利要求5所述的半导体器件,其中使用硅作为所述半导体晶片的材料,并且使用钨和钼中的任意一种作为构成所述金属层的金属。
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JPJP2003393695 | 2003-11-25 | ||
JP2003393695A JP3929966B2 (ja) | 2003-11-25 | 2003-11-25 | 半導体装置及びその製造方法 |
JP2003393695 | 2003-11-25 |
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US (2) | US7417311B2 (zh) |
JP (1) | JP3929966B2 (zh) |
KR (1) | KR101043313B1 (zh) |
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US20050112800A1 (en) | 2005-05-26 |
TW200524025A (en) | 2005-07-16 |
US7468292B2 (en) | 2008-12-23 |
KR101043313B1 (ko) | 2011-06-22 |
JP2005158929A (ja) | 2005-06-16 |
KR20050050570A (ko) | 2005-05-31 |
US20070032066A1 (en) | 2007-02-08 |
US7417311B2 (en) | 2008-08-26 |
JP3929966B2 (ja) | 2007-06-13 |
TWI371061B (en) | 2012-08-21 |
CN1630029A (zh) | 2005-06-22 |
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