CN106653699B - 一种ic裸芯片组的互连技系统集成方法 - Google Patents

一种ic裸芯片组的互连技系统集成方法 Download PDF

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CN106653699B
CN106653699B CN201610949908.6A CN201610949908A CN106653699B CN 106653699 B CN106653699 B CN 106653699B CN 201610949908 A CN201610949908 A CN 201610949908A CN 106653699 B CN106653699 B CN 106653699B
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bottom plate
bare chip
integrated circuit
circuit board
interconnection
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CN106653699A (zh
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杨斌
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Jiangsu Jixiangxing Intelligent Technology Co ltd
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Jiangsu Jixiangxing Intelligent Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83948—Thermal treatments, e.g. annealing, controlled cooling

Abstract

本发明公开了一种IC裸芯片组的互连技系统集成方法。包括如下步骤：步骤一，选用一底板，并在一底板的表面均布涂覆有导电胶；步骤二，把集成电路的裸芯片均布排列在底板上，将集成电路的裸芯片的引脚与底板上的导电胶配合，形成集成板；步骤三，将步骤二制成的集成板烘烤，烘干；步骤四，通过半导体芯片的光刻加工该集成电路的裸芯片与底板的互连。本发明针对集成电路裸芯片在电路板上集成，通过将集成电路裸芯片集中固定在一底板上，然后通过半导体芯片的光刻加工方法将不同集成电路裸芯片之间的线路进行连接，充分降低了电路板的结构面积，提高电路板的制作过程，降低制造成本。

Description

一种IC裸芯片组的互连技系统集成方法
技术领域
本发明属于系统集成技术领域，特别是涉及一种IC裸芯片组的互连技系统集成方法。
背景技术
集成电路的高密度封装难题已成为各种便携式电子产品的瓶颈,严重制约着手机、MP4等电子产品的发展。目前电子整机中,电路板上的集成电路芯片之间的互连是通过印刷电路板(PCB)上的金属布线来完成的。它需要先通过封装和焊接将IC芯片上的压焊点(PAD)和印刷。
发明内容
本发明的目的在于提供一种IC裸芯片组的互连技系统集成方法，通过将集成电路裸芯片集中固定在一底板上，然后通过半导体芯片的光刻加工方法将不同集成电路裸芯片之间的线路进行连接，充分降低了电路板的结构面积，提高电路板的制作过程，降低制造成本。
为解决上述技术问题，本发明是通过以下技术方案实现的：
本发明为一种IC裸芯片组的互连技系统集成方法，包括如下步骤：
步骤一，选用一底板，并在一底板的表面均布涂覆有导电胶；
步骤二，把集成电路的裸芯片均布排列在底板上，将集成电路的裸芯片的引脚与底板上的导电胶配合，形成集成板；
步骤三，将步骤二制成的集成板烘烤，烘干；
步骤四，通过半导体芯片的光刻加工该集成电路的裸芯片与底板的互连。
优选地，所述底板的表面复合有一层金属导电层。
本发明具有以下有益效果：
本发明针对集成电路裸芯片在电路板上集成，通过将集成电路裸芯片集中固定在一底板上，然后通过半导体芯片的光刻加工方法将不同集成电路裸芯片之间的线路进行连接，充分降低了电路板的结构面积，提高电路板的制作过程，降低制造成本。
当然，实施本发明的任一产品并不一定需要同时达到以上所述的所有优点。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明的一种IC裸芯片组的互连技系统集成方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
请参阅图1所示，本发明为一种IC裸芯片组的互连技系统集成方法，包括如下步骤：
步骤一，选用一底板，并在一底板的表面均布涂覆有导电胶；该底板采用电路板。
步骤二，把集成电路的裸芯片均布排列在底板上，将集成电路的裸芯片的引脚与底板上的导电胶配合，形成集成板；
步骤三，将步骤二制成的集成板烘烤，烘干；
步骤四，通过半导体芯片的光刻加工该集成电路的裸芯片与底板的互连，将集成电路的裸芯片之外的底板切除。
其中，底板的表面复合有一层金属导电层。
值得注意的是，上述系统实施例中，所包括的各个单元只是按照功能逻辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可；另外，各功能单元的具体名称也只是为了便于相互区分，并不用于限制本发明的保护范围。
另外，本领域普通技术人员可以理解实现上述各实施例方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，相应的程序可以存储于一计算机可读取存储介质中，所述的存储介质，如ROM/RAM、磁盘或光盘等。
以上公开的本发明优选实施例只是用于帮助阐述本发明。优选实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施方式。显然，根据本说明书的内容，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地理解和利用本发明。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (1)

1.一种IC裸芯片组的互连系统集成方法，其特征在于，包括如下步骤：
步骤一，选用一底板，并在一底板的表面均布涂覆有导电胶，所述底板的表面复合有一层金属导电层；
步骤二，把集成电路的裸芯片均布排列在底板上，将集成电路的裸芯片的引脚与底板上的导电胶配合，形成集成板；
步骤三，将步骤二制成的集成板烘烤，烘干；
步骤四，通过半导体芯片的光刻加工该集成电路的裸芯片与底板的互连。
CN201610949908.6A 2016-10-26 2016-10-26 一种ic裸芯片组的互连技系统集成方法 Active CN106653699B (zh)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102637608A (zh) * 2011-02-10 2012-08-15 新科金朋有限公司 半导体器件和形成用于3d fo-wlcsp的垂直互连结构的方法

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* Cited by examiner, † Cited by third party
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US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102637608A (zh) * 2011-02-10 2012-08-15 新科金朋有限公司 半导体器件和形成用于3d fo-wlcsp的垂直互连结构的方法

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