TWI622142B - 晶片封裝體以及晶片封裝方法 - Google Patents

晶片封裝體以及晶片封裝方法 Download PDF

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Publication number
TWI622142B
TWI622142B TW105136156A TW105136156A TWI622142B TW I622142 B TWI622142 B TW I622142B TW 105136156 A TW105136156 A TW 105136156A TW 105136156 A TW105136156 A TW 105136156A TW I622142 B TWI622142 B TW I622142B
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Taiwan
Prior art keywords
layer
wafer
packaging
mask
chip
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TW105136156A
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English (en)
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TW201818519A (zh
Inventor
王朝仁
張志嘉
何家充
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財團法人工業技術研究院
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Priority to TW105136156A priority Critical patent/TWI622142B/zh
Priority to CN201611160960.XA priority patent/CN108074877B/zh
Priority to US15/394,814 priority patent/US10090272B2/en
Application granted granted Critical
Publication of TWI622142B publication Critical patent/TWI622142B/zh
Publication of TW201818519A publication Critical patent/TW201818519A/zh

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Abstract

一種晶片封裝體，其包括至少一晶片、第一封裝層、重佈線層以及第二封裝層。所述至少一晶片具有主動面、背面以及多個側壁面。第一封裝層包覆側壁面。第一封裝層具有第一表面以及第二表面。重佈線層配置在所述至少一晶片的主動面以及第一封裝層的第一表面上。第二封裝層配置在所述至少一晶片的背面以及第一封裝層的第二表面上，其中第二封裝層的熱膨脹係數小於第一封裝層的熱膨脹係數。製造此晶片封裝體的方法亦被提出。

Description

晶片封裝體以及晶片封裝方法
本發明是有關於一種半導體元件及其製作方法，且特別是有關於一種晶片封裝體以及晶片封裝方法。
由於消費性電子產品對於可攜式(Portability)及多功能(Multi-function)之需求，迫使半導體元件朝小尺寸、高性能及低成本發展。晶圓級封裝(Wafer Level Package, WLP)因具備小尺寸封裝之優勢，恰好滿足可攜式電子產品之市場趨勢。在晶圓級封裝的技術中，扇出板型晶圓級封裝(Fan Out Panel-Level-Package, FO-PLP)以大面積板型基板承載晶片並搭配重佈線層，可大幅增加產能並降低封裝成本，而成為趨勢技術之一。
目前扇出板型晶圓級封裝主要採用兩種製程。一種是先以封裝膠體材料將晶片包覆後，再製作重佈線層。另一種是先製作重佈線層，再使晶片與重佈線層電性連接，最後才形成封裝膠體。然而，上述兩種製程在大面積板型基板上均容易因膜層間及膜層與晶片間熱膨脹係數差異及成型過程的內應力差異而產生不平整(non-planarity)、對位(alignment)精確度及翹曲(warpage)等問題。承上述，如何改善不平整、對位精確度及翹曲等問題，實為目前研發人員亟欲解決的問題。
本發明提供一種晶片封裝體以及多種晶片封裝方法。
本發明的一實施例的一種晶片封裝體包括至少一晶片、第一封裝層、重佈線層以及第二封裝層。所述至少一晶片具有主動面、與主動面相對的背面以及多個連接主動面與背面的側壁面。第一封裝層包覆所述至少一晶片的側壁面，其中第一封裝層具有第一表面以及與第一表面相對的第二表面。重佈線層配置在所述至少一晶片的主動面以及第一封裝層的第一表面上，且重佈線層與所述至少一晶片電性連接。第二封裝層配置在所述至少一晶片的背面以及第一封裝層的第二表面上，其中第二封裝層的熱膨脹係數小於第一封裝層的熱膨脹係數。
本發明的一實施例的一種晶片封裝方法包括以下步驟。於載板上設置至少一晶片。所述至少一晶片具有主動面、與主動面相對的背面以及多個連接主動面與背面的側壁面，其中主動面位於背面與載板之間。於載板上形成第一封裝層。第一封裝層包覆所述至少一晶片的側壁面，以暴露出所述至少一晶片的主動面以及背面。於第一封裝層以及所述至少一晶片的背面上形成第二封裝層，其中第二封裝層的熱膨脹係數小於第一封裝層的熱膨脹係數。使所述至少一晶片以及第一封裝層自載板脫離，以暴露出所述至少一晶片的主動面。於第一封裝層以及所述至少一晶片的主動面上形成重佈線層，且重佈線層與所述至少一晶片電性連接。
本發明的一實施例的一種晶片封裝方法包括以下步驟。於載板上形成重佈線層。於重佈線層上設置至少一晶片。所述至少一晶片與重佈線層電性連接且具有主動面、與主動面相對的背面以及多個連接主動面與背面的側壁面，其中主動面位於背面與重佈線層之間。於重佈線層上形成第一封裝層。第一封裝層包覆所述至少一晶片的側壁面，以暴露出所述至少一晶片的背面。於第一封裝層以及所述至少一晶片的背面上形成第二封裝層，其中第二封裝層的熱膨脹係數小於第一封裝層的熱膨脹係數。使重佈線層自載板脫離。
在本發明的實施例中，晶片可位於第一封裝層的應力釋放孔，而有助於將第一封裝層的應力釋放。此外，藉由使第二封裝層的熱膨脹係數小於第一封裝層的熱膨脹係數，可降低第二封裝層與晶片的熱膨脹係數差異。本發明的實施例可有助於改善不平整、對位精確度及翹曲等問題，進而具有良好的產能及封裝良率。
為讓本發明能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1G是依照本發明的第一實施例的一種晶片封裝體的製作流程的剖面示意圖。請參照圖1A，於載板CP上設置至少一晶片110。載板CP可以是玻璃基板或陶瓷基板，但不以此為限。所述至少一晶片110具有主動面SA、背面SB以及多個側壁面SC，其中背面SB與主動面SA相對，且側壁面SC連接主動面SA與背面SB。
在本實施例中，於載板CP上設置所述至少一晶片110之前，可預先於載板CP上形成離型層DB，使所述至少一晶片110透過離型層DB而暫時地固定在載板CP上，且所述至少一晶片110以覆晶方式覆於離型層DB上，使得主動面SA位於背面SB與載板CP之間。
請參照圖1B，於載板CP上形成第一封裝層120。第一封裝層120的材料可包括彈性材料、熱塑性材料、熱固性材料、複合材料、矽酮(Silicone)或其他合適的樹脂，例如是環氧樹脂或含環氧樹脂的複合材料，但不以此為限。
第一封裝層120包覆所述至少一晶片110的側壁面SC，且暴露出所述至少一晶片110的背面SB，而形成至少一個容納所述至少一晶片110的開孔O。開孔O的位置即所述至少一晶片110在第一封裝層120中所佔據的位置，且開孔O與所述至少一晶片110的數量相同。開孔O構成第一封裝層120的應力釋放孔，使得第一封裝層120不為連續薄膜。
在本實施例中，第一封裝層120的厚度T120小於所述至少一晶片110的厚度T110，但不以此為限。依據不同的設計需求，第一封裝層120的厚度T120也可以大於或等於所述至少一晶片110的厚度T110。
請參照圖1C，以成型製程(molding process)於第一封裝層120以及所述至少一晶片110的背面SB上形成第二封裝材料層130M。第二封裝材料層130M的材料例如包括聚矽氮烷化合物、聚矽氮氧烷化合物或聚矽氧烷化合物，但不以此為限。
請參照圖1D，對第二封裝材料層130M進行至少一表面處理製程，以於第一封裝層120以及所述至少一晶片110的背面SB上形成第二封裝層130，其中第二封裝層130的熱膨脹係數小於第一封裝層120的熱膨脹係數。表面處理製程可例如包括電漿表面處理，但不以此為限。
藉由表面處理製程可使第二封裝材料層130M緻密化。第二封裝層130的緻密程度與第二封裝層130的氮氧比相關，在一實施例中，還可藉由改變表面處理的功率，來調變第二封裝層130的氮氧比，從而調整第二封裝層130的熱膨脹係數及內應力。
請參照圖1E，使所述至少一晶片110以及第一封裝層120自載板CP脫離，以暴露出所述至少一晶片110的主動面SA。在本實施例中，所述至少一晶片110是形成在離型層DB上(參見圖1D)。在圖1E的剝離製程中，所述至少一晶片110以及第一封裝層120會自離型層DB脫離。在剝離製程之後，可接續一反轉步驟，使所述至少一晶片110的主動面SA朝上，以利後續製程。
請參照圖1F，於第一封裝層120以及所述至少一晶片110的主動面SA上形成重佈線層140，且重佈線層140與所述至少一晶片110電性連接。在本實施例中，還可進一步於重佈線層140上形成與重佈線層140電性連接的多個導電凸塊B。導電凸塊B可例如為銅凸塊，但不以此為限。
請參照圖1G，可透過晶粒切割製程而形成多個晶片封裝體100，各晶片封裝體100的第二封裝層130可為連續薄膜且具有單一熱膨脹係數。各晶片封裝體100包括至少一晶片110、第一封裝層120、重佈線層140以及第二封裝層130。所述至少一晶片110具有主動面SA、與主動面SA相對的背面SB以及多個連接主動面SA與背面SB的側壁面SC。第一封裝層120包覆所述至少一晶片110的側壁面SC，其中第一封裝層120具有第一表面S1以及與第一表面S1相對的第二表面S2。重佈線層140配置在所述至少一晶片110的主動面SA以及第一封裝層120的第一表面S1上，且重佈線層140與所述至少一晶片110電性連接。第二封裝層130配置在所述至少一晶片110的背面SB以及第一封裝層120的第二表面S2上，其中第二封裝層130的熱膨脹係數小於第一封裝層120的熱膨脹係數。
由於第一封裝層120的熱膨脹係數大於所述至少一晶片110的熱膨脹係數，藉由熱膨脹係數較小(較接近所述至少一晶片110的熱膨脹係數)的第二封裝層130形成在所述至少一晶片110的背面上，可降低所述至少一晶片110與其上封裝層(即第二封裝層130)的熱膨脹係數差異，且第一封裝層120具有至少一容納所述至少一晶片110的應力釋放孔可利於將第一封裝層120的應力釋放，從而有助於改善不平整、對位精確度及翹曲等問題。此外，第二封裝層130還可兼具散熱作用。
以下藉由圖2A至圖6H說明本發明的晶片封裝體的其他種製作流程，其中圖2A至圖9與圖1G中相同或相似的元件以相同或相似的標號表示，於下便不再贅述。
圖2A至圖2C是依照本發明的第二實施例的一種晶片封裝體的製作流程的一部分的剖面示意圖，其中圖2A及圖2B的步驟是接續於圖1C的步驟之後，取代圖1D的步驟。
請參照圖2A，在圖1C的步驟之後，提供第一遮罩M1，其中第一遮罩M1暴露出所述至少一晶片110的所在區域且遮蔽所述至少一晶片110以外的區域。接著，以第一遮罩M1為罩幕，在第一功率下，對位於所述至少一晶片110上的第二封裝材料層130M進行表面處理，以形成第二封裝層130A的至少一第一部分P1。
請參照圖2B，提供第二遮罩M2，其中第二遮罩M2遮蔽所述至少一晶片110的所在區域且暴露出所述至少一晶片110以外的區域。接著，以第二遮罩M2為罩幕，在低於第一功率的第二功率下，對位於第一封裝層120上的第二封裝材料層130M進行表面處理，以形成第二封裝層130A的第二部分P2，其中第二部分P2的熱膨脹係數小於所述至少一第一部分P1的熱膨脹係數。
在本實施例中，由於所述至少一第一部分P1與第二部分P2經過不同功率的表面處理，因此所述至少一第一部分P1與第二部分P2具有不同的熱膨脹係數及折射率。由於折射率不同，反光特性亦不同，可識別出第二封裝層130A在不同區域會有不同的反光特性。
在圖2B的步驟後，可接續如圖1E的剝離製程及反轉步驟。再接續形成如圖1F的重佈線層140及導電凸塊B。接著，請參照圖2C，可透過晶粒切割製程而形成多個晶片封裝體100A。
圖2C中各晶片封裝體100A的第二封裝層130A由多種(例如兩種)具有不同熱膨脹係數的部分構成。具體地，第二封裝層130A具有至少一第一部分P1以及第二部分P2，其中第二部分P2的熱膨脹係數小於所述至少一第一部分P1的熱膨脹係數。所述至少一第一部分P1配置在所述至少一晶片110的背面SB上。第二部分P2與所述至少一第一部分P1連接，其中第二部分P2配置在第一封裝層120的第二表面S2上。第二封裝層130A具有圖案化的設計有助於應力釋放，從而可進一步改善翹曲的問題。
補充說明的是，本實施例雖以各晶片110的所在區域及晶片110以外的區域來劃分出第二封裝層130A的第一部分P1以及第二部分P2，但本發明不以此為限。在另一實施例中，第二封裝層130A的第一部分P1及第二部分P2的其中至少一者也可進一步劃分出具有不同熱膨脹係數的子部分。在又一實施例中，第二封裝層130A的第一部分P1也可對應多個晶片110，但不以此為限。在另一實施例中，第一部分P1與第二部分P2的製作順序可顛倒。也就是說，可先進行圖2B的步驟再進行圖2A的步驟。
圖3是依照本發明的第三實施例的一種晶片封裝體的製作流程的一部分的剖面示意圖，其中圖3的步驟是接續於圖1B的步驟之後，取代圖1C及圖1D的步驟。
請參照圖3，在圖1B的步驟之後，第二封裝層130例如是藉由真空鍍膜製程形成在第一封裝層120以及所述至少一晶片110的背面SB上。所述真空鍍膜製程可包括化學氣相沉積或濺鍍等，但不以此為限。
在第二封裝層130的厚度T130甚薄的情況下，第二封裝層130可能會隨承載表面的高低起伏而起伏，本實施例可先形成較厚的第二封裝層130再透過研磨製程，以使後續所形成之晶片封裝體的厚度差異趨於最小化。所述研磨製程可包括機械研磨製程(mechanical grinding process)或化學機械研磨(chemical mechanical polishing, CMP)製程等。
在圖3的步驟後，可接續如圖1E的剝離製程及反轉步驟，再接續形成如圖1F的重佈線層140及導電凸塊B。接著，進行如圖1G的晶粒切割製程而形成如圖1G所示的多個晶片封裝體100。
圖4A及圖4B是依照本發明的第四實施例的一種晶片封裝體的製作流程的一部分的剖面示意圖，其中圖4A及圖4B的步驟是接續於圖1B的步驟之後，取代圖1C及圖1D的步驟。
請參照圖4A，在圖1B的步驟後，可藉由真空鍍膜製程，以形成第二封裝層130A的至少一第一部分P1。具體地，提供第一遮罩M1，其中第一遮罩M1暴露出所述至少一晶片110的所在區域且遮蔽所述至少一晶片110以外的區域。接著，以第一遮罩M1為罩幕，於所述至少一晶片110的背面SB上形成第二封裝層130A的第一部分P1。
請參照圖4B，藉由第二次真空鍍膜製程，以形成第二封裝層130A的第二部分P2。具體地，提供第二遮罩M2，其中第二遮罩M2遮蔽所述至少一晶片110的所在區域且暴露出所述至少一晶片110以外的區域。接著，以第二遮罩M2為罩幕，於第一封裝層120上形成第二封裝層130A的第二部分P2，其中第二部分P2的熱膨脹係數小於所述至少一第一部分P1的熱膨脹係數。
在圖4B之步驟後，可接續如圖1E的剝離製程及反轉步驟，再接續形成如圖1F的重佈線層140及導電凸塊B。接著，進行如圖2C的晶粒切割製程而形成如圖2C所示的多個晶片封裝體100A。
在另一實施例中，第一部分P1與第二部分P2的製作順序可顛倒。也就是說，可先進行圖4B的步驟再進行圖4A的步驟。
圖5A至圖5C是依照本發明的第五實施例的一種晶片封裝體的製作流程的一部分的剖面示意圖，其中圖5A及圖5B的步驟是接續於圖1B的步驟之後，取代圖1C及圖1D的步驟。
請參照圖5A，藉由真空鍍膜製程，於第一封裝層120以及所述至少一晶片110的背面SB上形成一層薄的第二封裝層130，其中第二封裝層130的熱膨脹係數小於第一封裝層120的熱膨脹係數。
請參照圖5B，再次藉由真空鍍膜製程，於至少部分第二封裝層130上形成第三封裝層150。具體地，提供遮罩M，其中遮罩M遮蔽所述至少一晶片110的所在區域且暴露出所述至少一晶片110以外的區域。接著，以遮罩M為罩幕，於位於第一封裝層120上的第二封裝層130上形成第三封裝層150，其中第三封裝層150的熱膨脹係數小於第二封裝層130的熱膨脹係數。
在圖5B的步驟後，可接續如圖1E的剝離製程及反轉步驟。再接續形成如圖1F的重佈線層140及導電凸塊B。接著，請參照圖5C，可透過晶粒切割製程而形成多個晶片封裝體100B。
各晶片封裝體100B進一步包括第三封裝層150。第三封裝層150配置在位於第二表面S2上的第二封裝層130上且暴露出位於所述至少一晶片110上的第二封裝層130，其中第三封裝層150的熱膨脹係數小於第二封裝層130的熱膨脹係數，且第三封裝層150與第二封裝層130可具有不同的折射率。
藉由熱膨脹係數較小(較接近所述至少一晶片110的熱膨脹係數)的第二封裝層130形成在所述至少一晶片110的背面上，可降低所述至少一晶片110與其上封裝層(即第二封裝層130)的熱膨脹係數差異，且第一封裝層120具有至少一容納所述至少一晶片110的應力釋放孔可利於將第一封裝層120的應力釋放。此外，在所述至少一晶片110以外的區域中，藉由封裝層的熱膨脹係數遞減的堆疊方式，可有助於抑制翹曲。是以，有助於改善晶片封裝體100B的不平整、對位精確度及翹曲等問題。
圖6A至圖6H是依照本發明的第六實施例的一種晶片封裝體的製作流程的剖面示意圖。請參照圖6A，於載板CP上形成重佈線層240。在本實施例中，於載板CP上形成重佈線層240之前，可預先於載板CP上形成離型層DB，再於離型層DB上形成重佈線層240。
請參照圖6B，於重佈線層240上設置至少一晶片210。所述至少一晶片210與重佈線層240電性連接且具有主動面SA、背面SB以及多個側壁面SC，其中背面SB與主動面SA相對，且側壁面SC連接主動面SA與背面SB。所述至少一晶片210以覆晶方式設置於重佈線層240上，使得主動面SA位於背面SB與重佈線層240之間。
請參照圖6C，於重佈線層240上形成第一封裝層220。第一封裝層220包覆所述至少一晶片210的側壁面SC。在本實施例中，第一封裝層220還填入所述至少一晶片210與重佈線層240之間的間隙G中。第一封裝層220具有至少一個容納所述至少一晶片210的開孔O。開孔O的位置即所述至少一晶片210在第一封裝層220中所佔據的位置，且開孔O與所述至少一晶片210的數量可為相同。開孔O構成第一封裝層220的應力釋放孔，使得第一封裝層220為圖案化薄膜。
在本實施例中，第一封裝層220的厚度T220小於所述至少一晶片210的厚度T210，但不以此為限。依據不同的設計需求，第一封裝層220的厚度T220也可以大於或等於所述至少一晶片210的厚度T210。
請參照圖6D，於第一封裝層220以及所述至少一晶片210的背面SB上形成第二封裝材料層230M。第二封裝材料層230M的材料例如包括聚矽氮烷化合物、聚矽氮氧烷化合物或聚矽氧烷化合物，但不以此為限。
請參照圖6E，對第二封裝材料層230M進行至少一表面處理製程，例如可包括電漿表面處理，以於第一封裝層220以及所述至少一晶片210的背面SB上形成第二封裝層230，其中第二封裝層230的熱膨脹係數小於第一封裝層220的熱膨脹係數。
請參照圖6F，使重佈線層240自載板CP脫離。在本實施例中，重佈線層240是形成在離型層DB上(參見圖6E)。在圖6F的剝離製程中，重佈線層240會自離型層DB脫離。在剝離製程之後，可接續一反轉步驟，使重佈線層240朝上，以利後續製程。
請參照圖6G，於重佈線層240上形成與重佈線層240電性連接的多個導電凸塊B。導電凸塊B可例如為銅凸塊，但不以此為限。
請參照圖6H，可透過晶粒切割製程而形成多個晶片封裝體200。晶片封裝體200與圖1G的晶片封裝體100具有相似的結構，其中相似的元件以相似的標號表示，於此便不再贅述此些元件的材質、相對配置關係及其功效。
在本實施例中，晶片封裝體200的第二封裝層230是採用成型製程搭配表面處理製程形成，但不以此為限。在另一實施例中，第二封裝層230也可採用真空鍍膜製程形成。具體內容請參照對應圖3的描述，於此不再贅述。
圖7至圖9分別是依照本發明的第七至第九實施例的晶片封裝體的剖面示意圖，其中圖7至圖9與圖6H中相同或相似的元件以相同或相似的標號表示，於下便不再贅述。
圖6H中各晶片封裝體200的第二封裝層230可為連續薄膜且具有單一熱膨脹係數。圖7中晶片封裝體200A的第二封裝層230A可由多種(例如兩種)具有不同熱膨脹係數的部分構成。具體地，第二封裝層230A具有至少一第一部分P1以及第二部分P2，其中第二部分P2的熱膨脹係數小於所述至少一第一部分P1的熱膨脹係數。所述至少一第一部分P1配置在所述至少一晶片210的背面SB上。第二部分P2與所述至少一第一部分P1連接，其中第二部分P2配置在第一封裝層220的第二表面S2上。第二封裝層230A具有圖案化的設計有助於應力釋放，從而可進一步改善翹曲的問題。
補充說明的是，本實施例雖以晶片210的所在區域及晶片210以外的區域來劃分出第二封裝層230A的第一部分P1以及第二部分P2，但本發明不以此為限。在另一實施例中，第二封裝層230A的第一部分P1及第二部分P2的其中至少一者也可進一步劃分出具有不同熱膨脹係數的子部分。在又一實施例中，第二封裝層230A的第一部分P1也可對應多個晶片210，但不以此為限。
晶片封裝體200A的製作方式可以是在如圖6D的步驟後，接續如圖2A及圖2B的步驟，再接續如圖6F至圖6H的步驟。或者，也可以是在如圖6D的步驟後，接續如圖4A及圖4B的步驟，再接續如圖6F至圖6H的步驟。相關的描述請參照對應的段落，於此便不再贅述。
請參照圖8，晶片封裝體200B可進一步包括第三封裝層250。第三封裝層250配置在位於第二封裝層230的第二表面S2上且暴露出位於所述至少一晶片110上的第二封裝層230，其中第三封裝層250的熱膨脹係數小於第二封裝層230的熱膨脹係數，且第三封裝層250與第二封裝層230可具有不同的折射率。
藉由熱膨脹係數較小(較接近所述至少一晶片210的熱膨脹係數)的第二封裝層230形成在所述至少一晶片210的背面上，可降低所述至少一晶片210與其上封裝層(即第二封裝層230)的熱膨脹係數差異，且第一封裝層220具有至少一容納所述至少一晶片210的應力釋放孔可利於將第一封裝層220的應力釋放。此外，在所述至少一晶片210以外的區域中，藉由封裝層的熱膨脹係數遞減的堆疊方式，可有助於抑制翹曲。是以，有助於改善晶片封裝體200B的不平整、對位精確度及翹曲等問題。
晶片封裝體200B的製作方式可以是在如圖6C的步驟後，接續如圖5A及圖5B的步驟，再接續如圖6F至圖6H的步驟。相關的描述請參照對應的段落，於此便不再贅述。
請參照圖9，晶片封裝體200C可進一步包括至少一導電通孔T。所述至少一導電通孔T貫穿第一封裝層220以及第二封裝層230，且所述至少一導電通孔T與重佈線層240電性連接。晶片封裝體200C還可進一步包括多個接墊P，且接墊P透過所述至少一導電通孔T而與重佈線層240電性連接。如此，所述至少一晶片210可透過重佈線層240、所述至少一導電通孔T以及接墊P而與電子元件E電性連接。電子元件E例如是記憶體，但不以此為限。
本實施例雖以圖6H的晶片封裝體200進行上述改良，然而圖1G的晶片封裝體100、圖2C的晶片封裝體100A、圖5C的晶片封裝體100B、圖7的晶片封裝體200A及圖8的晶片封裝體200B等亦可適用於上述改良，於下便不再贅述。
在本發明的實施例中，晶片可位於第一封裝層的應力釋放孔，而有助於將第一封裝層的應力釋放。此外，藉由使第二封裝層的熱膨脹係數小於第一封裝層的熱膨脹係數，可降低第二封裝層與晶片的熱膨脹係數差異。本發明有助於改善不平整、對位精確度及翹曲等問題，進而具有良好的產能及封裝良率。在一實施例中，還可使第二封裝層具有圖案化的設計，以利應力釋放，從而進一步改善翹曲的問題。在又一實施例中，封裝層在晶片以外的區域可採用熱膨脹係數遞減的堆疊方式，以抑制翹曲。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍及其均等範圍所界定者為準。
100、100A、100B、200、200A、200B、200C‧‧‧晶片封裝體
110、210‧‧‧晶片
120、220‧‧‧第一封裝層
130、130A、230、230A‧‧‧第二封裝層
130M、230M‧‧‧第二封裝材料層
140、240‧‧‧重佈線層
150、250‧‧‧第三封裝層
B‧‧‧導電凸塊
CP‧‧‧載板
DB‧‧‧離型層
E‧‧‧電子元件
G‧‧‧間隙
M‧‧‧遮罩
M1‧‧‧第一遮罩
M2‧‧‧第二遮罩
O‧‧‧開孔
P‧‧‧接墊
P1‧‧‧第一部分
P2‧‧‧第二部分
S1‧‧‧第一表面
S2‧‧‧第二表面
SA‧‧‧主動面
SB‧‧‧背面
SC‧‧‧側壁面
T‧‧‧導電通孔
T110、T120、T130、T210、T220‧‧‧厚度
圖1A至圖1G是依照本發明的第一實施例的一種晶片封裝體的製作流程的剖面示意圖。 圖2A至圖2C是依照本發明的第二實施例的一種晶片封裝體的製作流程的一部分的剖面示意圖。 圖3是依照本發明的第三實施例的一種晶片封裝體的製作流程的一部分的剖面示意圖。 圖4A及圖4B是依照本發明的第四實施例的一種晶片封裝體的製作流程的一部分的剖面示意圖。 圖5A至圖5C是依照本發明的第五實施例的一種晶片封裝體的製作流程的一部分的剖面示意圖。 圖6A至圖6H是依照本發明的第六實施例的一種晶片封裝體的製作流程的剖面示意圖。 圖7至圖9分別是依照本發明的第七至第九實施例的晶片封裝體的剖面示意圖。

Claims (20)

  1. 一種晶片封裝體，包括：至少一晶片，具有一主動面、一與該主動面相對的背面以及多個連接該主動面與該背面的側壁面；一第一封裝層，包覆該至少一晶片的該些側壁面，其中該第一封裝層具有一第一表面以及一與該第一表面相對的第二表面；一重佈線層，配置在該至少一晶片的該主動面以及該第一封裝層的該第一表面上，且該重佈線層與該至少一晶片電性連接；以及一第二封裝層，配置在該至少一晶片的該背面以及該第一封裝層的該第二表面上，其中該第二封裝層以及該至少一晶片的熱膨脹係數小於該第一封裝層的熱膨脹係數。
  2. 如申請專利範圍第1項所述的晶片封裝體，其中該第二封裝層具有至少一第一部分以及一第二部分，該至少一第一部分配置在該至少一晶片的該背面上，該第二部分與該至少一第一部分連接，其中該第二部分配置在該第一封裝層的該第二表面上。
  3. 如申請專利範圍第2項所述的晶片封裝體，其中該第二部分的熱膨脹係數小於該至少一第一部分的熱膨脹係數。
  4. 如申請專利範圍第2項所述的晶片封裝體，其中該第二部分的折射率不同於該至少一第一部分的折射率。
  5. 如申請專利範圍第1項所述的晶片封裝體，更包括：一第三封裝層，配置在該第二封裝層上且暴露出位於該至少 一晶片上的該第二封裝層。
  6. 如申請專利範圍第5項所述的晶片封裝體，其中該第三封裝層的熱膨脹係數小於該第二封裝層的熱膨脹係數。
  7. 如申請專利範圍第5項所述的晶片封裝體，其中該第三封裝層的折射率不同於該第二封裝層的折射率。
  8. 如申請專利範圍第1項所述的晶片封裝體，更包括：至少一導電通孔，貫穿該第一封裝層以及該第二封裝層，且該至少一導電通孔與該重佈線層電性連接。
  9. 一種晶片封裝方法，包括：於一載板上設置至少一晶片，該至少一晶片具有一主動面、一與該主動面相對的背面以及多個連接該主動面與該背面的側壁面，其中該主動面位於該背面與該載板之間；於該載板上形成一第一封裝層，該第一封裝層包覆該至少一晶片的該些側壁面，以暴露出該至少一晶片的該主動面以及該背面；於該第一封裝層以及該至少一晶片的該背面上形成一第二封裝層，其中該第二封裝層以及該至少一晶片的熱膨脹係數小於該第一封裝層的熱膨脹係數；使該至少一晶片以及該第一封裝層自該載板脫離，以暴露出該至少一晶片的該主動面；以及於該第一封裝層以及該至少一晶片的該主動面上形成一重佈線層，且該重佈線層與該至少一晶片電性連接。
  10. 如申請專利範圍第9項所述的晶片封裝方法，其中形成該第二封裝層的方法包括：以一成型製程於該第一封裝層以及該至少一晶片的該背面上形成一第二封裝材料層；以及對該第二封裝材料層進行至少一表面處理製程，以形成該第二封裝層。
  11. 如申請專利範圍第10項所述的晶片封裝方法，其中該至少一表面處理製程包括：提供一第一遮罩，其中該第一遮罩暴露出該至少一晶片的所在區域且遮蔽該至少一晶片以外的區域；以該第一遮罩為罩幕，在一第一功率下，對位於該至少一晶片上的該第二封裝材料層進行表面處理，以形成該第二封裝層的至少一第一部分；提供一第二遮罩，其中該第二遮罩遮蔽該至少一晶片的所在區域且暴露出該至少一晶片以外的區域；以及以該第二遮罩為罩幕，在低於該第一功率的一第二功率下，對位於該第一封裝層上的該第二封裝材料層進行表面處理，以形成該第二封裝層的一第二部分，其中該第二部分的熱膨脹係數小於該至少一第一部分的熱膨脹係數。
  12. 如申請專利範圍第9項所述的晶片封裝方法，其中形成該第二封裝層的方法包括至少一真空鍍膜製程。
  13. 如申請專利範圍第12項所述的晶片封裝方法，其中該至少一真空鍍膜製程包括：提供一第一遮罩，其中該第一遮罩暴露出該至少一晶片的所在區域且遮蔽該至少一晶片以外的區域；以該第一遮罩為罩幕，於該至少一晶片的該背面上形成該第二封裝層的至少一第一部分；提供一第二遮罩，其中該第二遮罩遮蔽該至少一晶片的所在區域且暴露出該至少一晶片以外的區域；以及以該第二遮罩為罩幕，於該第一封裝層上形成該第二封裝層的一第二部分，其中該第二部分的熱膨脹係數小於該至少一第一部分的熱膨脹係數。
  14. 如申請專利範圍第12項所述的晶片封裝方法，更包括：提供一遮罩，其中該遮罩遮蔽該至少一晶片的所在區域且暴露出該至少一晶片以外的區域；以及以該遮罩為罩幕，於位於該第一封裝層上的該第二封裝層上形成一第三封裝層，其中該第三封裝層的熱膨脹係數小於該第二封裝層的熱膨脹係數。
  15. 一種晶片封裝方法，包括：於一載板上形成一重佈線層；於該重佈線層上設置至少一晶片，該至少一晶片與該重佈線層電性連接且具有一主動面、一與該主動面相對的背面以及多個 連接該主動面與該背面的側壁面，其中該主動面位於該背面與該重佈線層之間；於該重佈線層上形成一第一封裝層，該第一封裝層包覆該至少一晶片的該些側壁面，以暴露出該至少一晶片的該背面；於該第一封裝層以及該至少一晶片的該背面上形成一第二封裝層，其中該第二封裝層以及該至少一晶片的熱膨脹係數小於該第一封裝層的熱膨脹係數；以及使該重佈線層自該載板脫離。
  16. 如申請專利範圍第15項所述的晶片封裝方法，其中形成該第二封裝層的方法包括：以一成型製程於該第一封裝層以及該至少一晶片的該背面上形成一第二封裝材料層；以及對該第二封裝材料層進行至少一表面處理製程，以形成該第二封裝層。
  17. 如申請專利範圍第16項所述的晶片封裝方法，其中該至少一表面處理製程包括：提供一第一遮罩，其中該第一遮罩暴露出該至少一晶片的所在區域且遮蔽該至少一晶片以外的區域；以該第一遮罩為罩幕，在一第一功率下，對位於該至少一晶片上的該第二封裝材料層進行表面處理，以形成該第二封裝層的至少一第一部分；提供一第二遮罩，其中該第二遮罩遮蔽該至少一晶片的所在 區域且暴露出該至少一晶片以外的區域；以及以該第二遮罩為罩幕，在低於該第一功率的一第二功率下，對位於該第一封裝層上的該第二封裝材料層進行表面處理，以形成該第二封裝層的一第二部分，其中該第二部分的熱膨脹係數小於該至少一第一部分的熱膨脹係數。
  18. 如申請專利範圍第15項所述的晶片封裝方法，其中形成該第二封裝層的方法包括至少一真空鍍膜製程。
  19. 如申請專利範圍第18項所述的晶片封裝方法，其中該至少一真空鍍膜製程包括：提供一第一遮罩，其中該第一遮罩暴露出該至少一晶片的所在區域且遮蔽該至少一晶片以外的區域；以該第一遮罩為罩幕，於該至少一晶片的該背面上形成該第二封裝層的至少一第一部分；提供一第二遮罩，其中該第二遮罩遮蔽該至少一晶片的所在區域且暴露出該至少一晶片以外的區域；以及以該第二遮罩為罩幕，於該第一封裝層上形成該第二封裝層的一第二部分，其中該第二部分的熱膨脹係數小於該至少一第一部分的熱膨脹係數。
  20. 如申請專利範圍第18項所述的晶片封裝方法，更包括：提供一遮罩，其中該遮罩遮蔽該至少一晶片的所在區域且暴露出該至少一晶片以外的區域；以及 以該遮罩為罩幕，於位於該第一封裝層上的該第二封裝層上形成一第三封裝層，其中該第三封裝層的熱膨脹係數小於該第二封裝層的熱膨脹係數。
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