TW201944553A - 疊層封裝結構 - Google Patents

疊層封裝結構 Download PDF

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Publication number
TW201944553A
TW201944553A TW107120679A TW107120679A TW201944553A TW 201944553 A TW201944553 A TW 201944553A TW 107120679 A TW107120679 A TW 107120679A TW 107120679 A TW107120679 A TW 107120679A TW 201944553 A TW201944553 A TW 201944553A
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package
semiconductor device
underfill
disposed
present
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TW107120679A
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TWI752238B (zh
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沈東翰
陳承先
劉國洲
鄭錫圭
賴怡仁
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種疊層封裝結構，其包括第一封裝件、多個導電凸塊、第二封裝件以及底部填充膠。導電凸塊設置在第一封裝件的第二表面上且電性連接到第一封裝件。第二封裝件通過導電凸塊設置在第一封裝件的第二表面上，且包括半導體裝置以及包封半導體裝置的包封材料。從包封材料的上部表面到半導體裝置的上部表面的最短距離大於或實質上等於半導體裝置的厚度的兩倍。底部填充膠填充在第一封裝件與第二封裝件之間。

Description

疊層封裝結構
本發明實施例是有關於一種疊層封裝結構。
隨著對較小電子產品的需求增長，電子行業中的製造商等不斷地尋求縮小電子產品中所用積體電路的尺寸的方法。為此，已研發並使用三維類型積體電路封裝技術。
製造3D集成晶片需要堆疊多個半導體封裝、在對應封裝之間耦接電路以及用電性絕緣黏著劑接合封裝以形成疊層封裝結構。例如使電性絕緣黏著劑固化的後續高溫處理步驟使疊層封裝結構經受機械應力，其可引起非期望的副作用，例如翹曲、開裂、分層以及疵點形成。
本發明實施例提供一種疊層封裝結構，其具有較高的產品良率。
在本發明的一實施例中，一種疊層封裝結構包括一第一封裝件、多個導電凸塊、一第二封裝件以及一底部填充膠。導電凸塊設置在第一封裝件的一第二表面上且電性連接到第一封裝件。第二封裝件通過導電凸塊設置在第一封裝件的第二表面上並包括一半導體裝置以及包封半導體裝置的一包封材料。從包封材料的一上部表面到半導體裝置的一上部表面的一最短距離大於或實質上等於半導體裝置的一厚度的兩倍。底部填充膠填充在第一封裝件與第二封裝件之間。
在本發明的一實施例中，一種疊層封裝結構包括一第一封裝件、多個導電凸塊、一第二封裝件以及一底部填充膠。第一封裝件包括一包封的半導體裝置以及一重佈線結構。包封的半導體裝置包括一第一半導體裝置、包封第一半導體裝置的一第一包封材料以及延伸穿過第一包封材料的多個通孔。重佈線結構設置在包封的半導體裝置的一第一表面上且電性連接到包封的半導體裝置。導電凸塊設置在包封的半導體裝置的一第二表面上且電性連接到包封的半導體裝置。第二表面與第一表面相對。第二封裝件設置在包封的半導體裝置的第二表面上並包括一第二半導體裝置以及包封第二半導體裝置的一第二包封材料。從第二包封材料的一上部表面到第二半導體裝置的一上部表面的一最短距離大於或實質上等於第二半導體裝置的一厚度的兩倍。底部填充膠填充在第一封裝件與第二封裝件之間。
在本發明的一實施例中，一種疊層封裝結構包括一第一封裝件、多個導電凸塊、一第二封裝件以及一底部填充膠。第一封裝件包括一包封的半導體裝置以及一重佈線結構，所述重佈線結構設置在包封的半導體裝置的一第一表面上且電性連接到包封的半導體裝置。導電凸塊設置在包封的半導體裝置的一第二表面上且電性連接到包封的半導體裝置。第二封裝件通過導電凸塊設置在第二表面上並包括多個半導體裝置以及包封半導體裝置的一包封材料。從包封材料的一上部表面到半導體裝置的一最頂部表面的一最短距離大於或實質上等於半導體裝置的一最大厚度的兩倍。底部填充膠填充在第一封裝件與第二封裝件之間。
為讓本發明實施例的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下揭露內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本發明實施例。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下（beneath）」、「下面（below）」、「下部（lower）」、「上方（above）”、「上部（upper）」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外更囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或處於其他取向）且本文中所用的空間相對性描述語可同樣相應地進行解釋。
另外，為易於說明，本文中可能使用例如「第一（first）」、「第二（second）」、「第三（third）」、「第四（fourth）」等用語來闡述與圖中所示者相似或不同的一個或多個元件或特徵，且可依據呈現次序或本說明的上下文來可互換地使用所述用語。
本發明實施例更可包括其它特徵和製程。舉例來說，可包括測試結構以説明驗證測試3D封裝或3DIC裝置。測試結構可包括例如形成在重佈線層中或基板上的測試墊，所述基板允許測試3D封裝或3DIC、使用探針及/或探針卡等等。驗證測試可在中間結構及最終結構上執行。另外，本文中所公開的結構及方法可以與並有已知良好晶粒的中間驗證的測試方法結合使用以增加產量並降低成本。
圖1到圖8說明根據本發明的一些示範性實施例的製造疊層封裝結構中的中間階段的剖面圖。應注意，將參照特定情形（即疊層封裝（Package on Package；PoP）結構）下的一些實施例描述本發明實施例。然而，本發明實施例中的概念更可應用於其它半導體結構或電路。根據各種實施例提供PoP結構以及形成PoP結構的方法。根據一些實施例說明形成PoP結構的中間階段。論述實施例的變化。貫穿各個視圖及說明性實施例，相似參考標號用於表示相似元件。
在一些實施例中，形成如圖8中所示PoP結構10的中間階段的描述如下。參看圖1，提供載體160，且黏著劑層165可設置在載體160上。在一些實施例中，載體160可以是玻璃載體、陶瓷載體或其類似物。黏著劑層165可以是光熱轉換釋放塗層（light to heat conversion release coating；LTHC）或其類似物。在一些實施例中，絕緣層170a可選擇性地設置在載體160上或在黏著劑層165（如果存在）上。隨後，多個通孔130形成在載體160上，且通孔130圍繞待設置第一半導體裝置110的中心區域A1。在一些實施例中，通孔130設置在圍繞中心區域A1的載體160的週邊區域A2上。應注意的是，本文中“中心”及“週邊”可不照字面地解釋，而可視為空間上的相對術語，除圖式中所描繪的定向以外，所述空間上的相對術語意欲涵蓋裝置在使用或操作中的不同定向。在本實施例中，通孔130形成在位於載體160上的絕緣層170a上，然而本發明實施例不限於此。在替代實施例中，可省略絕緣層170a及黏著劑層165，而通孔130則直接形成在載體160上。
在一些實施例中，至少一個如圖2所示的第一半導體裝置110a形成在載體160上且位於中心區域A1內。在本實施例中，第一半導體裝置110a形成在位於載體160上的絕緣層170a上，然而本發明實施例不限於此。在一些實施例中，第一半導體裝置110a可以是包括邏輯電路於其中的邏輯晶片。在一些示範性實施例中，第一半導體裝置110a的數量可以是多個，且可以是為手機應用程式而設計的多個裝置晶粒（device dies），且可包括例如電源管理積體電路（Power Management Integrated Circuit；PMIC）晶粒及收發器（Transceiver；TRX）晶粒。雖然僅示出一個第一半導體裝置110a，但是更多的半導體裝置可以被放置在載體160上方且彼此齊平。
在一些實施例中，載體160可包括以例如陣列方式配置的多個中心區域A1。相應地，通孔130可經形成以圍繞每個中心區域A1，且多個第一半導體裝置110a可分別設置在所述多個中心區域A1上，這樣通孔130可圍繞每個第一半導體裝置110a。利用這些佈置，可同時形成多個PoP結構。出於簡潔及清楚起見，圖1到圖8中僅示出所述多個PoP結構中的一個的製程。舉例來說，圖1中示出由所述多個通孔130中的一些圍繞的所述多個中心區域A1中的一個。
在一些實施例中，通孔130可預先形成，且隨後放置在載體160上。在替代實施例中，通孔130可由例如電鍍製程來形成。通孔130的電鍍可在放置第一半導體裝置110a之前執行，且可包括以下步驟。舉例來說，首先形成晶種層（未繪示）在載體160上方、形成光阻層（未繪示）並對其進行圖案化製程以及在被光阻層暴露的部份晶種層上電鍍而形成通孔130。光阻層以及由光阻層所覆蓋的部份晶種層可隨後被移除。第一半導體裝置110a可隨後放置在載體160上方。通孔130的材料可包括銅、鋁或其類似物。相應地，通孔130的底端與第一半導體裝置110a的背表面實質上齊平。
在一些示範性實施例中，多個導通孔114（例如銅通孔）可形成在第一半導體裝置110a的主動表面（例如頂部表面）上且電耦接到第一半導體裝置110a的基板112上的接墊113。在一些實施例中，介電層116a可形成在第一半導體裝置110a的主動表面（例如頂部表面）上，且可覆蓋導通孔114的頂部表面。在其它實施例中，介電層116a的頂部表面可與導通孔114的頂部表面實質上齊平。或者，可省略介電層116a，且導通孔114從第一半導體裝置110的主動表面突出。在一些實施例中，通孔130的頂端可與導通孔114的頂部表面實質上齊平。在其它實施例中，通孔130的頂端可實質上高於導通孔114的頂部表面。或者，通孔130的頂端可實質上低於導通孔114的頂部表面但是實質上高於導通孔114的底部表面。
隨後，載體160上的第一半導體裝置110a及通孔130由第一包封材料120a包封。換句話說，第一包封材料120a形成在載體160上以包封在週邊區域A2處的通孔130以及在中心區域A1處的第一半導體裝置110a。在一些實施例中，第一包封材料120a填充在第一半導體裝置110a與通孔130之間的間隙，且可與絕緣層170a接觸。第一包封材料120a可包括模製化合物（molding compound）、環氧樹脂或樹脂等。在一些實施例中，第一包封材料120a的頂部表面可高於通孔130的頂端以及介電層116a的頂部表面。即第一包封材料120a覆蓋通孔130的頂端以及介電層116a的頂部表面。
隨後，執行薄化製程（可以是研磨製程）以薄化第一包封材料120a（以及介電層116a）直到顯露通孔130的頂端以及導通孔114的頂部表面為止。所得結構繪示於圖3中。由於薄化製程，通孔130的頂端與導通孔114的頂部表面實質上齊平，且與第一包封材料120的頂部表面以及介電層116的頂部表面實質上齊平，如圖3中所示。在整篇描述中，如圖3中所示的包括第一半導體裝置110、通孔130以及第一包封材料120的所得結構被稱作包封的半導體裝置101，其在製程中可具有晶圓形式。相應地，在包封的半導體裝置101中，第一半導體裝置110設置在中心區域A1處，通孔130在圍繞中心區域A1的週邊區域A2處延伸穿過第一包封材料120，且第一包封材料120包封第一半導體裝置110及通孔130。換句話說，第一包封材料120包封其中的第一半導體裝置110，且通孔130延伸穿過第一包封材料120。
接下來參看圖4，重佈線結構140形成在包封的半導體裝置101的第一表面S1上。重佈線結構140電性連接到包封的半導體裝置101的第一半導體裝置110及通孔130。在一些實施例中，重佈線結構140形成在包封的半導體裝置101上方以連接到第一半導體裝置110的導通孔114以及通孔130。在一些實施例中，重佈線結構140更可使導通孔114與通孔130互連。重佈線結構140可由例如以下步驟而形成：沉積導電層、對導電層進行圖案化以形成重佈線路142、以介電層143部分地覆蓋重佈線路142並填充重佈線路142之間的間隙等。重佈線路142的材料可包括金屬或包括鋁、銅、鎢及/或其合金的金屬合金。介電層143可由例如氧化物、氮化物、碳化物、碳氮化物、其組合及/或其多層的介電材料來形成。重佈線路142形成在介電層143中且電性連接到第一半導體裝置110及通孔130。另外，凸塊下金屬（Under Bump Metallurgy；UBM）層144可由濺鍍、蒸鍍或無電電鍍等而形成在重佈線結構140上。
參看圖5，根據一些示範性實施例，電性連接件182中的至少一個以及至少一個集成被動裝置（Integrated Passive Device；IPD）184設置在重佈線路結構140上。電性連接件182的形成可包括將焊料球放置在凸塊下金屬層144上（或在重佈線路結構140上），並且隨後回焊焊料球。在替代實施例中，電性連接件182的形成可包括執行電鍍製程以在凸塊下金屬層144上（或重佈線路結構140上）形成焊料塊，並且隨後回焊焊料塊。電性連接件182更可包括導電柱，或具有焊料頂蓋的導電柱，其也可通過電鍍形成。集成被動裝置184可使用例如薄膜及微影製程的標準晶圓製造技術來製造，且可通過例如覆晶接合或打線接合（wire bonding）等來安裝在重佈線路結構140上。
隨後參看圖6，載體160可去除。在一些實施例中，通過使黏著劑層165失去黏著力或減小黏著力而使載體160脫離包封的半導體裝置101及絕緣層170a（如果存在）。黏著劑層165可與載體160一起被去除。舉例來說，可使黏著劑層165曝露於UV光下，使得黏著劑層165失去黏著力或減小黏著力，因而可從包封的半導體裝置101上去除載體160及黏著劑層165。
在去除載體160之後，通孔130的底端顯露出來。在所說明的結構中，通孔130的底端與第一半導體裝置110的底部表面以及第一包封材料120的底部表面齊平。在省略絕緣層170a的實施例中，可執行研磨製程以輕微地研磨第一半導體裝置110的底部表面以及通孔130的底端。或者，可省略研磨製程。
參看圖7，在具有絕緣層170a的實施例中，可隨後對絕緣層170a執行圖案化製程以形成多個開口172。如此，可形成具有多個開口172的絕緣層170。開口172分別位於通孔130上以顯露通孔130的底端。在一些實施例中，開口172可由微影製程、雷射鑽孔製程等來形成。相應地，所得結構是如圖7中所示的第一封裝件100。
參看圖8，多個導電凸塊300可形成在第一封裝件100的包封的半導體裝置101的第二表面S2上，以電性連接到第一封裝件100的通孔130。第二表面S2與第一表面S1相對。即重佈線結構140與導電凸塊300分別設置在包封的半導體裝置101的兩個相對表面S1、表面S2上。在一些實施例中，導電凸塊300設置在絕緣層170的開口172中以連接到通孔130。在一些實施例中，導電凸塊300設置在第二表面S2的週邊區域A2上且圍繞中心區域A1，第一半導體裝置110位於所述中心區域A1內。
隨後，第二封裝件200設置在第一封裝件100上且通過導電凸塊300電性連接到通孔130。在一些實施例中，第二封裝件200通過導電凸塊300設置在包封的半導體裝置101的第二表面S2上。第二封裝件200以其下部表面201面向包封的半導體裝置101的第二表面S2的方式安裝在第一封裝件100上。在一些實施例中，第二封裝件200可以是封裝件、裝置晶粒、被動裝置及/或其類似物。在一些實施例中，疊層封裝結構10可垂直地組合離散記憶體（discrete memory）封裝件及邏輯封裝件，且可在例如動態隨機記憶體（Dynamic Random Access Memory；DRAM）及其它記憶體的記憶體中採用（employed）第二封裝件200，然而本發明實施例不限於此。
隨後，將底部填充膠400填充到在第一封裝件100與第二封裝件200之間的間隙中以增強導電凸塊300的強度且因此增強整個疊層封裝結構10的強度。在一些實施例中，底部填充膠400覆蓋中心區域A1以及週邊區域A2，並包封導電凸塊300。底部填充膠400可隨後由熱固化製程來固化，且固化溫度的範圍可為約100℃到150℃。相應地，所得結構是如圖8中所示的疊層封裝結構10。
在一些實施例中，第二封裝件200可由覆晶接合的方式來安裝在第一封裝件100上，且第二封裝件200可包括設置在重佈線結構230上的至少一個第二半導體裝置210以及包封第二半導體裝置210的第二包封材料220。在一些實施例中，重佈線結構230可以是封裝基板。在其它實施例中，重佈線結構230可以是與重佈線結構140相似的重佈線層（redistribution layer；RDL），其由例如以下步驟來形成：沉積導電層、圖案化導電層以形成重佈線路、以介電層部分地覆蓋重佈線路以及填充在重佈線路之間的間隙等。
一般來說，在接合製程期間，如果第二半導體裝置210、第二包封材料220以及重佈線結構230具有不同的熱膨脹（thermal expansion；CTE）係數，那麼在加熱封裝件200以及冷卻封裝件200時產生不同的膨脹程度。不同程度的膨脹對焊料球連接件施加很大應力，其可引起第二封裝件200的翹曲（warpage）。在疊層封裝配置中包括覆晶封裝時會產生額外的困難。在疊層封裝結構10中，例如專用積體電路（application specific IC；ASIC）及記憶體封裝（例如動態隨機存取記憶體（Dynamic Random Access Memory；DRAM））的兩個封裝件100及200可以彼此堆疊的方式安裝。舉例來說，第二封裝件200可大於第一封裝件100，且可具有圍繞其周圍的導電凸塊300陣列以形成到第一封裝件100的連接。例如疊層封裝結構10的配置會增加封裝件翹曲的可能性。
相應地，在將底部填充膠400分配在具有翹曲輪廓的第一封裝件100與第二封裝件200之間時，底部填充膠400可能無法完全地填充間隙，這會導致在底部填充膠400內形成空隙（void）。此外，隨著高溫固化，在底部填充膠400內的空隙將變大且迅速地成核而引起脫層（delamination）。因此，控制疊層封裝結構10的翹曲輪廓是甚為重要的，以使底部填充膠400填充在第一封裝件100與第二封裝件200之間的間隙而沒有空隙形成。
為獲得在固化製程期間封裝件的翹曲度與底部填充膠400的失敗率（例如開裂或脫層等）之間的關係而進行一系列實驗，並可相應地計算出由第二封裝件200的不同程度的翹曲造成的疊層封裝結構10的底部填充膠400的失敗率（failure rate）。為監測疊層封裝結構10的翹曲，可採用共面性（co-planarity）測量工具，其可採用投影波紋技術（Shadow Moire' technique）來測量疊層封裝結構10的共面性。當然，以下實驗資料及條件僅出於說明的目的提供，且本發明實施例不限於此，而實際上涵蓋作為本文所提供教示的結果而為相關的所有變化。
圖9描繪說明在指定溫度下第二封裝件的翹曲與底部填充膠失敗率之間的關係的圖。圖10描繪說明在另一指定溫度下第二封裝件的翹曲與底部填充膠失敗率之間的關係的圖。在圖9中展示的實驗中，疊層封裝結構10暴露於100℃左右的指定溫度以類比底部填充膠400的固化製程。已發現在第二封裝件200的翹曲實質上等於或小於約-20微米時，底部填充膠400的失敗率達到0%。另外，在第二封裝件200呈凹形翹曲輪廓形式（即第二封裝件200的翹曲為負值）時，底部填充膠400的失敗率低於10%。
在圖10中展示的實驗中，疊層封裝結構10暴露於150℃左右的指定溫度以類比底部填充膠400的固化製程。相似地，已發現在第二封裝件200的翹曲實質上等於或小於約-20微米時，底部填充膠400的失敗率達到0%。另外，在第二封裝件200呈凹形翹曲輪廓形式（即第二封裝件200的翹曲為負值）時，底部填充膠400的失敗率也低於10%。
有監於此，可將第二封裝件200的翹曲輪廓控制為凹形翹曲輪廓以降低底部填充膠400的失敗率。在實施方案中的一個中，第二封裝件200的下部表面201朝向包封的半導體裝置101的第二表面S2彎曲，且下部表面201是面向第二表面S2的表面。在一些實施例中，從第二表面S2的中心區域A1到第二封裝件200的最短距離D1實質上小於從第二表面S2的週邊區域A2上的任何位置到第二封裝件200的最短距離D2。也就是說，如圖8中所繪示，第一封裝件100與第二封裝件200之間的距離（例如間隙寬度）從週邊區域A2到中心區域A1逐漸減小。舉例來說，中心區域A1處的最短距離D1的範圍實質上可介於30微米到60微米之間，而週邊區域A2處的最短距離D2的範圍實質上可介於100微米到140微米之間。當然，實例中的數值範圍僅出於說明的目的提供，且本發明實施例不限於所述實例，而實際上涵蓋作為本文所提供教示的結果而為相關的所有變化。
為實現第二封裝件200的凹形翹曲輪廓，從第二包封材料220的上部表面222到第二半導體裝置210的上部表面212的最短距離T1大於或實質上等於第二半導體裝置210的厚度T2的兩倍（即T1≧2×T2）。通過這種配置，由於第二封裝件200的元件之間的熱膨脹失配（thermal expansion mismatch），第二封裝件200將在熱製程（thermal process）之後呈凹形翹曲輪廓形式，因此第一封裝件100與第二封裝件200之間的間隙寬度從週邊區域A2到中心區域A1逐漸減小。由此，在使底部填充膠400從週邊區域A2分配並流向中心區域A1時，底部填充膠400可由於毛細作用而輕易地填充中心區域A1處的間隙而沒有空隙形成。
圖11說明根據本發明的一些示範性實施例的疊層封裝結構的剖面圖。應注意，圖11中繪示的疊層封裝結構10'含有許多與先前圖8所公開的疊層封裝結構10相同或相似的特徵。出於清楚及簡化的目的，可省略相同或相似特徵的細節描述，並且相同或相似參考標號指代相同或類似元件。如下描述圖11中繪示的疊層封裝結構10'與圖8中繪示的疊層封裝結構10之間的主要差異。
在一些實施例中，第二封裝件200'包括設置在重佈線結構230上的多個第二半導體裝置210a、210b以及包封所述多個第二半導體裝置210a、210b的第二包封材料220。在一些實施例中，重佈線結構230可以是封裝基板。在其它實施例中，重佈線結構230可以是與重佈線結構140相似的重佈線層。在一些實施例中，從第二包封材料220的上部表面222到所述多個第二半導體裝置210a 210b的最頂部表面的最短距離T1大於或實質上等於所述多個第二半導體裝置210a、210b的最大厚度的兩倍。
在本實施例中，第二半導體裝置210a、第二半導體裝置210b以並排方式設置在重佈線結構230上。第二半導體裝置210a及第二半導體裝置210b的厚度T2及厚度T3可相同。在這種情況下，從上部表面222到第二半導體裝置210a或第二半導體裝置210b中任一個的頂部表面212a或頂部表面212b的最短距離T1大於或實質上等於第二半導體裝置210a或第二半導體裝置210b中任一個的厚度T2或厚度T3的兩倍。在其它實施例中，第二半導體裝置210a的厚度T2及第二半導體裝置210b的及厚度T3可不同。舉例來說，第二半導體裝置210a的厚度T2大於第二半導體裝置210b的厚度T3。在這種情況下，從上部表面222到第二半導體裝置210a的頂部表面212a的最短距離T1大於或實質上等於第二半導體裝置210a的厚度T2的兩倍。應注意，圖11中示出兩個第二半導體裝置210a、210b，然而本發明實施例並不限制第二封裝件200中的第二半導體裝置210a、210b的配置及數量。
通過這種配置，第二封裝件200'將在熱製程之後呈凹形翹曲輪廓形式，因此第一封裝件100與第二封裝件200'之間的間隙寬度從週邊區域A2到中心區域A1逐漸減小。由此，在使底部填充膠400從週邊區域A2分配且流向中心區域A1時，底部填充膠400可由於毛細作用而輕易地在中心區域A1上方流動，且填充第一封裝件100與第二封裝件200'之間的間隙而沒有空隙形成。
圖12說明根據本發明的一些示範性實施例的疊層封裝結構的剖面圖。應注意，圖12中繪示的疊層封裝結構10''含有許多與先前圖8所公開的疊層封裝結構10相同或相似的特徵。出於清楚及簡化的目的，可省略相同或相似特徵的細節描述，並且相同或相似參考標號指代相同或類似元件。如下描述圖12中繪示的疊層封裝結構10''與圖8中繪示的疊層封裝結構10之間的主要差異。
在一些實施例中，第二封裝件200''包括設置在重佈線結構230上的多個第二半導體裝置210a、210b、210c以及包封所述多個第二半導體裝置210a、210b、210c的第二包封材料220'。在一些實施例中，重佈線結構230可以是封裝基板。在其它實施例中，重佈線結構230可以是與重佈線結構140相似的重佈線層（redistribution layer；RDL）。在一些實施例中，從第二包封材料220'的上部表面222到所述多個第二半導體裝置210a、210b、210c中的最頂部表面的最短距離T1大於或實質上等於所述多個第二半導體裝置210a、210b、210c中的最大厚度的兩倍。
在本實施例中，第二半導體裝置210b及第二半導體裝置210c在重佈線結構230上彼此堆疊，且第二半導體裝置210a設置於第二半導體裝置210b及第二半導體裝置210c旁。第二半導體裝置210a、第二半導體裝置210b、第二半導體裝置210c的厚度T2、厚度T3、厚度T4可相同。在這種情況下，從上部表面222到第二半導體裝置210a、第二半導體裝置210b及第二半導體裝置210c中的最頂部表面212b的最短距離T1'大於或實質上等於第二半導體裝置210a、第二半導體裝置210b及第二半導體裝置210c中任一個的厚度T2、厚度T3或厚度T4的兩倍。在其它實施例中，第二半導體裝置210a、第二半導體裝置210b及第二半導體裝置210c的厚度T2、厚度T3及厚度T4可不同。舉例來說，第二半導體裝置210b的厚度T3大於第二半導體裝置210c的厚度T4。在這種情況下，從上部表面222到第二半導體裝置210b的最頂部表面212b的最短距離T1'大於或實質上等於第二半導體裝置210b的厚度T3的兩倍（即如果T3≥T4，那麼T1'≧2×T3）。在這種情況下，從上部表面222到第二半導體裝置210a的頂部表面212a的距離T1也將大於或實質上等於厚度T2的兩倍，這是因為厚度T3與厚度T4的總和大於厚度T2。當然，如果厚度T2大於厚度T3與厚度T4的總和，則從上部表面222到頂部表面212a的距離T1成為距離T1及距離T1'中的最短距離，那麼最短距離T1在決定第二封裝件200''的翹曲方面具有關鍵性。應注意，第二封裝件200''中的第二半導體裝置210a、第二半導體裝置210b、第二半導體裝置210c的配置及數量僅用於說明，且本發明實施例不限於此。
通過這種配置，第二封裝件200''將在熱製程之後呈凹形翹曲輪廓形式，這意味著第一封裝件100與第二封裝件200''之間的間隙寬度從週邊區域A2到中心區域A1逐漸減小。由此，在使底部填充膠400從週邊區域A2分配且流向中心區域A1時，底部填充膠400可由於毛細作用而輕易地在中心區域A1上方流動，且填充第一封裝件100與第二封裝件200''之間的間隙而沒有空隙形成。因此，本發明實施例中的疊層封裝結構的良率（yield rates）明顯提升。
基於以上論述，可見本發明實施例提供各種優勢。然而，應理解，並非所有優勢都必須在本文中論述，且其它實施例可提供不同優勢，並且對於所有實施例並不需要特定優勢。
根據本發明的一些實施例，疊層封裝結構包括一第一封裝件、多個導電凸塊、一第二封裝件以及一底部填充膠。導電凸塊設置在第一封裝件的一第二表面上且電性連接到第一封裝件。第二封裝件通過導電凸塊設置在第一封裝件的第二表面上並包括一半導體裝置以及包封半導體裝置的一包封材料。從包封材料的一上部表面到半導體裝置的一上部表面的一最短距離大於或實質上等於半導體裝置的一厚度的兩倍。底部填充膠填充在第一封裝件與第二封裝件之間。
根據本發明的一些實施例，所述多個導電凸塊設置在所述第二表面的一週邊區域上。
根據本發明的一些實施例，所述第二封裝件的一下部表面朝向所述第一封裝件的所述第二表面彎曲，其中所述下部表面面向所述第二表面。
根據本發明的一些實施例，從所述第二表面的一中心區域到所述第二封裝件的一最短距離實質上小於從所述第二表面的一週邊區域上的任何位置到所述第二封裝件的一最短距離。
根據本發明的一些實施例，從所述包封材料的一上部表面到所述半導體裝置的一上部表面的一最短距離大於或實質上等於所述半導體裝置的一厚度的兩倍。
根據本發明的一些實施例，所述第二封裝件包括多個半導體裝置以及包封所述多個半導體裝置的所述包封材料。
根據本發明的一些實施例，從所述包封材料的一上部表面到所述多個半導體裝置的一最頂部表面的一最短距離大於或實質上等於所述多個半導體裝置的一最大厚度的兩倍。
根據本發明的一些實施例，所述底部填充膠覆蓋所述第二表面的一中心區域以及一週邊區域，以及包封所述導電凸塊。
根據本發明的一些實施例，疊層封裝結構包括一第一封裝件、多個導電凸塊、一第二封裝件以及一底部填充膠。第一封裝件包括一包封的半導體裝置以及一重佈線結構。包封的半導體裝置包括一第一半導體裝置、包封第一半導體裝置的一第一包封材料以及延伸穿過第一包封材料的多個通孔。重佈線結構設置在包封的半導體裝置的一第一表面上且電性連接到包封的半導體裝置。導電凸塊設置在包封的半導體裝置的一第二表面上且電性連接到包封的半導體裝置。第二表面與第一表面相對。第二封裝件設置在包封的半導體裝置的第二表面上並包括一第二半導體裝置以及包封第二半導體裝置的一第二包封材料。從第二包封材料的一上部表面到第二半導體裝置的一上部表面的一最短距離大於或實質上等於第二半導體裝置的一厚度的兩倍。底部填充膠填充在第一封裝件與第二封裝件之間。
根據本發明的一些實施例，從所述第二表面的一中心區域到所述第二封裝件的一最短距離小於從所述第二表面的一週邊區域上的任何位置到所述第二封裝件的一最短距離。
根據本發明的一些實施例，所述多個導電凸塊設置在所述週邊區域上。
根據本發明的一些實施例，所述底部填充膠覆蓋所述中心區域以及所述週邊區域，以及包封所述導電凸塊。
根據本發明的一些實施例，所述第二半導體裝置的數量是多個，以及所述第二包封材料包封所述多個第二半導體裝置。
根據本發明的一些實施例，從所述第二包封材料的一上部表面到所述多個第二半導體裝置的一最頂部表面的一最短距離大於或實質上等於所述多個第二半導體裝置的一最大厚度的兩倍。
根據本發明的一些實施例，所述第二封裝件的一下部表面朝向所述第二表面彎曲。
根據本發明的一些實施例，疊層封裝結構包括一第一封裝件、多個導電凸塊、一第二封裝件以及一底部填充膠。第一封裝件包括一包封的半導體裝置以及一重佈線結構，所述重佈線結構設置在包封的半導體裝置的一第一表面上且電性連接到包封的半導體裝置。導電凸塊設置在包封的半導體裝置的一第二表面上且電性連接到包封的半導體裝置。第二封裝件通過導電凸塊設置在第二表面上並包括多個半導體裝置以及包封半導體裝置的一包封材料。從包封材料的一上部表面到半導體裝置的一最頂部表面的一最短距離大於或實質上等於半導體裝置的一最大厚度的兩倍。底部填充膠填充在第一封裝件與第二封裝件之間。
根據本發明的一些實施例，從所述第二表面的一中心區域到所述第二封裝件的一最短距離小於從所述第二表面的一週邊區域上的任何位置到所述第二封裝件的一最短距離。
根據本發明的一些實施例，所述第二封裝件的一下部表面朝向所述第二表面彎曲。
根據本發明的一些實施例，所述多個半導體裝置以並排方式佈置。
根據本發明的一些實施例，所述多個半導體裝置彼此堆疊。
雖然本發明實施例已以實施例揭露如上，然其並非用以限定本發明實施例，任何所屬技術領域中具有通常知識者，在不脫離本發明實施例的精神和範圍內，當可作些許的更動與潤飾，故本發明實施例的保護範圍當視後附的申請專利範圍所界定者為準。
10、10'、10''‧‧‧疊層封裝結構
100‧‧‧第一封裝件
101‧‧‧包封的半導體裝置
110、110a‧‧‧第一半導體裝置
112‧‧‧基板
113‧‧‧接墊
114‧‧‧導通孔
116、116a、143‧‧‧介電層
120、120a‧‧‧第一包封材料
130‧‧‧通孔
140、230‧‧‧重佈線結構
142‧‧‧重佈線路
144‧‧‧凸塊下金屬層
160‧‧‧載體
165‧‧‧黏著劑層
170、170a‧‧‧絕緣層
172‧‧‧開口
182‧‧‧電性連接件
184‧‧‧集成被動裝置
200、200'、200''‧‧‧第二封裝件
201‧‧‧下部表面
210、210a、210b、210c‧‧‧第二半導體裝置
212、222‧‧‧上部表面
212a、212b‧‧‧頂部表面
220、220’‧‧‧第二包封材料
300‧‧‧導電凸塊
400‧‧‧底部填充膠
A1‧‧‧中心區域
A2‧‧‧週邊區域
D1、D2、T1、T1'‧‧‧最短距離
S1‧‧‧第一表面
S2‧‧‧第二表面
T2、T3、T4‧‧‧厚度
結合附圖閱讀以下詳細說明，會最好地理解本發明實施例的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1到圖8說明根據本發明的一些示範性實施例的製造疊層封裝結構中的中間階段的剖面圖。 圖9描繪說明在指定溫度下第二封裝件的翹曲與底部填充膠失敗率之間的關係的圖。 圖10描繪說明在另一指定溫度下第二封裝件的翹曲與底部填充膠失敗率之間的關係的圖。 圖11說明根據本發明的一些示範性實施例的疊層封裝結構的剖面圖。 圖12說明根據本發明的一些示範性實施例的疊層封裝結構的剖面圖。

Claims (1)

  1. 一種疊層封裝結構，包括： 一第一封裝件； 多個導電凸塊，設置在所述第一封裝件的一第二表面上以及電連接到所述第一封裝件； 一第二封裝件，通過所述多個導電凸塊設置在所述第一封裝件的所述第二表面上並包括一半導體裝置以及包封所述半導體裝置的一包封材料，其中從所述包封材料的一上部表面到所述半導體裝置的一上部表面的一最短距離大於或實質上等於所述半導體裝置的一厚度的兩倍；以及 一底部填充膠，填充在所述第一封裝件與所述第二封裝件之間。
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