TW201826409A - 半導體封裝、封裝上封裝及其製造方法 - Google Patents

半導體封裝、封裝上封裝及其製造方法 Download PDF

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TW201826409A
TW201826409A TW106130964A TW106130964A TW201826409A TW 201826409 A TW201826409 A TW 201826409A TW 106130964 A TW106130964 A TW 106130964A TW 106130964 A TW106130964 A TW 106130964A TW 201826409 A TW201826409 A TW 201826409A
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semiconductor package
package
semiconductor
layer structure
redistribution layer
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TW106130964A
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English (en)
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于達人
洪佑昇
許文松
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聯發科技股份有限公司
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Publication of TW201826409A publication Critical patent/TW201826409A/zh

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本發明提供了一種半導體封裝、封裝上封裝及其製造方法。其中該半導體封裝的製造方法包括：提供一載體基板；在該載體基板上形成一重分佈層結構，其中該重分佈層結構包括：至少一凸塊墊；在該重分佈層結構上安裝一半導體晶粒；在該半導體晶粒以及該重分佈層結構上形成一成型模料；移除該載體基板，以露出該重分佈層結構的複數個焊球墊；以及於該等焊球墊上形成複數個導電結構。

Description

半導體封裝、封裝上封裝及其製造方法
本發明涉及半導體封裝技術，特別係涉及一種半導體封裝、封裝上封裝（package-on-package，PoP）及其製造方法。
FOWLP（Fan-out wafer level packaging，扇出晶圓級封裝）係一種晶圓級處理中的嵌入式封裝方法，並且也係一種用來封裝大量具有高集成靈活度的I/O（Input/output，輸入/輸出）的先進封裝技術。
一般地，在FOWLP製程中，複數個半導體晶粒以面向下地方式放置在臨時的帶載體（tape carrier）上。該等半導體晶粒與該臨時帶載體使用成型模料來包覆成型。在成型之後，移除該帶載體，留下該等半導體晶粒的主動面從一般被稱為重構晶圓（reconstituted wafer）的結構中露出。
接著，在該重構晶圓的頂面上形成一RDL（redistribution layer，重分佈層）結構。BGA（Ball Grid Array，球柵陣列）錫球附著至該RDL結構上，並且接著分割該重構晶圓以形成單獨的封裝。
因此，本發明之主要目的即在於提供一種半導體封裝、封裝上封裝及其製造方法。
根據本發明至少一個實施例的一種半導體封裝，包括：一重分佈層結構，具有相對的第一及第二表面，其中該重分佈層結構包括：至少一凸塊墊，位於該第一表面上；一半導體晶粒，安裝於該重分佈層結構的該第一表面上，其中該半導體晶粒為以其主動面面向該重分佈層結構的覆晶，其中，複數個I/O墊設置在該半導體晶粒的該主動面上，其中在每個I/O墊上設置一連接元件，其中，該連接元件連接該凸塊墊；一成型模料，包封該半導體晶粒並且覆蓋該重分佈層結構的該第一表面；以及複數個導電結構，安裝在該重分佈層結構的該第二表面上。
根據本發明至少一個實施例的一種封裝上封裝，包括：底部半導體封裝，該底部半導體封裝為如上所述的半導體封裝，其中該底部半導體封裝進一步包括：複數個穿過該成型模料的穿模通孔；以及一上部半導體封裝，安裝在該底部半導體封裝上，並且該上部半導體封裝通過該等穿模通孔電性連接至該下部半導體封裝。
根據本發明至少一個實施例的一種半導體封裝的製造方法，包括：提供一載體基板；在該載體基板上形成一重分佈層結構，其中該重分佈層結構包括：至少一凸塊墊；在該重分佈層結構上安裝一半導體晶粒；在該半導體晶粒以及該重分佈層結構上形成一成型模料；移除該載體基板，以露出該重分佈層結構的複數個焊球墊；以及於該等焊球墊上形成複數個導電結構。
根據本發明至少一個實施例的一種封裝上封裝的製造方法，包括：採用上述的製造半導體封裝的方法來形成一半導體封裝；將該半導體封裝切割為一晶粒封裝，其中該晶粒封裝作為該封裝上封裝的底部半導體封裝；以及在該底部半導體封裝上安裝一上部半導體封裝，其中該上部半導體封裝通過複數個貫穿該成型模料的穿模通孔電性連接至該底部半導體封裝。
本發明實施例的半導體封裝的製造方法，採用後晶粒（die-last）製程，即先形成重分佈層結構，然後再將半導體晶粒安裝於重分佈層結構上，因此能夠保證安裝的晶粒都是已知合格的晶粒，從而提高產品的良品率。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
本發明的一個或複數個實現將參考所附的圖式來進行描述，其中通篇中，類似的參考符號用來表示類似的元件，並且示出的結構並不必按比例繪制。術語“晶粒（die）”、“晶片（chip）”、“半導體晶片”以及“半導體晶粒”在整個說明書中可以互換使用。
本發明涉及一種具有RDL結構的扇出半導體封裝，封裝上封裝（PoP）及其製造方法。
第1至5圖示出了根據本發明一個實施例的一種半導體封裝的製造方法。
如第1圖所示，提供了一載體基板100。根據一個實施例，該載體基板100可以包括：玻璃、矽、陶瓷或者金屬，但是不限制於此。根據一個實施例，一釋放層（release layer）102形成於該載體基板100的頂面上。
接著，一RDL結構120形成於該釋放層125上。該RDL結構120可以包括：至少一介電層125，一第一金屬層121，一第二金屬層122，以及一通孔123，其中該通孔123電性連接該第一金屬層121和該第二金屬層122。
根據一個實施例，例如，第一金屬層121可以包括：一導電元件墊121a，以及第二金屬層122可以包括：一凸塊墊122a，一金屬跡線（trace）122b以及一接墊（pad）122c。可以理解的是，在圖式中所描繪的RDL結構120中的層和圖案僅係作為說明的目的。RDL結構120中的金屬層的數量可以取決於設計要求，例如RDL結構120中的金屬層可以為多層，例如包括：第一、第二以及第三金屬層，其中第一與第二金屬層之間通過第一介電層隔開，第二與第三金屬層之間通過第二介電層隔開。
根據一個實施例，第一金屬層121和第二金屬層122可以包括：鋁、銅、鎢、鈦、氮化鈦，等等。介電層125可以包括：任何合適的絕緣材料，包括但不限於：PID（Photo Image Dielectric，光成像介電質）材料，預浸材料（prepreg）或者樹脂材料，諸如ABF（Ajinomoto Build-up Film，曰本味之素公司所供應的一種環氧樹脂絕緣膜）或類似物。
根據一個實施例，介電層125中的金屬圖案可以通過增層法（build-up process）和電鍍製程來形成，但是不限制於此。在另一實施例中，介電層125可以包括：無機材料，諸如矽氧化物、矽氮化物或類似物，以及介電層125中的金屬圖案可以由微影製程與蝕刻製程來形成。
根據一個實施例，介電層125中形成的金屬跡線或金屬圖案可以具有介於1~10µm（微米）的線寬，例如3 µm、5 µm或者7 µm；並且，兩相鄰線之間的間隔介於1~10µm之間，例如3 µm、5 µm或者7 µm，但是不限制於此。
根據一個實施例，可選地，在RDL結構120形成之後，一焊料遮罩130形成於介電層125和第二金屬層122上。該焊料遮罩130可以包括：複數個開口131，分別露出第二金屬層122的凸塊墊122a以及接墊122c。可選地，一OSP（Organic Solderability Preservatives，有機保焊）膜（未示出）可以應用至凸塊墊122a以及接墊122c的露出的表面上。
如第2圖所示，在形成RDL結構120之後，複數個半導體晶粒200可以安裝於RDL結構120上的晶片安裝區域中。根據一個實施例，每個半導體晶粒200均為其主動面200a向下面向RDL結構120的覆晶。複數個I/O墊201可以設置在每個半導體晶粒200的主動面200a上。諸如金屬凸塊或金屬柱等連接元件202可以設置在每個I/O墊201上。連接元件202例如通過焊料203連接至對應的凸塊墊122a。
可選地，一電子元件210，例如該電子元件120為諸如解耦電容、電阻或電感等被動元件，可以安裝至該RDL結構120上。例如，該電子元件210通過使用SMT（Surface Mount Technique，表面安裝技術）來安裝於接墊122c上。
如第3圖所示，在RDL結構120上安裝了半導體晶粒200之後，應用一成型模料300。該成型模料300至少覆蓋半導體晶粒200，電子元件210，以及RDL結構120的頂面，從而形成晶圓級封裝10。根據一個實施例，可以對成型模料300施加一固化製程。該成型模料300可以包括：環氧樹脂與二氧化矽填充物的混合物，但是不限制於此。
根據另一實施例，如第4圖所示，在形成成型模料300之前，一底部填充材料（underfill）310可以應用在每個半導體晶粒200和RDL結構120之間。底部填充材料310可以為填充了二氧化矽的環氧樹脂，但是不限制於此。底部填充材料310填充每個半導體晶粒200和RDL結構120之間的間隙（或間隔）。
接著，移除載體基板100和釋放層102，從而露出RDL結構120的底面。通過使用加熱、雷射、UV/IR（紫外/紅外）輻射或者機械剝離來執行載體基板100的解接合（de-bonding），但是不限制於此。在移除了載體基板100之後，暴露第一金屬層121的導電元件墊121a。
根據一個實施例，沒有金屬飾面（metal finish）形成於第一金屬層121的導電元件墊121a上。該第一金屬層121的厚度可以介於1~20μm之間，例如7μm或12μm。根據另一實施例，諸如Ni，Au及/或其他基本金屬等金屬飾面可以形成於第一金屬層121的導電元件墊121a上。
接著，複數個導電結構410分別設置在第一金屬層121的導電元件墊121a上，以完成半導體封裝10。接著，對該半導體封裝10施加晶圓切割製程並且將該半導體封裝10單個化為獨立的晶粒封裝1。根據一個實施例，導電結構410可以為焊料球，焊料凸塊，銅柱凸塊，或者他們的任意組合，但是不限制於此。
第5圖為根據本發明實施例的PoP的橫截面示意圖。如第5圖所示，形成複數個用於進一步連接的TMV320，其中該等TMV320穿過成型模料300的整個厚度。根據一個實施例，可以通過將複數個通孔鑽入成型模料30中，並且使用諸如銅等金屬來填充該等通孔，從而形成TMV320。TMV320可以在晶圓切割製程之前形成，但是不限制於此。
在示出的PoP組態中，晶粒封裝1起底部封裝的功能，一上部封裝2直接安裝於該晶粒封裝1上。例如，該上部封裝可以為DRAM晶片封裝，但是不限制於此。上部封裝2可以包括：一晶片（諸如DRAM晶片，未示出），該晶片可以通過TMV320和RDL120電性連接至底部封裝。上部封裝2可以包括複數個連接元件21（諸如導電結構或凸塊），用來連接上部封裝2和TMV320。
第6至9圖示出了根據本發明另一實施例的TMV和PoP的製造方法，其中，類似的參考符號表示類似的元件、層或區域。
如第6圖所示，類似地，提供了一載體基板100。該載體基板100可以包括：玻璃、矽、陶瓷或金屬，但是不限制於此。一釋放層102可以形成於載體基板100的頂面上。接著，一RDL結構120形成於該釋放層102上。
該RDL結構120可以包括至少一介電層125，一第一金屬層121，一第二金屬層122以及一通孔123，其中通孔123電性連接該第一金屬層121和該第二金屬層122。該第一金屬層121可以包括：一導電元件墊121a，以及該第二金屬層122可以包括：一凸塊墊122a，一金屬跡線122b，一接墊122c和接墊122d。
在RDL結構120形成之後，焊料遮罩130可以形成於介電層125和第二金屬層122上。焊料遮罩130可以包括：複數個開口131，分別露出第二金屬層122的凸塊墊122a、接墊122c及122d。
接著，複數個金屬柱320a形成於位於RDL結構120的外圍區域處的接墊122d上，其中該外圍區域可以係該RDL結構120中除了晶片安裝區域之外的區域或者圍繞晶片安裝區域的區域。例如，為了形成金屬柱320a，光阻層（未示出）形成於RDL結構120上。接著，執行一微影製程以在光阻層中形成通孔開口。通孔開口對齊接墊122d。接著，通過CVD（Chemical Vapor Deposition，化學氣相沉積）、PVD（Physical Vapor Deposition，物理氣相沉積）、ALD（Atomic Layer Deposition，原子層沉積）或電鍍製程來將諸如銅等金屬沉積在通孔開口中。接著，移除光阻層。
如第7圖所示，在形成金屬柱320a之後，將複數個半導體晶粒200安裝在RDL結構120上的晶片安裝區域內。根據一個實施例，每個半導體晶粒200為以其主動面向下面向RDL結構120的覆晶。複數個I/O墊201可以設置在每個半導體晶粒200的主動面200a上。諸如金屬凸塊或金屬柱等連接元件202可以設置在每個I/O墊201上。連接元件202例如通過焊料203連接至對應的凸塊墊122a。
可選地，一電子元件210，諸如解耦電容、電阻或電感，可以安裝至RDL結構120上。例如，電子元件210可以通過使用SMT來安裝在接墊122c上。
如第8圖所示，在RDL結構120上安裝了半導體晶粒200之後，施加一成型模料300。該成型模料300至少覆蓋半導體晶粒200，電子元件210，金屬柱320a以及RDL結構120的頂面，從而形成晶圓級封裝10。可選地，可以執行CMP（Chemical Mechanical Polishing，化學機械研磨）製程以暴露金屬柱320a的頂面，從而形成TMV320。
接著，移除載體基板100和釋放層102，從而露出RDL結構120的底面。通過使用加熱、雷射、UV/IR輻射或者機械剝離來執行載體基板100的解接合（de-bonding），但是不限制於此。在移除了載體基板100之後，暴露第一金屬層121的導電元件墊121a。
接著，導電結構410可以分別設置在第一金屬層121的導電元件墊121a上，以完成半導體封裝10。接著，對該半導體封裝10執行晶圓切割製程並且將該半導體封裝10單個化為獨立的晶粒封裝（或半導體封裝）1。
如第9圖所示，上部封裝2安裝於晶粒封裝1上。例如，上部封裝2可以為DRMA晶片封裝，但是不限制於此。上部封裝2可以包括：晶片（諸如DRAM晶片，未示出），該晶片可以通過TMV320和RDL結構120電性連接至下部封裝。該上部封裝2可以包括：複數個連接元件，諸如導電結構或凸塊，用來連接上部封裝2與TMV320。
本發明實施例的半導體封裝的製造方法，由於採用後晶粒（die-last）製程，即先形成RDL結構，然後再將半導體晶粒安裝於重分佈層結構上，因此能夠保證安裝的晶粒都是已知合格的晶粒，從而提高產品的良品率。另外，本發明實施例形成的半導體封裝，對於RDL結構中第一表面（晶粒所接合的表面）上的的導電跡線而言，其位於晶粒區（即俯視時半導體晶粒在RDL結構上的投影區域）的部分和位於晶粒區外的部分之間不會存在偏移，而傳統的採用先晶粒（die-first）的方案，即先安裝晶粒後形成RDL結構，則會存在偏移。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100‧‧‧載體基板；
102‧‧‧釋放層；
120‧‧‧RDL結構；
125‧‧‧介電層；
121‧‧‧第一金屬層；
122‧‧‧第二金屬層；
123‧‧‧通孔；
121a‧‧‧導電元件墊；
122a‧‧‧凸塊墊；
122b‧‧‧金屬跡線；
122c、122d‧‧‧接墊；
130‧‧‧焊料遮罩；
131‧‧‧開口；
200‧‧‧半導體晶粒；
200a‧‧‧主動面
201‧‧‧I/O墊
203‧‧‧焊料
202、21‧‧‧連接元件
210‧‧‧電子元件
300‧‧‧成型模料
10‧‧‧晶圓級封裝/半導體封裝
310‧‧‧底部填充材料
410‧‧‧導電結構
1‧‧‧晶粒封裝
320‧‧‧TMV
2‧‧‧上部封裝
320a‧‧‧金屬柱
包含所附的圖式以提供對實施例的進一步理解，並且該所附的圖式納入該說明書中並構成該說明書的一部分。圖式示意了實施例的一部分，並且連同描述一起來解釋本發明的原理。在圖式中： 第1至5圖示出了根據本發明實施例的半導體封裝的製造方法，其中第4圖示出了一種具有底部填充材料的半導體封裝，其中該底部填充材料位於半導體晶粒與RDL結構之間，以及第5圖示出了一種PoP（封裝上封裝或者堆疊封裝）；以及 第6至9圖示出了根據本發明另一實施例的TMV（Through Mold Via，穿模通孔）和PoP的製造方法。

Claims (13)

  1. 一種半導體封裝，包括： 一重分佈層結構，具有相對的第一及第二表面，其中該重分佈層結構包括：至少一凸塊墊，位於該第一表面上； 一半導體晶粒，安裝於該重分佈層結構的該第一表面上，其中該半導體晶粒為以其主動面面向該重分佈層結構的覆晶，其中，複數個I/O墊設置在該半導體晶粒的該主動面上，其中在每個I/O墊上設置一連接元件，其中，該連接元件連接該凸塊墊； 一成型模料，包封該半導體晶粒並且覆蓋該重分佈層結構的該第一表面；以及 複數個導電結構，安裝在該重分佈層結構的該第二表面上。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該重分佈層結構包括：至少一介電層，一位於該第一表面上的第一金屬層，一位於該第二表面上的第二金屬層，以及至少一通孔，其中該通孔電性連接該第一金屬層與該第二金屬層。
  3. 如申請專利範圍第1項所述的半導體封裝，其中該連接元件包括：一金屬凸塊或者一金屬柱；及/或，該連接元件通過焊料連接至該凸塊墊。
  4. 如申請專利範圍第1項所述的半導體封裝，其中進一步包括：一電子元件，安裝在該重分佈層結構的該第一表面上。
  5. 如申請專利範圍第1項所述的半導體封裝，其中進一步包括：一底部填充材料，設置在該半導體晶粒和該重分佈層結構之間。
  6. 一種封裝上封裝，包括： 底部半導體封裝，該底部半導體封裝為如申請專利範圍第1~5項中任一項所述的半導體封裝，其中該底部半導體封裝進一步包括：複數個穿過該成型模料的穿模通孔；以及 一上部半導體封裝，安裝在該底部半導體封裝上，並且該上部半導體封裝通過該等穿模通孔電性連接至該底部半導體封裝。
  7. 一種半導體封裝的製造方法，包括： 提供一載體基板； 在該載體基板上形成一重分佈層結構，其中該重分佈層結構包括：至少一凸塊墊； 在該重分佈層結構上安裝一半導體晶粒； 在該半導體晶粒以及該重分佈層結構上形成一成型模料； 移除該載體基板，以露出該重分佈層結構的複數個焊球墊；以及 於該等焊球墊上形成複數個導電結構。
  8. 如申請專利範圍第7項所述的半導體封裝的製造方法，其中該載體基板包括：玻璃、矽、陶瓷或金屬。
  9. 如申請專利範圍第7項所述的半導體封裝的製造方法，其中該半導體晶粒為以其主動面面向該重分佈層結構的覆晶； 其中，複數個I/O墊設置在該半導體晶粒的主動面上； 其中，在每個I/O墊上設置一連接元件，並且該連接元件連接至該凸塊墊。
  10. 如申請專利範圍第7項所述的半導體封裝的製造方法，其中在該半導體晶粒和該重分佈層結構上形成該成型模料之後，該方法進一步包括：在該成型模料中形成複數個穿模通孔。
  11. 如申請專利範圍第10項所述的半導體封裝的製造方法，其中在該成型模料中形成複數個穿模通孔的步驟包括：將複數個通孔鑽入該成型模料中；以及使用金屬來填充該等通孔。
  12. 如申請專利範圍第8項所述的半導體封裝的製造方法，其中在該重分佈層結構上安裝該半導體晶粒之前，該方法進一步包括：在該重分佈層結構上形成複數個金屬柱；其中該成型模料還包封該等金屬柱，並且該等金屬柱的頂面從該成型模料中露出以作為穿模通孔。
  13. 一種封裝上封裝的製造方法，包括： 採用如申請專利範圍第7~12項中任一項所述的製造半導體封裝的方法來形成一半導體封裝； 將該半導體封裝切割為一晶粒封裝，其中該晶粒封裝作為該封裝上封裝的底部半導體封裝；以及 在該底部半導體封裝上安裝一上部半導體封裝，其中該上部半導體封裝通過複數個穿過該成型模料的穿模通孔電性連接至該底部半導體封裝。
TW106130964A 2016-09-12 2017-09-11 半導體封裝、封裝上封裝及其製造方法 TW201826409A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI671873B (zh) * 2018-10-30 2019-09-11 力成科技股份有限公司 半導體封裝結構
TWI820221B (zh) * 2018-09-28 2023-11-01 日商迪思科股份有限公司 半導體封裝件之製造方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9515017B2 (en) * 2014-12-18 2016-12-06 Intel Corporation Ground via clustering for crosstalk mitigation
KR20170053416A (ko) * 2015-11-06 2017-05-16 주식회사 엘지화학 반도체 장치 및 반도체 장치의 제조 방법
US10211071B2 (en) * 2016-01-29 2019-02-19 Nxp B.V. IC packaging method and a packaged IC device
CN106601627A (zh) * 2016-12-21 2017-04-26 江苏长电科技股份有限公司 先封后蚀电镀铜柱导通三维封装结构的工艺方法
TWI666743B (zh) * 2017-09-29 2019-07-21 英屬開曼群島商鳳凰先驅股份有限公司 感測器封裝件及其製作方法
WO2019227436A1 (zh) * 2018-05-31 2019-12-05 华为技术有限公司 一种倒装芯片的封装结构及电子设备
KR102536269B1 (ko) * 2018-09-14 2023-05-25 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10903561B2 (en) * 2019-04-18 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
KR102494920B1 (ko) * 2019-05-21 2023-02-02 삼성전자주식회사 반도체 패키지
CN110349861A (zh) * 2019-06-27 2019-10-18 深圳第三代半导体研究院 一种新型PoP封装结构及其制作方法
KR102551352B1 (ko) 2019-06-28 2023-07-04 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
KR20210011279A (ko) 2019-07-22 2021-02-01 삼성전자주식회사 반도체 패키지
US11862587B2 (en) 2019-07-25 2024-01-02 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
CN111106013B (zh) * 2019-10-31 2022-03-15 广东芯华微电子技术有限公司 Tmv结构的制备方法、大板扇出型异构集成封装结构及其制备方法
KR20210120532A (ko) 2020-03-27 2021-10-07 삼성전자주식회사 반도체 패키지
US20210366852A1 (en) * 2020-05-25 2021-11-25 Nanya Technology Corporation Semiconductor structure and method of forming the same
US11430776B2 (en) * 2020-06-15 2022-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacturing
CN111883437B (zh) * 2020-07-03 2023-04-25 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
CN115050654B (zh) * 2022-08-17 2022-11-08 甬矽电子(宁波)股份有限公司 扇入型封装结构的制备方法和扇入型封装结构
CN117737653B (zh) * 2023-12-19 2024-08-16 深圳市知音科技有限公司 可剥铜载板及其制备方法以及其在先进封装中的应用

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100909322B1 (ko) 2007-07-02 2009-07-24 주식회사 네패스 초박형 반도체 패키지 및 그 제조방법
US8871568B2 (en) * 2012-01-06 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and method of forming the same
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9478474B2 (en) 2012-12-28 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for forming package-on-packages
US10269619B2 (en) 2013-03-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
US9721922B2 (en) * 2013-12-23 2017-08-01 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package
JP2016021475A (ja) * 2014-07-14 2016-02-04 イビデン株式会社 プリント配線板
KR20160023975A (ko) * 2014-08-21 2016-03-04 삼성전자주식회사 반도체 패키지

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI820221B (zh) * 2018-09-28 2023-11-01 日商迪思科股份有限公司 半導體封裝件之製造方法
TWI671873B (zh) * 2018-10-30 2019-09-11 力成科技股份有限公司 半導體封裝結構

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