CN107818956A - 半导体封装、封装上封装及其制造方法 - Google Patents

半导体封装、封装上封装及其制造方法 Download PDF

Info

Publication number
CN107818956A
CN107818956A CN201710800845.2A CN201710800845A CN107818956A CN 107818956 A CN107818956 A CN 107818956A CN 201710800845 A CN201710800845 A CN 201710800845A CN 107818956 A CN107818956 A CN 107818956A
Authority
CN
China
Prior art keywords
semiconductor
package
layer structure
redistribution layer
manufacture method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201710800845.2A
Other languages
English (en)
Inventor
于达人
洪佑昇
许文松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN107818956A publication Critical patent/CN107818956A/zh
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明实施例公开了一种半导体封装、封装上封装及其制造方法。其中该制造方法包括：提供载体基板；在该载体基板上形成重分布层结构，其中该重分布层结构包括：至少一凸块垫；在该重分布层结构上安装半导体晶粒；在该半导体晶粒以及该重分布层结构上形成模塑料；移除该载体基板，以露出该重分布层结构的多个焊球垫；以及于该多个焊球垫上形成多个导电结构。本发明实施例，可以提高产品的良品率。

Description

半导体封装、封装上封装及其制造方法
技术领域
本发明涉及半导体封装技术，尤其涉及一种半导体封装、封装上封装(package-on-package，PoP)及其制造方法。
背景技术
FOWLP(Fan-out wafer level packaging，扇出晶圆级封装)是一种晶圆级处理中的嵌入式封装方法，并且也是一种用来封装大量具有高集成灵活度的I/O(Input/output，输入/输出)的先进封装技术。
一般地，在FOWLP工艺中，多个半导体晶粒以面向下地方式放置在临时的磁带载体(tape carrier)上。该多个半导体晶粒与该临时磁带载体使用模塑料来包覆成型。在成型之后，移除该磁带载体，留下该多个半导体晶粒的主动面从一般被称为重构晶圆(reconstituted wafer)的结构中露出。
接着，在该重构晶圆的顶面上形成RDL(redistribution layer，重分布层)结构。BGA(Ball Grid Array，球栅阵列)球附着至该RDL结构上，并且接着分割该重构晶圆以形成单独的封装。
发明内容
有鉴于此，本发明实施例提供了一种半导体封装、封装上封装及其制造方法。
本发明提供了一种半导体封装的制造方法，包括：提供载体基板；在该载体基板上形成重分布层结构，其中该重分布层结构包括：至少一凸块垫；在该重分布层结构上安装半导体晶粒；在该半导体晶粒以及该重分布层结构上形成模塑料；移除该载体基板，以露出该重分布层结构的多个焊球垫；以及于该多个焊球垫上形成多个导电结构。
其中，该载体基板包括：玻璃、硅、陶瓷或金属。
其中，该半导体晶粒为以其主动面面向该重分布层结构的倒装芯片，其中，多个I/O垫设置在该半导体晶粒的主动面上。
其中，在每个I/O垫上设置连接元件，并且该连接元件连接至该凸块垫。
其中，在该半导体晶粒和该重分布层结构上形成该模塑料之后，该方法进一步包括：在该模塑料中形成多个穿模通孔。
其中，在该模塑料中形成多个穿模通孔的步骤包括：将多个通孔钻入该模塑料中；以及使用金属来填充该多个通孔。
其中，在该重分布层结构上安装该半导体晶粒之前，该方法进一步包括：在该重分布层结构上形成多个金属柱；其中该模塑料还包封该多个金属柱，并且该多个金属柱的顶面从该模塑料中露出以作为穿模通孔。
本发明实施例提供了一种封装上封装的制造方法，包括：采用如上所述的制造半导体封装的方法来形成半导体封装；将该半导体封装切割为晶粒封装，其中该晶粒封装作为该封装上封装的底部半导体封装；以及在该底部半导体封装上安装上部半导体封装，其中该上部半导体封装通过多个穿过该模塑料的穿模通孔电性连接至该底部半导体封装。
本发明实施例提供了一种封装上封装的制造方法，包括：形成底部半导体封装；以及在该底部半导体封装上安装上部半导体封装，并且该上部半导体封装电性连接至该底部半导体封装；其中，形成该底部半导体封装的步骤包括：形成重分布层结构，其中该重分布层结构具有相对的第一表面与第二表面，并且该重分布层结构包括：至少一位于该第一表面上的凸块垫；以倒装芯片的方式将半导体晶粒安装于该重分布层结构上，其中该半导体晶粒的主动面上设置了多个I/O垫，并且在每个I/O垫上设置连接元件，其中该连接元件连接至对应的凸块垫；使用模塑料来封装该半导体晶粒；在该模塑料中形成多个穿模通孔；以及在该重分布层结构的该第二表面上形成多个导电结构；其中，该上部半导体封装通过该多个穿模通孔电性连接至该底部半导体封装。
其中，该连接元件包括：金属凸块或者金属柱。
其中，该连接元件通过焊料连接至该凸块垫。
其中，进一步包括：电子元件，安装于该重分布层结构的该第一表面上。
其中，该电子元件包括：电容、电阻或电感。
其中，进一步包括：在该半导体晶粒与该重分布层结构之间插入底部填充材料。
本发明实施例提供了一种半导体封装，包括：重分布层结构，具有相对的第一及第二表面，其中该重分布层结构包括：至少一凸块垫，位于该第一表面上；半导体晶粒，安装于该重分布层结构的该第一表面上，其中该半导体晶粒为以其主动面面向该重分布层结构的倒装芯片，其中，多个I/O垫设置在该半导体晶粒的该主动面上，其中在每个I/O垫上设置连接元件，其中，该连接元件连接该凸块垫；
模塑料，包封该半导体晶粒并且覆盖该重分布层结构的该第一表面；以及
多个导电结构，安装在该重分布层结构的该第二表面上。
其中，该重分布层结构包括：至少一介电层，位于该第一表面上的第一金属层，位于该第二表面上的第二金属层以及至少一通孔，其中该通孔电性连接该第一金属层与该第二金属层。
其中，该连接元件包括：金属凸块或者金属柱；及/或，该连接元件通过焊料连接至该凸块垫。
其中，进一步包括：电子元件，安装在该重分布层结构的该第一表面上。
其中，进一步包括：底部填充材料，设置在该半导体晶粒和该重分布层结构之间。
本发明实施例提供了一种封装上封装，包括：底部半导体封装，该底部半导体封装为如上所述的半导体封装，其中该底部半导体封装进一步包括：多个穿过该模塑料的穿模通孔；以及上部半导体封装，安装在该底部半导体封装上，并且该上部半导体封装通过该多个穿模通孔电性连接至该底部半导体封装。
本发明实施例的有益效果是：
本发明实施例的半导体封装的制造方法，采用后晶粒(die-last)工艺，即先形成重分布层结构，再将半导体晶粒安装于重分布层结构上，因此能够保证安装的晶粒都是已知合格的晶粒，从而提高产品的良品率。
附图说明
包含附图以提供对实施例的进一步理解，并且该附图纳入该说明书中并构成该说明书的一部分。附图示意了实施例的一部分，并且连同描述一起来解释本发明的原理。在附图中：
图1至5示出了根据本发明实施例的半导体封装的制造方法，其中图4示出了一种具有底部填充材料的半导体封装，其中该底部填充材料位于半导体晶粒与RDL结构之间，以及图5示出了一种PoP(封装上封装或者堆叠封装)；以及
图6至9示出了根据本发明另一实施例的TMV(Through Mold Via，穿模通孔)和PoP的制造方法。
具体实施方式
在本申请说明书及权利要求当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求并不以名称的差异作为区分元件的方式，而是以元件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语，故应解释成“包括(含)但不限定于”。另外，“耦接”一词在此为包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电气连接至该第二装置，或透过其它装置或连接手段间接地电气连接至该第二装置。
本发明的一个或多个实现将参考附图来进行描述，其中通篇中，类似的参考符号用来表示类似的元件，并且示出的结构并不必按比例绘制。术语“晶粒(die)”、“芯片(chip)”、“半导体芯片”以及“半导体晶粒”在整个说明书中可以互换使用。
本发明涉及一种具有RDL结构的扇出半导体封装，封装上封装(PoP)及其制造方法。
图1至5示出了根据本发明一个实施例的一种半导体封装的制造方法。
如图1所示，提供了载体基板100。根据一个实施例，该载体基板100可以包括：玻璃、硅、陶瓷或者金属，但是不限制于此。根据一个实施例，释放层(release layer)102形成于该载体基板100的顶面上。
接着，RDL结构120形成于该释放层125上。该RDL结构120可以包括：至少一介电层125，第一金属层121，第二金属层122，以及通孔123，其中该通孔123电性连接该第一金属层121和该第二金属层122。
根据一个实施例，例如，第一金属层121可以包括：导电元件垫121a，以及第二金属层122可以包括：凸块垫122a，金属迹线(trace)122b以及接垫(pad)122c。可以理解的是，在附图中所描绘的RDL结构120中的层和图案仅作为说明的目的。RDL结构120中的金属层的数量可以取决于设计要求，例如RDL结构120中的金属层可以为多层，例如包括：第一、第二以及第三金属层，其中第一与第二金属层之间通过第一介电层隔开，第二与第三金属层之间通过第二介电层隔开。
根据一个实施例，第一金属层121和第二金属层122可以包括：铝、铜、钨、钛、氮化钛，等等。介电层125可以包括：任何合适的绝缘材料，包括但不限于：PID(Photo ImageDielectric，光成像介电质)材料，预浸材料(prepreg)或者树脂材料，诸如ABF(AjinomotoBuild-up Film，曰本味之素公司所供应的一种环氧树脂绝缘膜)或类似物。
根据一个实施例，介电层125中的金属图案可以通过增层法(build-up process)和电镀工艺来形成，但是不限制于此。在另一实施例中，介电层125可以包括：无机材料，诸如氧化硅、氮化硅或类似物，以及介电层125中的金属图案可以由光刻工艺与蚀刻工艺来形成。
根据一个实施例，介电层125中形成的金属迹线或金属图案可以具有介于1～10μm(微米)的线宽，例如3μm、5μm或者7μm；并且，两相邻线之间的间隔介于1～10μm之间，例如3μm、5μm或者7μm，但是不限制于此。
根据一个实施例，可选地，在RDL结构120形成之后，焊料屏蔽130形成于介电层125和第二金属层122上。该焊料屏蔽130可以包括：多个开口131，分别露出第二金属层122的凸块垫122a以及接垫122c。可选地，OSP(organic solderability preservatives，有机保焊)膜(未示出)可以应用至凸块垫122a以及接垫122c的露出的表面上。
如图2所示，在形成RDL结构120之后，多个半导体晶粒200可以安装于RDL结构120上的芯片安装区域中。根据一个实施例，每个半导体晶粒200均为其主动面200a向下面向RDL结构120的倒装芯片。多个I/O垫201可以设置在每个半导体晶粒200的主动面200a上。诸如金属凸块或金属柱等连接元件202可以设置在每个I/O垫201上。连接元件202例如通过焊料203连接至对应的凸块垫122a。
可选地，电子元件210可以安装至该RDL结构120上，例如该电子元件120为解耦电容、电阻或电感等被动元件。例如，该电子元件210通过使用SMT(Surface MountTechnique，表面安装技术)来安装于接垫122c上。
如图3所示，在RDL结构120上安装了半导体晶粒200之后，施加一模塑料300。该模塑料300至少覆盖半导体晶粒200，电子元件210，以及RDL结构120的顶面，从而形成晶圆级封装10。根据一个实施例，可以对模塑料300施加固化工艺。该模塑料300可以包括：环氧树脂与二氧化硅填充物的混合物，但是不限制于此。
根据另一实施例，如图4所示，在形成模塑料300之前，底部填充材料(underfill)310可以应用在每个半导体晶粒200和RDL结构120之间。底部填充材料310可以为填充了二氧化硅的环氧树脂，但是不限制于此。底部填充材料310填充每个半导体晶粒200和RDL结构120之间的间隙(或间隔)。
接着，移除载体基板100和释放层102，从而露出RDL结构120的底面。通过使用加热、激光、UV/IR(紫外/红外)辐射或者机械剥离来执行载体基板100的解接合(de-bonding)，但是不限制于此。在移除了载体基板100之后，暴露第一金属层121的导电元件垫121a。
根据一个实施例，没有金属饰面(metal finish)形成于第一金属层121的导电元件垫121a上。该第一金属层121的厚度可以介于1～20μm之间，例如7μm或12μm。根据另一实施例，诸如Ni，Au及/或其他基本金属等金属饰面可以形成于第一金属层121的导电元件垫121a上。
接着，多个导电结构410分别设置在第一金属层121的导电元件垫121a上，以完成半导体封装10。接着，对该半导体封装10施加晶圆切割工艺并且将该半导体封装10单个化为独立的晶粒封装1。根据一个实施例，导电结构410可以为焊料球，焊料凸块，铜柱凸块，或者他们的任意组合，但是不限制于此。
图5为根据本发明实施例的PoP的横截面示意图。如图5所示，形成多个用于进一步连接的TMV320，其中该多个TMV320穿过模塑料300的整个厚度。根据一个实施例，可以通过将多个通孔钻入模塑料30中，并且使用诸如铜等金属来填充该多个通孔，从而形成TMV320。TMV320可以在晶圆切割工艺之前形成，但是不限制于此。
在示出的PoP中，晶粒封装1起底部封装的功能，上部封装2直接安装于该晶粒封装1上。例如，该上部封装可以为DRAM芯片封装，但是不限制于此。上部封装2可以包括：芯片(诸如DRAM芯片，未示出)，该芯片可以通过TMV320和RDL120电性连接至底部封装。上部封装2可以包括多个连接元件21(诸如导电结构或凸块)，用来连接上部封装2和TMV320。
图6至9示出了根据本发明另一实施例的TMV和PoP的制造方法，其中，类似的参考符号表示类似的元件、层或区域。
如图6所示，类似地，提供了载体基板100。该载体基板100可以包括：玻璃、硅、陶瓷或金属，但是不限制于此。释放层102可以形成于载体基板100的顶面上。接着，RDL结构120形成于该释放层102上。
该RDL结构120可以包括至少一介电层125，第一金属层121，第二金属层122以及通孔123，其中通孔123电性连接该第一金属层121和该第二金属层122。该第一金属层121可以包括：导电元件垫121a，以及该第二金属层122可以包括：凸块垫122a，金属迹线122b，接垫122c和接垫122d。
在RDL结构120形成之后，焊料屏蔽130可以形成于介电层125和第二金属层122上。焊料屏蔽130可以包括：多个开口131，分别露出第二金属层122的凸块垫122a、接垫122c及122d。
接着，多个金属柱320a形成于位于RDL结构120的外围区域处的接垫122d上，其中该外围区域可以为该RDL结构120中除了芯片安装区域之外的区域或者围绕芯片安装区域的区域。例如，为了形成金属柱320a，光阻层(未示出)形成于RDL结构120上。接着，执行光刻工艺以在光阻层中形成通孔开口。通孔开口对齐接垫122d。接着，通过CVD(Chemical VaporDeposition，化学气相沉积)、PVD(Physical Vapor Deposition，物理气相沉积)、ALD(Atomic Layer Deposition，原子层沉积)或电镀工艺来将诸如铜等金属沉积在通孔开口中。接着，移除光阻层。
如图7所示，在形成金属柱320a之后，将多个半导体晶粒200安装在RDL结构120上的芯片安装区域内。根据一个实施例，每个半导体晶粒200为以其主动面向下面向RDL结构120的倒装芯片。多个I/O垫201可以设置在每个半导体晶粒200的主动面200a上。诸如金属凸块或金属柱等连接元件202可以设置在每个I/O垫201上。连接元件202例如通过焊料203连接至对应的凸块垫122a。
可选地，电子元件210，诸如解耦电容、电阻或电感等被动元件，可以安装至RDL结构120上。例如，电子元件210可以通过使用SMT来安装在接垫122c上。
如图8所示，在RDL结构120上安装了半导体晶粒200之后，施加一模塑料300。该模塑料300至少覆盖半导体晶粒200，电子元件210，金属柱320a以及RDL结构120的顶面，从而形成晶圆级封装10。可选地，可以执行CMP(Chemical Mechanical Polishing，化学机械研磨)工艺以暴露金属柱320a的顶面，从而形成TMV320。
接着，移除载体基板100和释放层102，从而露出RDL结构120的底面。通过使用加热、激光、UV/IR辐射或者机械剥离来执行载体基板100的解接合(de-bonding)，但是不限制于此。在移除了载体基板100之后，暴露第一金属层121的导电元件垫121a。
接着，导电结构410可以分别设置在第一金属层121的导电元件垫121a上，以完成半导体封装10。接着，对该半导体封装10执行晶圆切割工艺并且将该半导体封装10单个化为独立的晶粒封装(或半导体封装)1。
如图9所示，上部封装2安装于晶粒封装1上。例如，上部封装2可以为DRMA芯片封装，但是不限制于此。上部封装2可以包括：芯片(诸如DRAM芯片，未示出)，该芯片可以通过TMV320和RDL结构120电性连接至下部封装。该上部封装2可以包括：多个连接元件，诸如导电结构或凸块，用来连接上部封装2与TMV320。
本发明实施例的半导体封装的制造方法，由于采用后晶粒(die-last)工艺，即先形成RDL结构，然后再将半导体晶粒安装于重分布层结构上，因此能够保证安装的晶粒都是已知合格的晶粒，从而提高产品的良品率。另外，本发明实施例形成的半导体封装，对于RDL结构中第一表面(晶粒所接合的表面)上的的导电迹线而言，其位于晶粒区(即俯视时半导体晶粒在RDL结构上的投影区域)的部分和位于晶粒区外的部分之间不会存在偏移，而传统的采用先晶粒(die-first)的方案，即先安装晶粒后形成RDL结构，则会存在一定程度的偏移。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (20)

1.一种半导体封装的制造方法，其特征在于，包括：
提供载体基板；
在该载体基板上形成重分布层结构，其中该重分布层结构包括：至少一凸块垫；
在该重分布层结构上安装半导体晶粒；
在该半导体晶粒以及该重分布层结构上形成模塑料；
移除该载体基板，以露出该重分布层结构的多个焊球垫；以及
于该多个焊球垫上形成多个导电结构。
2.如权利要求1所述的半导体封装的制造方法，其特征在于，该载体基板包括：玻璃、硅、陶瓷或金属。
3.如权利要求1所述的半导体封装的制造方法，其特征在于，该半导体晶粒为以其主动面面向该重分布层结构的倒装芯片，其中，多个I/O垫设置在该半导体晶粒的主动面上。
4.如权利要求1所述的半导体封装的制造方法，其特征在于，在每个I/O垫上设置连接元件，并且该连接元件连接至该凸块垫。
5.如权利要求1所述的半导体封装的制造方法，其特征在于，在该半导体晶粒和该重分布层结构上形成该模塑料之后，该方法进一步包括：在该模塑料中形成多个穿模通孔。
6.如权利要求5所述的半导体封装的制造方法，其特征在于，在该模塑料中形成多个穿模通孔的步骤包括：将多个通孔钻入该模塑料中；以及使用金属来填充该多个通孔。
7.如权利要求1所述的半导体封装的制造方法，其特征在于，在该重分布层结构上安装该半导体晶粒之前，该方法进一步包括：在该重分布层结构上形成多个金属柱；其中该模塑料还包封该多个金属柱，并且该多个金属柱的顶面从该模塑料中露出以作为穿模通孔。
8.一种封装上封装的制造方法，其特征在于，包括：
采用如权利要求1～6中任一项所述的制造半导体封装的方法来形成半导体封装；
将该半导体封装切割为晶粒封装，其中该晶粒封装作为该封装上封装的底部半导体封装；以及
在该底部半导体封装上安装上部半导体封装，其中该上部半导体封装通过多个穿过该模塑料的穿模通孔电性连接至该底部半导体封装。
9.一种封装上封装的制造方法，其特征在于，包括：
形成底部半导体封装；以及
在该底部半导体封装上安装上部半导体封装，并且该上部半导体封装电性连接至该底部半导体封装；
其中，形成该底部半导体封装的步骤包括：
形成重分布层结构，其中该重分布层结构具有相对的第一表面与第二表面，并且该重分布层结构包括：至少一位于该第一表面上的凸块垫；
以倒装芯片的方式将半导体晶粒安装于该重分布层结构上，其中该半导体晶粒的主动面上设置了多个I/O垫，并且在每个I/O垫上设置连接元件，其中该连接元件连接至对应的凸块垫；
使用模塑料来封装该半导体晶粒；
在该模塑料中形成多个穿模通孔；以及
在该重分布层结构的该第二表面上形成多个导电结构；
其中，该上部半导体封装通过该多个穿模通孔电性连接至该底部半导体封装。
10.如权利要求9所述的封装上封装的制造方法，其特征在于，该连接元件包括：金属凸块或者金属柱。
11.如权利要求9所述的封装上封装的制造方法，其特征在于，该连接元件通过焊料连接至该凸块垫。
12.如权利要求9所述的封装上封装的制造方法，其特征在于，进一步包括：电子元件，安装于该重分布层结构的该第一表面上。
13.如权利要求12所述的封装上封装的制造方法，其特征在于，该电子元件包括：电容、电阻或电感。
14.如权利要求9所述的封装上封装的制造方法，其特征在于，进一步包括：
在该半导体晶粒与该重分布层结构之间插入底部填充材料。
15.一种半导体封装，其特征在于，包括：
重分布层结构，具有相对的第一及第二表面，其中该重分布层结构包括：至少一凸块垫，位于该第一表面上；
半导体晶粒，安装于该重分布层结构的该第一表面上，其中该半导体晶粒为以其主动面面向该重分布层结构的倒装芯片，其中，多个I/O垫设置在该半导体晶粒的该主动面上，其中在每个I/O垫上设置连接元件，其中，该连接元件连接该凸块垫；
模塑料，包封该半导体晶粒并且覆盖该重分布层结构的该第一表面；以及
多个导电结构，安装在该重分布层结构的该第二表面上。
16.如权利要求15所述的半导体封装，其特征在于，该重分布层结构包括：至少一介电层，位于该第一表面上的第一金属层，位于该第二表面上的第二金属层以及至少一通孔，其中该通孔电性连接该第一金属层与该第二金属层。
17.如权利要求15所述的半导体封装，其特征在于，该连接元件包括：金属凸块或者金属柱；及/或，该连接元件通过焊料连接至该凸块垫。
18.如权利要求15所述的半导体封装，其特征在于，进一步包括：电子元件，安装在该重分布层结构的该第一表面上。
19.如权利要求15所述的半导体封装，其特征在于，进一步包括：底部填充材料，设置在该半导体晶粒和该重分布层结构之间。
20.一种封装上封装，其特征在于，包括：
底部半导体封装，该底部半导体封装为如权利要求15～19中任一项所述的半导体封装，其中该底部半导体封装进一步包括：多个穿过该模塑料的穿模通孔；以及
上部半导体封装，安装在该底部半导体封装上，并且该上部半导体封装通过该多个穿模通孔电性连接至该底部半导体封装。
CN201710800845.2A 2016-09-12 2017-09-07 半导体封装、封装上封装及其制造方法 Withdrawn CN107818956A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662393254P 2016-09-12 2016-09-12
US62/393,254 2016-09-12
US15/638,388 US10217716B2 (en) 2016-09-12 2017-06-30 Semiconductor package and method for fabricating the same
US15/638,388 2017-06-30

Publications (1)

Publication Number Publication Date
CN107818956A true CN107818956A (zh) 2018-03-20

Family

ID=59350669

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710800845.2A Withdrawn CN107818956A (zh) 2016-09-12 2017-09-07 半导体封装、封装上封装及其制造方法

Country Status (4)

Country Link
US (1) US10217716B2 (zh)
EP (1) EP3293759A1 (zh)
CN (1) CN107818956A (zh)
TW (1) TW201826409A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110349861A (zh) * 2019-06-27 2019-10-18 深圳第三代半导体研究院 一种新型PoP封装结构及其制作方法
CN111106013A (zh) * 2019-10-31 2020-05-05 广东芯华微电子技术有限公司 Tmv结构的制备方法、大板扇出型异构集成封装结构及其制备方法
CN112166502A (zh) * 2018-05-31 2021-01-01 华为技术有限公司 一种倒装芯片的封装结构及电子设备

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9515017B2 (en) * 2014-12-18 2016-12-06 Intel Corporation Ground via clustering for crosstalk mitigation
KR20170053416A (ko) * 2015-11-06 2017-05-16 주식회사 엘지화학 반도체 장치 및 반도체 장치의 제조 방법
US10211071B2 (en) * 2016-01-29 2019-02-19 Nxp B.V. IC packaging method and a packaged IC device
CN106601627A (zh) * 2016-12-21 2017-04-26 江苏长电科技股份有限公司 先封后蚀电镀铜柱导通三维封装结构的工艺方法
TWI666743B (zh) * 2017-09-29 2019-07-21 英屬開曼群島商鳳凰先驅股份有限公司 感測器封裝件及其製作方法
KR102536269B1 (ko) * 2018-09-14 2023-05-25 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP7207927B2 (ja) * 2018-09-28 2023-01-18 株式会社ディスコ 半導体パッケージの製造方法
TWI671873B (zh) * 2018-10-30 2019-09-11 力成科技股份有限公司 半導體封裝結構
US10903561B2 (en) * 2019-04-18 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
KR102494920B1 (ko) * 2019-05-21 2023-02-02 삼성전자주식회사 반도체 패키지
KR102551352B1 (ko) 2019-06-28 2023-07-04 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
KR20210011279A (ko) 2019-07-22 2021-02-01 삼성전자주식회사 반도체 패키지
US11862587B2 (en) 2019-07-25 2024-01-02 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
KR20210120532A (ko) 2020-03-27 2021-10-07 삼성전자주식회사 반도체 패키지
US20210366852A1 (en) * 2020-05-25 2021-11-25 Nanya Technology Corporation Semiconductor structure and method of forming the same
CN111883437B (zh) * 2020-07-03 2023-04-25 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
CN115050654B (zh) * 2022-08-17 2022-11-08 甬矽电子(宁波)股份有限公司 扇入型封装结构的制备方法和扇入型封装结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090008762A1 (en) * 2007-07-02 2009-01-08 Nepes Corporation Ultra slim semiconductor package and method of fabricating the same
CN103199055A (zh) * 2012-01-06 2013-07-10 台湾积体电路制造股份有限公司 封装件及其形成方法
CN104733379A (zh) * 2013-12-23 2015-06-24 新科金朋有限公司 在半导体管芯上形成细节距的rdl的半导体器件和方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9478474B2 (en) 2012-12-28 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for forming package-on-packages
US10269619B2 (en) 2013-03-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090008762A1 (en) * 2007-07-02 2009-01-08 Nepes Corporation Ultra slim semiconductor package and method of fabricating the same
CN103199055A (zh) * 2012-01-06 2013-07-10 台湾积体电路制造股份有限公司 封装件及其形成方法
CN104733379A (zh) * 2013-12-23 2015-06-24 新科金朋有限公司 在半导体管芯上形成细节距的rdl的半导体器件和方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112166502A (zh) * 2018-05-31 2021-01-01 华为技术有限公司 一种倒装芯片的封装结构及电子设备
CN112166502B (zh) * 2018-05-31 2023-01-13 华为技术有限公司 一种倒装芯片的封装结构及电子设备
CN110349861A (zh) * 2019-06-27 2019-10-18 深圳第三代半导体研究院 一种新型PoP封装结构及其制作方法
CN111106013A (zh) * 2019-10-31 2020-05-05 广东芯华微电子技术有限公司 Tmv结构的制备方法、大板扇出型异构集成封装结构及其制备方法
CN111106013B (zh) * 2019-10-31 2022-03-15 广东芯华微电子技术有限公司 Tmv结构的制备方法、大板扇出型异构集成封装结构及其制备方法

Also Published As

Publication number Publication date
US20180076166A1 (en) 2018-03-15
EP3293759A1 (en) 2018-03-14
US10217716B2 (en) 2019-02-26
TW201826409A (zh) 2018-07-16

Similar Documents

Publication Publication Date Title
CN107818956A (zh) 半导体封装、封装上封装及其制造方法
US11417643B2 (en) Package-on-package with redistribution structure
US9583472B2 (en) Fan out system in package and method for forming the same
US11784166B2 (en) Dual sided fan-out package having low warpage across all temperatures
US9799622B2 (en) High density film for IC package
US8729714B1 (en) Flip-chip wafer level package and methods thereof
TWI575624B (zh) 半導體封裝及其製作方法
CN108766940B (zh) 用于3d封装的应力补偿层
US10083919B2 (en) Packaging for high speed chip to chip communication
CN107946253A (zh) 采用模制中介层的晶圆级封装
US9922917B2 (en) Semiconductor package including substrates spaced by at least one electrical connecting element
JP5714112B2 (ja) ＰｏＰ−ｍＷＬＰとしての多機能センサ
CN102810520A (zh) 热改善的集成电路封装件
CN107768337A (zh) 预先凸起的重分布层结构及半导体封装
US20150014864A1 (en) Semiconductor package and method of fabricating the same
TWI752238B (zh) 疊層封裝結構
US20150332986A1 (en) Semiconductor device including semiconductor chip covered with sealing resin
TWI727469B (zh) 封裝體及其形成方法
US11956897B2 (en) Semiconductor package device and method of manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication

Application publication date: 20180320

WW01 Invention patent application withdrawn after publication