JP7207927B2 - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
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- JP7207927B2 JP7207927B2 JP2018185537A JP2018185537A JP7207927B2 JP 7207927 B2 JP7207927 B2 JP 7207927B2 JP 2018185537 A JP2018185537 A JP 2018185537A JP 2018185537 A JP2018185537 A JP 2018185537A JP 7207927 B2 JP7207927 B2 JP 7207927B2
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- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Description
本発明の実施形態1に係る半導体パッケージの製造方法を図面に基づいて説明する。図1は、実施形態1に係る半導体パッケージの製造方法により製造される半導体パッケージを模式的に示す断面図である。図2は、実施形態1に係る半導体パッケージの製造方法により半導体パッケージに分割される半導体パッケージ基板の一部を示す平面図である。図3は、図2中のIII-III線に沿う断面図である。図4は、実施形態1に係る半導体パッケージの製造方法の流れを示すフローチャートである。
図5は、図4に示された半導体パッケージの製造方法の溝形成工程においてダイシングテープで半導体パッケージ基板を支持した状態を模式的に示す断面図である。図6は、図4に示された半導体パッケージの製造方法の溝形成工程を模式的に示す断面図である。図7は、図4に示された半導体パッケージの製造方法の溝形成工程後の半導体パッケージ基板を模式的に示す断面図である。
図8は、図4に示された半導体パッケージの製造方法の溝形成工程においてスパッタテープで半導体パッケージ基板を支持した状態を模式的に示す断面図である。図9は、図4に示された半導体パッケージの製造方法のシールド層形成工程後の半導体パッケージ基板を模式的に示す断面図である。
図10は、図4に示された半導体パッケージの製造方法の分割工程を模式的に示す断面図である。図11は、図4に示された半導体パッケージの製造方法の分割工程後の半導体パッケージ基板を模式的に示す断面図である。
本発明の実施形態2に係る半導体パッケージの製造方法を図面に基づいて説明する。図12は、実施形態2に係る半導体パッケージの製造方法の溝形成工程においてダイシングテープで半導体パッケージ基板を支持した状態を模式的に示す断面図である。図13は、実施形態2に係る半導体パッケージの製造方法の分割工程を模式的に示す断面図である。図14は、実施形態2に係る半導体パッケージの製造方法の分割工程後の半導体パッケージ基板を模式的に示す断面図である。なお、図12、図13及び図14は、実施形態1と同一部分に同一符号を付して説明を省略する。
2 配線基板
3 半導体チップ
4 半田ボール
6 封止剤
7 シールド層
9 加工溝
10 半導体パッケージ基板
11 分割予定ライン
21 上面
22 下面
61 上面
91 第1の幅
92 底面
93 第2の幅
94 側面
101 第1の切削ブレード(第1の切削手段)
111 第2の切削ブレード(第2の切削手段)
ST1 溝形成工程
ST2 シールド層形成工程
ST3 分割工程
Claims (2)
- 複数の分割予定ラインで区画された配線基板の上面に複数の半導体チップがマウントされ、該配線基板の下面に複数の半田ボールがマウントされ、該下面に下面側半導体チップがマウントされ、該配線基板が絶縁性の絶縁板と該絶縁板の内部に設けられた導電性のグランドラインとを備え、両面が封止剤により封止された半導体パッケージ基板を該分割予定ラインに沿って分割し半導体パッケージを製造する半導体パッケージの製造方法であって、
該上面側から少なくとも該配線基板に備わる該グランドラインを加工溝内に露出させる深さ以上で該半導体パッケージ基板を完全分割しない深さまで該分割予定ラインに沿って第1の切削手段で切り込み、該封止剤の少なくとも上面に第1の幅である加工溝を形成する溝形成工程と、
該封止剤側上方から導電性材料で、該加工溝の側面及び該加工溝の底面及び該封止剤上面に該グランドラインに接続したシールド層を形成するシールド層形成工程と、
該シールド層形成工程を実施した後に、第2の切削手段によって該加工溝に沿って該側面に形成されたシールド層を除去しない幅で切り込み、該半導体パッケージ基板を分割する分割工程と、
を備える事を特徴とする、半導体パッケージの製造方法。 - 該溝形成工程において、
該加工溝は、上面の第1の幅が底面の第2の幅より大きく該加工溝の側面には傾斜が形成されていることを特徴とする、請求項1に記載の半導体パッケージの製造方法。
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