TWI575624B - 半導體封裝及其製作方法 - Google Patents

半導體封裝及其製作方法 Download PDF

Info

Publication number
TWI575624B
TWI575624B TW105111959A TW105111959A TWI575624B TW I575624 B TWI575624 B TW I575624B TW 105111959 A TW105111959 A TW 105111959A TW 105111959 A TW105111959 A TW 105111959A TW I575624 B TWI575624 B TW I575624B
Authority
TW
Taiwan
Prior art keywords
conductive
semiconductor
semiconductor package
carrier
semiconductor die
Prior art date
Application number
TW105111959A
Other languages
English (en)
Other versions
TW201640599A (zh
Inventor
蔡憲聰
Original Assignee
聯發科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW201640599A publication Critical patent/TW201640599A/zh
Application granted granted Critical
Publication of TWI575624B publication Critical patent/TWI575624B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H01L2224/25174—Stacked arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

半導體封裝及其製作方法
本發明係有關於一種半導體結構，特別是有關於一種積體電路及半導體封裝的內連結構。
已知，積體電路晶粒(IC die)是製作在半導體晶圓(例如矽晶圓)上的微細電路元件。當晶粒從晶圓切割下來後，可以黏合至一基板上，以進行內連重分佈。後續透過打線，可以將晶粒上的接合墊電連接至基板上的引腳(lead)。最後，將晶粒與打線以成型模料模封包覆起來，即構成一封裝。
通常，上述封裝內所封裝的引腳可在載體中的導體網絡內重分佈，並在封裝外構成以陣列形式的連接端點。目前，業界已在單一封裝中堆疊兩個或更多個的晶粒。這樣的裝置又可稱做多晶片堆疊封裝(stacked multichip package)。
第1圖例示習知的多晶片堆疊封裝的剖面示意圖。如第1圖所示，一第一晶粒11被安置在一基板10上。然後，一第二晶粒12可以黏合方式固定在第一晶粒11的上表面，如此構成一晶粒堆疊組態。當從上往下看時，第二晶粒12係部 分重疊於第一晶粒11。接著，利用傳統的打線機(wire bonder)形成打線16及18,將第一晶粒11與第二晶粒12分別電連結至基板10上相對應的接合指(bond finger)。再將模封材20包封在基材10上，以構成一模封蓋。
然而，上述的封裝結構仍有部分缺點需要進一步克服，例如，打線18不容易形成在靠近第二晶粒12的懸出的側邊(overhanging side edge)12a上的接合墊上，這是因為打線機產生的應力可能造成第一晶粒11與第二晶粒12之間的剝離情形，導致製程良率下降。
本發明一主要目的在提供一種改良的半導體封裝及其製作方法，以解決上述先前技藝的不足與缺點。
根據本發明一實施例，提供一種半導體封裝，包含一第一半導體晶粒，具有一主動面及一相對該主動面的下表面；複數個輸入/輸出(I/O)墊，分佈在該第一半導體晶粒的主動面上；一模封材，覆蓋該第一半導體晶粒的主動面，其中該模封材包含一下表面，其與該第一半導體晶粒的下表面齊平；以及複數個列印的內連結構，嵌入於該模封材中，用以電連接該複數個I/O墊，其中各該列印的內連結構包含一導電接線以及一導電接墊，其中該導電接線與該導電接墊係一體形成的。
根據本發明實施例，該導電接墊係排列在該第一半導體晶粒周圍的該模封材的下表面，其中該導電接墊的一顯露出的下表面係與該模封材的下表面齊平。
根據本發明實施例，該導電接線與該導電接墊係以3D列印一體形成。其中該列印的內連結構包含銀、金、銅、奈米碳管、石墨烯或奈米金屬顆粒。
根據本發明另一實施例，所述半導體封裝還包含一第二半導體晶粒，以黏合的方式固定在該第一半導體晶粒的上表面。當從上往下看時，該第二半導體晶粒係部分重疊於該第一半導體晶粒。
根據本發明一實施例，提供了一種半導體封裝，包含：一半導體晶粒，具有一主動面及一相對該主動面的下表面；複數個輸入/輸出(I/O)墊，分佈在該半導體晶粒的主動面上；一模封材，覆蓋該半導體晶粒的主動面，其中該模封材包含一下表面，其與該半導體晶粒的下表面齊平；以及複數個列印的導電接線，嵌入於該模封材中，用以電連接該複數個I/O墊，其中各該列印的導電接線包含一直角彎折部。
根據本發明一實施例，提供了一種半導體封裝的製作方法，包含： 提供一載板；將複數個半導體晶粒設置在該載板上，其中各該半導體晶粒具有一主動面，以及一下表面，相對於該主動面，其中在該主動面上分佈有複數個輸入/輸出(I/O)墊；於該載板上與該半導體晶粒的主動面上列印出內連結構，該內連結構包含導電接墊及導電接線；將該載板的上表面、該半導體晶粒的上表面、該導電接線與該導電接墊以一模封材包覆住；以及移除該載板。
根據本發明一實施例，提供了一種半導體封裝的製作方法，包含： 提供一載板；將複數個半導體晶粒設置在該載板上；於該載板上與該複數個半導體晶粒的上表面列印出一臨時內連結構；將該載板的上表面、該複數個半導體晶粒的上表面，與該臨時內連結構以一模封材包覆住；移除該載板；去除該臨時內連結構，從而於該模封材內形成一凹穴；以及將該凹穴以一導電材料填滿，俾形成一內連結構。
以上實施例的半導體封裝，採用列印的方式形成內連結構(或導電接線)，從而提高半導體封裝的良率。
1、2、3、4‧‧‧半導體封裝
100‧‧‧下晶粒封裝
101‧‧‧基板
101a‧‧‧上表面
101b‧‧‧下表面
102‧‧‧接合指(金手指)
103‧‧‧錫球
110‧‧‧半導體晶粒(下半導體晶粒)
110a‧‧‧主動面(上表面)
110b‧‧‧下表面
116、118‧‧‧導電接線
116a、118a‧‧‧導電接線
118b‧‧‧延伸部
121‧‧‧輸入/輸出(I/O)墊
200‧‧‧模封材
200a‧‧‧上表面
200b‧‧‧下表面
210‧‧‧被動元件
210a、210b‧‧‧端子
216、218‧‧‧導電接墊
230‧‧‧連接件
260‧‧‧開孔
300‧‧‧上晶粒封裝
310‧‧‧積體電路晶粒
320‧‧‧導電元件
410‧‧‧上半導體晶粒
410a‧‧‧主動面
410b‧‧‧下表面
412‧‧‧懸突的側邊
421‧‧‧I/O墊
500‧‧‧載板
510‧‧‧內連結構
510’‧‧‧臨時內連結構
530‧‧‧凹穴
600‧‧‧3D列印結構
610‧‧‧導電接線
610a‧‧‧次接線
620‧‧‧電源管理單元熱管
630‧‧‧電感
640‧‧‧電源柱
所附圖式係提供用以方便對本發明更進一步的了解，其構成本說明書的一部分。所附圖式與說明書內容一同闡述之本發明實施例，有助於解釋本發明的原理原則。在圖式中：第1圖為習知多晶片堆疊封裝的剖面示意圖；第2圖為依據本發明實施例所繪示的半導體封裝的剖面示意圖；第3圖為依據本發明另一實施例所繪示的封裝上封裝的剖面示意圖；第4圖為依據本發明又另一實施例所繪示的多晶粒封裝的剖面示意圖；第5圖至第9圖為依據本發明實施例所繪示的製作第2圖中半導體封裝的例示 性方法示意圖；第10圖至第12圖為依據本發明另一實施例所繪示的製作第2圖中半導體封裝的例示性方法示意圖；以及第13圖為依據本發明又另一實施例所繪示的半導體封裝的側視示意圖。
在下文中，將參照附圖說明本發明實施例細節，該些附圖中之內容構成說明書的一部份，並且以可實行該實施例之特例描述方式來繪示。
下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
請參閱第2圖，其為依據本發明實施例所繪示的半導體封裝的剖面示意圖。如第2圖所示，半導體封裝1包含一半導體晶粒110，該半導體晶粒110具有一上表面或主動面110a，以及一下表面110b，該下表面110b相對於主動面110a。在主動面110a上分佈有複數個接合墊或輸入/輸出(I/O)墊121。根據本發明實施例，主動面110a、I/O墊121，以及主動面110a與下表面110b之間的四個側面係被一模封材200，例如成型模料(molding compound)，所覆蓋住。
在某些實施例中，模封材200可以是環氧樹脂、樹脂，可模塑的聚合 物，或類似物所構成。模封材200可以基本上以液態施加，並且然後可以通過化學反應固化，例如在環氧樹脂或樹脂中。在其它一些實施例中，成型模料可以是紫外線(UV)或熱固化的聚合物，以凝膠態或可延展固體形態被佈置圍繞在半導體晶粒110周圍，然後再通過UV或熱固化方法來固化。模封材200可利用模具(圖未示)進行固化。
根據本發明實施例，下表面110b係從模封材200的下表面200b顯露出來。模封材200具有一上表面200a，相對於其下表面200b。根據本發明實施例，顯露出來的半導體晶粒110的下表面110b係與模封材200的下表面200b齊平。根據本發明實施例，在半導體晶粒110的主動面110a上不需要形成重佈線層(re-distribution layer，RDL)。
為簡化說明，圖中並未繪示出半導體晶粒110的細部結構。需理解的是，半導體晶粒110可以包含一半導體基板，例如矽基板。在半導體基板的主動面上，可以形成有複數個電路元件，例如，電晶體等。在半導體基板上還可以沉積有複數層間介電層(inter-layer dielectric，ILD)。層間介電層可以是由有機材料或者非有機材料所構成，其中有機材料包含高分子材料，非有機材料包括氮化矽、氧化矽、石墨烯等。在層間介電層中可以形成有複數金屬內連線層。前述半導體晶粒110的I/O墊121可以是形成在最上層金屬層中，並以一鈍化層覆蓋，但不限於此。
根據本發明實施例，在模封材200的下表面200b上分佈有複數個導電接墊216及218。所述導電接墊216及218排列在半導體晶粒110的周圍，並分別經由導電接線116及118電連接至主動面110a上的I/O墊121。導電接墊216及218的一 顯露出的下表面係與模封材200的下表面200b齊平。為方便進一步連結，在導電接墊216及218上可以形成有複數個連接件230，例如，導電凸塊(如C4凸塊或銅柱)或者導電錫球(如BGA(Ball Grid Array，球柵陣列)錫球)。
本發明的主要技術特徵之一在於導電接線116及118與導電接墊216及218係一體形成。根據本發明實施例，例如，導電接線116及118與導電接墊216及218可以是利用3D列印機或具有3D列印功能的打線機形成。導電接線116及118與導電接墊216及218係被模封材200包覆住。根據本發明實施例，不需要額外的封裝基板(packaging substrate)或中介層(interposer)。另外，由於導電接線116及118是利用3D列印機或具有3D列印功能的打線機形成，所以導電接線116及118可以具有一直角彎折部，如此可以避免鄰近接線的短路問題。
根據本發明實施例，半導體封裝1可以另包含一被動元件(passive device)210，例如一分立(discrete)電容元件、一電阻元件、一電感元件等。被動元件210可以設置在接近模封材200的下表面200b的位置。根據本發明實施例，被動元件210可以具有兩個端子210a及210b，分別電連接至導電接線116a及118a。
根據本發明實施例，導電接線116a及導電接線118a係分別與導電接線116及118一體形成。因此，端子210a係經由一體形成的導電接線116及116a電連接至導電接墊216及半導體晶粒110，而端子210b係經由一體形成的導電接線118及118a電連接至導電接墊218及半導體晶粒110。
根據本發明實施例，導電接線116或118可以有一體的延伸部，具有不同的圖案、尺寸或結構，沿著導電接線116或118的走線長度方向形成。例如， 第2圖中繪示出導電接線118可以具有一增寬的延伸部118b，其設置在接近模封材200的上表面200a的位置。上述增寬的延伸部118b可以包含接墊、盤體、網格等形狀，但不限於此。
請參閱第3圖，其為依據本發明另一實施例所繪示的半導體封裝的剖面示意圖，其中相同的區域、層或元件沿用相同的符號來表示。如第3圖所示，半導體封裝2可以是一封裝上封裝(package-on-package，PoP)。半導體封裝2包含一下晶粒封裝100，其結構特徵類似第2圖中所描述。下晶粒封裝100與第2圖中的半導體封裝1的差異在於，下晶粒封裝100的模封材200的上表面200a中另形成有開孔260，例如，雷射鑽孔。
各個開孔260可以顯露出部分的延伸部118b，在此實施例中，延伸部118b係為一體成型的接合墊。在開孔260內及顯露出的延伸部118b上，形成有導電元件320，該導電元件320包括但不限於：凸塊下金屬(under bump metal)及凸塊。在導電元件320上則安裝有一上晶粒封裝300，其包含一已模封的積體電路晶粒310。
請參閱第4圖，其為依據本發明又另一實施例所繪示的半導體封裝的剖面示意圖，其中相同的區域、層或元件沿用相同的符號來表示。如第4圖所示，半導體封裝3可以是一多晶粒封裝。半導體封裝3包含一下半導體晶粒110以及一上半導體晶粒410，其中上半導體晶粒410直接堆疊在下半導體晶粒110上。上半導體晶粒410可以利用黏合的方式固定在下半導體晶粒110的上表面。在下半導體晶粒110的主動面110a上分佈有複數個接墊或I/O墊121，在上半導體晶粒410的主動面410a上分佈有複數個接墊或I/O墊421。
根據本發明實施例，當從上往下看時，上半導體晶粒410係部分重疊於下半導體晶粒110。因此，上半導體晶粒410具有一懸出的側邊412。根據本發明實施例，所述懸出的側邊412與超過下半導體晶粒110的邊緣的下表面410b係被模封材200所包覆。
同樣的，在模封材200的下表面200b分佈有複數個導電接墊216及218。所述導電接墊216及218以陣列方式排列在半導體晶粒110的周圍，並分別經由導電接線116及118電連接至主動面110a上的I/O墊121及主動面410a上的I/O墊421。
為方便進一步連結，在導電接墊216及218上可以形成複數個連接件230，例如，導電凸塊(如C4凸塊或銅柱)或者導電錫球(如BGA錫球)。根據本發明實施例，例如，至少一I/O墊421係經由導電接線118及分支的導電接線118a與至少一I/O墊121電連接，其中分支的導電接線118a與導電接線118係一體形成的。
第5圖至第9圖為依據本發明實施例所繪示的製作第2圖中半導體封裝1的例示性方法示意圖。首先，如第5圖所示，提供一載體500。載體500可以包含玻璃、矽、金屬或任何合適材料的載體。接著將複數個半導體晶粒110設置在載體500上。各個半導體晶粒110具有一上表面或主動面110a，以及一下表面110b，相對於主動面110a。在主動面110a上分佈有複數個接合墊或I/O墊121。
半導體晶粒110可以利用黏合的方式固定在載板500的上表面。此 外，可選擇在載板500上設置一被動元件210，例如一分立電容元件、一電阻元件、一電感元件等。
如第6圖所示，接著在載板500上以及半導體晶粒110的主動面110a上形成內連結構510，該內連結構510包括但不限於：導電接墊216及218以及導電接線116及118。導電接線116及118分別與導電接墊216及218係一體形成的。被動元件210可以具有兩個端子210a及210b，分別電連接至導電接線116a及118a。
例如，導電接線116及118與導電接墊216及218可以是利用3D列印機或具有3D列印功能的打線機形成。例如，內連結構510可以包含銀、金、銅、奈米碳管、石墨烯或奈米金屬顆粒，但不限於此。在形成內連結構510之後，可選擇進行一固化製程或乾燥製程，以固化內連結構510及/或去除內連結構510中的溶劑。
根據本發明實施例，例如，導電接線118或者116可以有一體的延伸部，具有不同的圖案、尺寸或結構，沿著導電接線118或者116的走線長度方向形成。例如，導電接線118可以具有一增寬的延伸部118b。增寬的延伸部118b可以包含接墊、盤體、網格等形狀，但不限於此。需理解的是，在此階段，還可以另外在載體500上印刷出其他結構，例如一熱管(heat pipe)(圖未示)。
如第7圖所示，接著，將載體500的上表面、半導體晶粒110的上表面110a、導電接線116及118與導電接墊216及218以模封材200包覆住。例如，模封材200可以包含一成型模料，包含但不限於，環氧樹脂或樹脂。
如第8圖所示，接著將載體500去除，以顯露出模封材200的下表面200b、半導體晶粒110的下表面110b，以及導電接墊216及218。為方便進一步連結，在導電接墊216及218上可以形成有複數個連接件230，例如，導電凸塊(如C4凸塊或銅柱)或者導電錫球(如BGA錫球)。儘管圖中未繪示，應理解在模封材200的下表面200b與半導體晶粒110的下表面110b可以另形成有一鈍化層。
如第9圖所示，在形成連接件230之後，隨後進行一晶圓切割製程，以將個別的半導體封裝1彼此分離開來。在上述晶圓切割製程過程中，可以使用一切割膠帶(圖未示)，以提供臨時的支撐。
第10圖至第12圖為依據本發明另一實施例所繪示的製作半導體封裝1的例示性方法示意圖，其中相同的區域、層或元件能沿用相同的符號來表示。
如第10圖所示，在載板500上安裝好半導體晶粒110及被動元件210之後，接著以3D列印形成一臨時內連結構510’。根據本發明實施例，上述臨時內連結構510’可以是由一非導電材料或一可灰化(ashable)材料所構成。為簡化說明，在載板500上僅顯示出一個半導體晶粒110。
接著，以模封材200包覆載板500的上表面、半導體晶粒110的上表面110a，及上述臨時內連結構510’。例如，模封材200可以包含一環氧樹脂成型模料。
如第11圖所示，接著將載板500去除，以顯露出模封材200的下表面200b、半導體晶粒110的下表面110b，及部分的臨時內連結構510’。接著，將臨 時內連結構510’完全去除，如此在模封材200內形成凹穴530。
如第12圖所示，接著以導電材料將凹穴530填滿，形成內連結構510，該內連結構510包括但不限於，導電接墊216及218與導電接線116及118。導電接線116及118分別與導電接墊216及218係一體形成的。被動元件210可以具有兩個端子210a及210b，分別電連接至導電接線116a及118a。
例如，內連結構510可以包含銀、金、銅、奈米碳管、石墨烯或奈米金屬顆粒，但不限於此。在形成內連結構510之後，可選擇進行一固化製程、回焊製程或乾燥製程。
第13圖為依據本發明又另一實施例所繪示的半導體封裝的側視示意圖，其中相同的區域、層或元件沿用相同的符號來表示。如第13圖所示，半導體封裝4可以是一多晶粒封裝。半導體封裝4可以包含一基板101，具有一上表面101a及一下表面101b，其中上表面101a與下表面101b是相反的兩個面。基板101可以是一封裝基板或一印刷電路板，但不限於此。沿著基板101的上表面101a的周緣，設有複數個接合指(又稱”金手指”)102。在基板101的下表面101b上，設有複數個錫球103。
半導體封裝4包含一下半導體晶粒110以及一上半導體晶粒410，其中上半導體晶粒410直接堆疊在下半導體晶粒110上。上半導體晶粒410可以利用黏合的方式固定在下半導體晶粒110的上表面110a。在下半導體晶粒110的主動面110a上分佈有複數個接合墊或I/O墊121，在上半導體晶粒410的主動面410a上分佈有複數個接合墊或I/O墊421。根據本發明實施例，當從上往下看時，上半導體晶 粒410係部分重疊於下半導體晶粒110。因此，上半導體晶粒410具有一懸突的側邊412。根據本發明實施例，所述懸突的側邊412與上半導體晶粒410超出下半導體晶粒110的邊緣的下表面係被模封材(圖未示)所包覆。
根據本發明實施例，在上半導體晶粒410的主動面410a上與下半導體晶粒110的主動面110a上，形成有3D列印結構600，該3D列印結構包括但不限於，導電接線610、電源管理單元(power management unit，PMU)熱管620、電感630及電源柱(power bar)640等。根據本發明實施例，所述導電接線610可以內連I/O墊421、I/O墊121及/或接合指102。例如，其中一導電接線610可以透過次接線610a電連接至複數個接合指102，其中次接線610a係與此導電接線610一體形成。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧半導體封裝
110‧‧‧半導體晶粒
110a‧‧‧主動面(上表面)
110b‧‧‧下表面
116、118‧‧‧導電接線
116a、118a‧‧‧導電接線
118b‧‧‧延伸部
121‧‧‧輸入/輸出(I/O)墊
200‧‧‧模封材
200a‧‧‧上表面
200b‧‧‧下表面
210‧‧‧被動元件
210a、210b‧‧‧端子
216、218‧‧‧導電接墊
230‧‧‧連接件

Claims (25)

  1. 一種半導體封裝，包含：一第一半導體晶粒，具有一主動面及一相對該主動面的下表面；複數個輸入/輸出墊，分佈在該第一半導體晶粒的主動面上；一模封材，覆蓋該第一半導體晶粒的主動面，其中該模封材包含一下表面，其與該第一半導體晶粒的下表面齊平；以及複數個列印的內連結構，嵌入於該模封材中，用以電連接該複數個I/O墊，其中各該列印的內連結構包含一導電接線以及一導電接墊，其中該導電接線與該導電接墊係一體形成的。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該導電接墊係設置在該第一半導體晶粒周圍的該模封材的下表面，其中該導電接墊的一顯露出的下表面係與該模封材的下表面齊平。
  3. 如申請專利範圍第1項所述的半導體封裝，其中該導電接線與該導電接墊係以3D列印一體形成。
  4. 如申請專利範圍第1項所述的半導體封裝，其中該列印的內連結構包含銀、金、銅、奈米碳管、石墨烯或奈米金屬顆粒。
  5. 如申請專利範圍第1項所述的半導體封裝，其中該模封材包含環氧樹脂、樹脂或可模塑的聚合物。
  6. 如申請專利範圍第1項所述的半導體封裝，其中該第一半導體晶粒的 下表面未被該模封材所覆蓋。
  7. 如申請專利範圍第1項所述的半導體封裝，其中該導電接線包含一增寬的延伸部，設置在接近該模封材的一上表面的位置。
  8. 如申請專利範圍第7項所述的半導體封裝，其中該增寬的延伸部係為一接墊。
  9. 如申請專利範圍第8項所述的半導體封裝，其中於該模封材的上表面中另設有一開孔，顯露出該接墊。
  10. 如申請專利範圍第9項所述的半導體封裝，其中在該開孔內及該接墊上，設有一導電元件。
  11. 如申請專利範圍第10項所述的半導體封裝，其中在該模封材的上表面安裝有一晶粒封裝，電連接於該導電元件。
  12. 如申請專利範圍第1項所述的半導體封裝，其中另包含一被動元件，嵌入於該模封料中，並電連接該列印的內連結構。
  13. 如申請專利範圍第1項所述的半導體封裝，其中另包含一第二半導體晶粒，以黏合的方式固定在該第一半導體晶粒的上表面。
  14. 如申請專利範圍第13項所述的半導體封裝，其中當從上往下看時， 該第二半導體晶粒係部分重疊於該第一半導體晶粒。
  15. 一種半導體封裝，包含：一半導體晶粒，具有一主動面及一相對該主動面的下表面；複數個輸入/輸出墊，分佈在該半導體晶粒的主動面上；一模封材，覆蓋該半導體晶粒的主動面，其中該模封材包含一下表面，其與該半導體晶粒的下表面齊平；以及複數個列印的內連結構，嵌入於該模封材中，用以電連接該複數個I/O墊，其中各該列印的內連結構包含一導電接線以及一導電接墊，其中該導電接線與該導電接墊係一體形成的；其中該導電接線包含一直角彎折部。
  16. 如申請專利範圍第15項所述的半導體封裝，其中另包含複數個導電接墊，設置在該半導體晶粒周圍的該模封材的下表面，其中該導電接墊的一顯露出的下表面係與該模封材的下表面齊平。
  17. 一種半導體封裝的製作方法，包含：提供一載體；將複數個半導體晶粒設置在該載體上，其中各該半導體晶粒具有一主動面，以及相對於該主動面的一下表面，其中在該主動面上分佈有複數個輸入/輸出墊；於該載體上與該半導體晶粒的主動面上列印出內連結構，該內連結構包含導電接墊及導電接線，其中該導電接線與該導電接墊係一體形成的；將該載體的上表面、該半導體晶粒的上表面、該導電接線與該導電接墊以一模封材包覆住；以及 移除該載體。
  18. 如申請專利範圍第17項所述的半導體封裝的製作方法，其中載體包含玻璃載板、矽載板或金屬載板。
  19. 如申請專利範圍第17項所述的半導體封裝的製作方法，其中該內連結構包含銀、金、銅、奈米碳管、石墨烯或奈米金屬顆粒。
  20. 如申請專利範圍第17項所述的半導體封裝的製作方法，其中該導電接線與該導電接墊是利用一3D列印機或一具有3D列印功能的打線機形成。
  21. 如申請專利範圍第17項所述的半導體封裝的製作方法，其中在移除該載體之後，在該導電接墊上形成連接件，並在形成該連接件之後，接著進行一切割製程，將個別的半導體封裝彼此分離開來。
  22. 一種半導體封裝的製作方法，包含：提供一載體；將複數個半導體晶粒設置在該載體上；於該載板上與該複數個半導體晶粒的上表面列印出一臨時內連結構；將該載板的上表面、該複數個半導體晶粒的上表面，與該臨時內連結構以一模封材包覆住；移除該載體；去除該臨時內連結構，從而於該模封材內形成一凹穴；以及將該凹穴以一導電材料填滿，俾形成一內連結構。
  23. 如申請專利範圍第22項所述的半導體封裝的製作方法，其中該內連結構包含一導電接墊與一導電接線，其中該導電接線與該導電接墊係一體形成的。
  24. 如申請專利範圍第22項所述的半導體封裝的製作方法，其中該臨時內連結構是由一非導電材料或一可灰化材料所構成。
  25. 如申請專利範圍第22項所述的半導體封裝的製作方法，其中該內連結構包含銀、金、銅、奈米碳管、石墨烯或奈米金屬顆粒。
TW105111959A 2015-05-14 2016-04-18 半導體封裝及其製作方法 TWI575624B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562161591P 2015-05-14 2015-05-14
US201562190401P 2015-07-09 2015-07-09
US15/063,433 US9842831B2 (en) 2015-05-14 2016-03-07 Semiconductor package and fabrication method thereof

Publications (2)

Publication Number Publication Date
TW201640599A TW201640599A (zh) 2016-11-16
TWI575624B true TWI575624B (zh) 2017-03-21

Family

ID=55589710

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105111959A TWI575624B (zh) 2015-05-14 2016-04-18 半導體封裝及其製作方法

Country Status (4)

Country Link
US (2) US9842831B2 (zh)
EP (1) EP3093877B1 (zh)
CN (1) CN106158818B (zh)
TW (1) TWI575624B (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106575077A (zh) 2014-08-07 2017-04-19 奥宝科技有限公司 Lift印刷系统
WO2016063270A1 (en) 2014-10-19 2016-04-28 Orbotech Ltd. Llift printing of conductive traces onto a semiconductor substrate
EP3247816A4 (en) 2015-01-19 2018-01-24 Orbotech Ltd. Printing of three-dimensional metal structures with a sacrificial support
JP2016192447A (ja) * 2015-03-30 2016-11-10 株式会社東芝 半導体装置
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof
US9842831B2 (en) 2015-05-14 2017-12-12 Mediatek Inc. Semiconductor package and fabrication method thereof
WO2017006306A1 (en) 2015-07-09 2017-01-12 Orbotech Ltd Control of lift ejection angle
US10688692B2 (en) 2015-11-22 2020-06-23 Orbotech Ltd. Control of surface properties of printed three-dimensional structures
US10903319B2 (en) * 2016-06-15 2021-01-26 Nanomedical Diagnostics, Inc. Patterning graphene with a hard mask coating
DE102016224631B4 (de) * 2016-12-09 2020-06-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Elektrisch leitende Verbindung zwischen mindestens zwei elektrischen Komponenten an einem mit elektronischen und/oder elektrischen Bauelementen bestücktem Träger, die mit einem Bonddraht ausgebildet ist
WO2018120060A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Interposer design in package structures for wire bonding applications
TW201901887A (zh) * 2017-05-24 2019-01-01 以色列商奧寶科技股份有限公司 於未事先圖樣化基板上電器互連電路元件
US10546817B2 (en) * 2017-12-28 2020-01-28 Intel IP Corporation Face-up fan-out electronic package with passive components using a support
KR102102389B1 (ko) * 2018-09-18 2020-04-21 전자부품연구원 고전력 및 고주파수 응용을 위한 반도체 패키지 및 그 제조방법
TWI692062B (zh) * 2018-11-01 2020-04-21 華邦電子股份有限公司 線路結構及其製造方法
TWI677949B (zh) 2018-11-21 2019-11-21 華邦電子股份有限公司 半導體元件
KR102302633B1 (ko) * 2019-08-02 2021-09-14 동국대학교 경주캠퍼스 산학협력단 3d 프린터와 나노와이어를 이용한 초소수성 표면 제조 방법
CN113307647B (zh) * 2021-04-16 2022-05-31 长春工业大学 一种氮化铝陶瓷覆铜板的间接钎焊方法
CN114446838A (zh) * 2022-03-03 2022-05-06 芯体素(杭州)科技发展有限公司 基于3d打印工艺的植球方法、装置、电子设备及存储介质
WO2024060058A1 (en) * 2022-09-21 2024-03-28 Yangtze Advanced Memory Industrial Innovation Center Co., Ltd. Integrated circuit device, packaging, and method for forming thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201133655A (en) * 2010-03-22 2011-10-01 Powertech Technology Inc Packaging method of array-cutting type quad flat non-leaded packages

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0252443A (ja) 1988-08-17 1990-02-22 Mitsubishi Electric Corp ワイヤボンディング方法
JPH05299530A (ja) 1992-04-17 1993-11-12 Oki Electric Ind Co Ltd 樹脂封止半導体装置及びその製造方法
JPH08107123A (ja) 1994-10-04 1996-04-23 Hitachi Ltd 半導体集積回路装置の製造方法、その製造装置および半導体集積回路装置
JP2001230270A (ja) 2000-02-14 2001-08-24 Fujitsu Ltd 半導体装置及びその製造方法
JPWO2003084297A1 (ja) 2002-03-28 2005-08-11 新光電気工業株式会社 配線構造体及びその製造方法
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7176580B1 (en) 2003-10-24 2007-02-13 Joseph Fjelstad Structures and methods for wire bonding over active, brittle and low K dielectric areas of an IC chip
US7205178B2 (en) 2004-03-24 2007-04-17 Freescale Semiconductor, Inc. Land grid array packaged device and method of forming same
EP1754256B1 (en) 2004-05-28 2012-01-11 Nxp B.V. Chip having two groups of chip contacts
KR101313391B1 (ko) 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
US7394148B2 (en) 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
JP2007123595A (ja) 2005-10-28 2007-05-17 Nec Corp 半導体装置及びその実装構造
US8344524B2 (en) 2006-03-07 2013-01-01 Megica Corporation Wire bonding method for preventing polymer cracking
US20070216033A1 (en) 2006-03-20 2007-09-20 Corisis David J Carrierless chip package for integrated circuit devices, and methods of making same
US8203219B2 (en) * 2006-03-23 2012-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Electrically enhanced wirebond package
US7915081B2 (en) * 2006-03-31 2011-03-29 Intel Corporation Flexible interconnect pattern on semiconductor package
JP5598787B2 (ja) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
TWI471958B (zh) 2006-09-06 2015-02-01 Qualcomm Inc 晶片封裝結構及其製程
WO2008099326A1 (en) * 2007-02-14 2008-08-21 Nxp B.V. A carrier for bonding a semiconductor chip onto and a method of contacting a semiconductor chip to a carrier
JP5123633B2 (ja) 2007-10-10 2013-01-23 ルネサスエレクトロニクス株式会社 半導体装置および接続材料
US8035211B2 (en) 2008-03-26 2011-10-11 Stats Chippac Ltd. Integrated circuit package system with support structure under wire-in-film adhesive
JP2010087208A (ja) 2008-09-30 2010-04-15 Fujifilm Corp 立体構造物の形成方法、半導体装置の製造方法、および半導体装置
US7838332B2 (en) * 2008-11-26 2010-11-23 Infineon Technologies Ag Method of manufacturing a semiconductor package with a bump using a carrier
CN101764113B (zh) 2008-12-25 2012-02-29 俞宛伶 半导体元件的线路面的连接垫上的金属凸块结构及形成方法
KR101284376B1 (ko) * 2009-01-27 2013-07-09 파나소닉 주식회사 반도체 칩의 실장 방법, 그 방법을 이용하여 얻어진 반도체 장치 및 반도체 칩의 접속 방법, 및, 표면에 배선이 설치된 입체 구조물 및 그 제법
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
KR20100124161A (ko) 2009-05-18 2010-11-26 주식회사 하이닉스반도체 반도체 패키지의 제조방법
KR101624973B1 (ko) * 2009-09-23 2016-05-30 삼성전자주식회사 패키지 온 패키지 타입의 반도체 패키지 및 그 제조방법
JP2011077460A (ja) 2009-10-02 2011-04-14 Toyota Motor Corp 半導体装置と、その製造方法
KR101712043B1 (ko) 2010-10-14 2017-03-03 삼성전자주식회사 적층 반도체 패키지, 상기 적층 반도체 패키지를 포함하는 반도체 장치 및 상기 적층 반도체 패키지의 제조 방법
US8492203B2 (en) 2011-01-21 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
US20120228768A1 (en) 2011-03-07 2012-09-13 Reza Argenty Pagaila Integrated circuit packaging system using b-stage polymer and method of manufacture thereof
WO2012126377A1 (en) * 2011-03-22 2012-09-27 Nantong Fujitsu Microelectronics Co., Ltd. System-level packaging methods and structures
CN103843133B (zh) * 2011-07-03 2017-10-27 联达科技控股有限公司 具有热熔接封装部件的引线载体
US9324659B2 (en) * 2011-08-01 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die
US10128161B2 (en) * 2011-10-27 2018-11-13 Global Circuit Innovations, Inc. 3D printed hermetic package assembly and method
KR20140064053A (ko) 2012-11-19 2014-05-28 삼성전자주식회사 재배선 층을 갖는 반도체 패키지
JP2015527753A (ja) * 2012-09-07 2015-09-17 イオプレックス リミテッド 印刷形成による端子パッドを有するリードキャリア
TWI481901B (zh) 2012-12-03 2015-04-21 Wistron Corp 頭戴式顯示裝置
TW201436164A (zh) * 2013-01-21 2014-09-16 Pbt Pte Ltd 用於半導體封裝之基體及其形成方法
JP6273945B2 (ja) * 2013-04-26 2018-02-07 日亜化学工業株式会社 発光装置
US9281338B2 (en) 2014-04-25 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor image sensor device having back side illuminated image sensors with embedded color filters
JP6437246B2 (ja) 2014-08-28 2018-12-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR102320046B1 (ko) 2014-09-19 2021-11-01 삼성전자주식회사 캐스케이드 칩 스택을 갖는 반도체 패키지
US9972601B2 (en) 2014-09-26 2018-05-15 Intel Corporation Integrated circuit package having wirebonded multi-die stack
US9559069B2 (en) 2015-01-29 2017-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device, integrated circuit structure using the same, and manufacturing method thereof
US9960130B2 (en) 2015-02-06 2018-05-01 UTAC Headquarters Pte. Ltd. Reliable interconnect
US20160307873A1 (en) 2015-04-16 2016-10-20 Mediatek Inc. Bonding pad arrangment design for semiconductor package
US10446522B2 (en) 2015-04-16 2019-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multiple conductive features in semiconductor devices in a same formation process
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof
US9842831B2 (en) 2015-05-14 2017-12-12 Mediatek Inc. Semiconductor package and fabrication method thereof
CN205303447U (zh) 2015-12-28 2016-06-08 江阴长电先进封装有限公司 一种指纹识别传感器的封装结构
KR102570325B1 (ko) 2016-11-16 2023-08-25 에스케이하이닉스 주식회사 재배선 구조를 갖는 적층형 반도체 패키지

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201133655A (en) * 2010-03-22 2011-10-01 Powertech Technology Inc Packaging method of array-cutting type quad flat non-leaded packages

Also Published As

Publication number Publication date
CN106158818A (zh) 2016-11-23
CN106158818B (zh) 2018-11-30
US20160336303A1 (en) 2016-11-17
US20180076185A1 (en) 2018-03-15
EP3093877A2 (en) 2016-11-16
EP3093877A3 (en) 2017-02-22
TW201640599A (zh) 2016-11-16
US9842831B2 (en) 2017-12-12
US10340259B2 (en) 2019-07-02
EP3093877B1 (en) 2019-07-24

Similar Documents

Publication Publication Date Title
TWI575624B (zh) 半導體封裝及其製作方法
US11631611B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
US11424220B2 (en) Semiconductor structure and manufacturing method thereof
US10720409B2 (en) Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
CN107342277B (zh) 封装件及其形成方法
TWI667762B (zh) 半導體封裝中的重佈線層及其形成方法
TWI451505B (zh) 凹入的半導體基底和相關技術
TWI601247B (zh) 半導體封裝結構
CN113140519A (zh) 采用模制中介层的晶圆级封装
TWI714120B (zh) 封裝層電感器
US8372692B2 (en) Method of stacking flip-chip on wire-bonded chip
TW201701404A (zh) 封裝結構及封裝方法
US9082644B2 (en) Method of manufacturing and testing a chip package
US20170207153A1 (en) Semiconductor package device and method of manufacturing the same
TW201737452A (zh) 系統級封裝及用於製造系統級封裝的方法
US10115673B1 (en) Embedded substrate package structure
KR101685068B1 (ko) 시스템 인 패키지 및 이의 제조방법
CN109560055A (zh) 半导体封装装置及其制造方法
CN106469706B (zh) 电子封装件及其制法
US20230317693A1 (en) Die package, ic package and manufacturing process thereof