CN106158818A - 半导体封装及其制作方法 - Google Patents

半导体封装及其制作方法 Download PDF

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Publication number
CN106158818A
CN106158818A CN201610221935.1A CN201610221935A CN106158818A CN 106158818 A CN106158818 A CN 106158818A CN 201610221935 A CN201610221935 A CN 201610221935A CN 106158818 A CN106158818 A CN 106158818A
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semiconductor
conductive connection
molding material
semiconductor packages
grain
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CN106158818B (zh
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蔡宪聪
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明公开了一种半导体封装及其制作方法。其中该半导体封装包含有半导体晶粒、多个I/O垫、模封材和多个打印的内连结构。其中该多个I/O垫分布在该半导体晶粒的主动面上。其中，该模封材覆盖该半导体晶粒的主动面，并且该模封材的下表面与该半导体晶粒的下表面齐平。其中，该多个内连结构嵌入于该模封材中，并电连接该多个I/O垫。其中各个该打印的内连结构包含导电接线以及导电接垫，其中该导电接线与该导电接垫是一体成型的。该半导体封装，利用打印技术(如3D打印)来形成内连结构，因此可以提高半导体封装的良品率。

Description

半导体封装及其制作方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种集成电路及半导体封装的内连结构。
背景技术
已知，集成电路晶粒(IC die)是制作在半导体晶圆(例如硅晶圆)上的微细电路组件。当晶粒从晶圆切割下来后，可以黏合至基板上，以进行内连重分布。后续透过打线，可以将晶粒上的接合垫电连接至基板上的引脚(lead)。最后，将晶粒与打线以成型模料(molding compound)模封包覆起来，即构成封装。
通常，上述封装内所封装的引脚可在载体中的导体网络内重分布，并在封装外构成以阵列形式的连接端点。目前，业界已在单一封装中堆叠两个或更多的晶粒。这样的装置又可称做多芯片堆叠封装(stacked multichip package)。
图1例示已知的多芯片堆叠封装的剖面示意图。如图1所示，第一晶粒11安置在基板10上。然后，第二晶粒12可以黏合方式固定在第一晶粒11的上表面，如此构成晶粒堆叠组态。当从上往下看时，第二晶粒12部分重叠于第一晶粒11。接着，利用传统的打线机(wire bonder)形成打线16及18，从而将第一晶粒11与第二晶粒12分别电连接至基板10上对应的接合手指(bond finger)。再将模封材(encapsulant material)20包封在基材10上，以构成模封盖。
然而，上述的封装结构仍有部分缺点需要进一步克服，例如，打线18不容易形成在靠近第二晶粒12的悬出的侧边(overhanging side edge)12a上的接合垫上，这是因为打线机产生的应力可能造成第一晶粒11与第二晶粒12之间的剥离情形，导致工艺良率下降。
发明内容
有鉴于此，本发明提供了一种改良的半导体封装及其制作方法，可以提高良品率。
本发明提供了一种半导体封装，包含：第一半导体晶粒，具有主动面及相对于该主动面的下表面；多个输入/输出垫，分布在该第一半导体晶粒的主动面上；模封材，覆盖该第一半导体晶粒的主动面，其中该模封材包含下表面，其与该第一半导体晶粒的下表面齐平；以及多个打印的内连结构，嵌入于该模封材中，用以电连接该多个I/O垫，其中各该打印的内连结构包含导电接线以及导电接垫，其中该导电接线与该导电接垫是一体成型的。
其中，该导电接垫设置在该第一半导体晶粒周围的该模封材的下表面，其中该导电接垫的显露出的下表面与该模封材的下表面齐平。
其中，该导电接线与该导电接垫以3D打印而一体成型。
其中，该打印的内连结构包含：银、金、铜、纳米碳管、石墨烯或纳米金属颗粒。
其中，该模封材包含环氧树脂、树脂或可模塑的聚合物。
其中，该第一半导体晶粒的下表面未被该模封材所覆盖。
其中，该导电接线包含增宽的延伸部，设置在接近该模封材的上表面的位置。
其中，该增宽的延伸部为接垫。
其中，在该模封材的上表面中另设有开孔，显露出该接垫。
其中，在该开孔内及该接垫上，设有导电组件。
其中，在该模封材的上表面安装有晶粒封装，该晶粒封装电连接于该导电组件。
其中，另包含无源组件，嵌入于该模封料中，并电连接该打印的内连结构。
其中，另包含第二半导体晶粒，以黏合的方式固定在该第一半导体晶粒的上表面。
其中，当从上往下看时，该第二半导体晶粒部分重叠于该第一半导体晶粒。
本发明提供了一种半导体封装，包含：半导体晶粒，具有主动面及相对该主动面的下表面；多个输入/输出垫，分布在该半导体晶粒的主动面上；模封材，覆盖该半导体晶粒的主动面，其中该模封材包含下表面，其与该半导体晶粒的下表面齐平；以及多个打印的导电接线，嵌入于该模封材中，用以电连接该多个I/O垫，其中各该打印的导电接线包含直角弯折部。
其中，另包含多个导电接垫，设置在该半导体晶粒周围的该模封材的下表面，其中该导电接垫的显露出的下表面与该模封材的下表面齐平。
本发明提供了一种半导体封装的制作方法，包含：提供载体；将多个半导体晶粒设置在该载体上，其中各该半导体晶粒具有一主动面，以及相对于该主动面的下表面，其中在该主动面上分布有多个输入/输出垫；于该载体上与该半导体晶粒的主动面上打印出内连结构，该内连结构包含导电接垫及导电接线；将该载体的上表面、该半导体晶粒的上表面、该导电接线与该导电接垫以一模封材包覆住；以及移除该载体。
其中，该载体包含玻璃载板、硅载板或金属载板。
其中，该导电接线与该导电接垫是一体成型的。
其中，该内连结构包含银、金、铜、纳米碳管、石墨烯或纳米金属颗粒。
其中，该导电接线与该导电接垫是利用3D打印机或具有3D打印功能的打线机形成。
其中，在移除该载体之后，在该导电接垫上形成连接件，并在形成该连接件之后，接着进行一切割工艺，将半导体封装彼此分离开来。
本发明提供了一种半导体封装的制作方法，包含：提供载体；将多个半导体晶粒设置在该载体上；于该载板上与该多个半导体晶粒的上表面打印出临时内连结构；将该载板的上表面、该多个半导体晶粒的上表面，与该临时内连结构以一模封材包覆住；移除该载体；去除该临时内连结构，从而于该模封材内形成凹穴；以及将该凹穴以导电材料填满，形成内连结构。
其中，该内连结构包含导电接垫与导电接线，其中该导电接线与该导电接垫是一体成型的。
其中，该临时内连结构是由非导电材料或可灰化材料所构成。
其中，该内连结构包含银、金、铜、纳米碳管、石墨烯或纳米金属颗粒。
本发明的有益效果是：
上述的半导体封装及其制作方法，采用打印的方式形成内连结构或导电接线，从而提高了半导体封装的良品率。
附图说明
所附的附图提供用以方便对本发明更进一步的了解，其构成本说明书的一部分。通过所附的附图与说明书的内容一同阐述本发明实施例，有助于解释本发明的原理原则。在附图中：
图1为已知多芯片堆叠封装的剖面示意图；
图2为依据本发明实施例所绘示的半导体封装的剖面示意图；
图3为依据本发明另一实施例所绘示的封装上封装的剖面示意图；
图4为依据本发明又另一实施例所绘示的多晶粒封装的剖面示意图；
图5至图9为依据本发明实施例所绘示的制作图2中半导体封装的例示性方法示意图；
图10至图12为依据本发明另一实施例所绘示的制作图2中半导体封装的例示性方法示意图；以及
图13为依据本发明又另一实施例所绘示的半导体封装的侧视示意图。
具体实施方式
在下文中，将参照附图说明本发明实施例细节，该些附图中之内容构成说明书的一部分，并且以可实行该实施例的特例描述方式来绘示。
下文实施例已描述足够的细节使本领域技术人员得以实施。当然，亦可实行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图2，其为依据本发明实施例所绘示的半导体封装的剖面示意图。如图2所示，半导体封装1包含半导体晶粒110，该半导体晶粒110具有上表面或主动面110a，以及下表面110b，该下表面110b相对于主动面110a。在主动面110a上分布有多个接合垫或输入/输出(I/O)垫121。根据本发明实施例，主动面110a、I/O垫121，以及主动面110a与下表面110b之间的四个侧面被模封材200所覆盖住，例如成型模料(molding compound)。
在某些实施例中，模封材200可以是环氧树脂、树脂，可模塑的聚合物，或类似物所构成。模封材200可以基本上以液态施加，并且然后可以通过化学反应固化，例如在环氧树脂或树脂中。在其它一些实施例中，成型模料可以是紫外线(UV)或热固化的聚合物，以凝胶态或可延展固体形态布置围绕在半导体晶粒110周围，然后再通过UV或热固化方法来固化。模封材200可利用模具(图未示)进行固化。
根据本发明实施例，下表面110b从模封材200的下表面200b显露出来。模封材200具有上表面200a，相对于其下表面200b。根据本发明实施例，显露出来的半导体晶粒110的下表面110b与模封材200的下表面200b齐平。根据本发明实施例，在半导体晶粒110的主动面110a上不需要形成重布线层(Re-Distribution Layer，RDL)。
为简化说明，图中并未绘示出半导体晶粒110的细部结构。需理解的是，半导体晶粒110可以包含半导体基板，例如硅基板。在半导体基板的主动面上，可以形成有多个电路组件，例如，晶体管等。在半导体基板上还可以沉积有多个层间介电层(Inter-Layer Dielectric，ILD)。层间介电层可以是由有机材料或者非有机材料所构成，其中有机材料包含高分子材料，非有机材料包括氮化硅、氧化硅、石墨烯等。在层间介电层中可以形成有多个金属内连线层。前述半导体晶粒110的I/O垫121可以是形成在最上层金属层中，并由钝化层覆盖，但不限于此。
根据本发明实施例，在模封材200的下表面200b上分布有多个导电接垫216及218。所述导电接垫216及218排列在半导体晶粒110的周围，并分别经由导电接线116及118电连接至主动面110a上的I/O垫121。导电接垫216及218的显露出的下表面与模封材200的下表面200b齐平。为方便进一步连接，在导电接垫216及218上可以形成多个连接件230，例如，导电凸块(如C4凸块或铜柱)或者导电锡球(如BGA(Ball Grid Array，球栅阵列)锡球)。
本发明的主要技术特征之一在于导电接线116及118与导电接垫216及218一体成型。根据本发明实施例，例如，导电接线116及118与导电接垫216及218可以是利用3D打印机或具有3D打印功能的打线机形成。导电接线116及118与导电接垫216及218被模封材200包覆住。根据本发明实施例，不需要额外的封装基板(packaging substrate)或中介层(interposer)。另外，由于导电接线116及118是利用3D打印机或具有3D打印功能的打线机形成，所以导电接线116及118可以具有直角弯折部，如此可以避免邻近接线的短路问题。
根据本发明实施例，半导体封装1可以另包含无源组件(passive device)210，例如分立(discrete)电容组件、电阻组件、电感组件等。无源组件210可以设置在接近模封材200的下表面200b的位置。根据本发明实施例，无源组件210可以具有两个端子210a及210b，分别电连接至导电接线116a及118a。
根据本发明实施例，导电接线116a及导电接线118a分别与导电接线116及118一体成型。因此，端子210a经由一体成型的导电接线116及116a电连接至导电接垫216及半导体晶粒110，而端子210b经由一体成型的导电接线118及118a电连接至导电接垫218及半导体晶粒110。
根据本发明实施例，导电接线116或118可以有一体的延伸部，具有不同的图案、尺寸或结构，沿着导电接线116或118的走线长度方向形成。例如，图2中绘示出导电接线118可以具有增宽的延伸部118b，其设置在接近模封材200的上表面200a的位置。上述增宽的延伸部118b可以包含接垫、盘体、网格等形状，但不限于此。
请参阅图3，其为依据本发明另一实施例所绘示的半导体封装的剖面示意图，其中相同的区域、层或组件沿用相同的符号来表示。如图3所示，半导体封装2可以是封装上封装(Package-on-Package，PoP)。半导体封装2包含下晶粒封装100，其结构特征类似图2中所描述的结构特征。下晶粒封装100与图2中的半导体封装1的差异在于，下晶粒封装100的模封材200的上表面200a另形成有开孔260，例如，雷射钻孔。
各个开孔260可以显露出部分的延伸部118b，在此实施例中，延伸部118b为一体成型的接合垫。在开孔260内及显露出的延伸部118b上，形成有导电组件320，该导电组件320包括但不限于：凸块下金属(under bump metal)及凸块。在导电组件320上则安装有上晶粒封装300，其包含已模封的集成电路晶粒310。
请参阅图4，其为依据本发明又另一实施例所绘示的半导体封装的剖面示意图，其中相同的区域、层或组件沿用相同的符号来表示。如图4所示，半导体封装3可以是多晶粒封装。半导体封装3包含下半导体晶粒110以及上半导体晶粒410，其中上半导体晶粒410直接堆叠在下半导体晶粒110上。上半导体晶粒410可以利用黏合的方式固定在下半导体晶粒110的上表面。在下半导体晶粒110的主动面110a上分布有多个接垫或I/O垫121，在上半导体晶粒410的主动面410a上分布有多个接垫或I/O垫421。
根据本发明实施例，当从上往下看时，上半导体晶粒410部分重叠于下半导体晶粒110。因此，上半导体晶粒410具有悬出的侧边412。根据本发明实施例，所述悬出的侧边412与超过下半导体晶粒110的边缘的下表面410b被模封材200所包覆。
同样的，在模封材200的下表面200b分布有多个导电接垫216及218。所述导电接垫216及218以阵列方式排列在半导体晶粒110的周围，并分别经由导电接线116及118电连接至主动面110a上的I/O垫121及主动面410a上的I/O垫421。
为方便进一步连接，在导电接垫216及218上可以形成多个连接件230，例如，导电凸块(如C4凸块或铜柱)或者导电锡球(如BGA锡球)。根据本发明实施例，例如，至少一个I/O垫421经由导电接线118及分支的导电接线118a与至少一个I/O垫121电连接，其中分支的导电接线118a与导电接线118为一体成型的。
图5至图9为依据本发明实施例所绘示的制作图2中半导体封装1的例示性方法示意图。首先，如图5所示，提供载体500。载体500可以为包含玻璃、硅、金属或任何合适材料的载体。接着将多个半导体晶粒110设置在载体500上。各个半导体晶粒110具有上表面或主动面110a，以及下表面110b，该下表面110b相对于主动面110a。在主动面110a上分布有多个接合垫或I/O垫121。
半导体晶粒110可以利用黏合的方式固定在载板500的上表面。此外，可选择在载板500上设置无源组件210，例如分立电容组件、电阻组件、电感组件等。
如图6所示，接着在载板500上以及半导体晶粒110的主动面110a上形成内连结构510，该内连结构510包括但不限于：导电接垫216及218以及导电接线116及118。导电接线116及118分别与导电接垫216及218一体成型的。无源组件210可以具有两个端子210a及210b，分别电连接至导电接线116a及118a。
例如，导电接线116及118与导电接垫216及218可以是利用3D打印机或具有3D打印功能的打线机形成。例如，内连结构510可以包含银、金、铜、纳米碳管、石墨烯或纳米金属颗粒，但不限于此。在形成内连结构510之后，可选择进行固化工艺或干燥工艺，以固化内连结构510及/或去除内连结构510中的溶剂。
根据本发明实施例，例如，导电接线118或者116可以有一体的延伸部，具有不同的图案、尺寸或结构，沿着导电接线118或者116的走线长度方向形成。例如，导电接线118可以具有增宽的延伸部118b。增宽的延伸部118b可以包含接垫、盘体、网格等形状，但不限于此。需理解的是，在此阶段，还可以另外在载体500上印刷出其他结构，例如热管(heat pipe)(图未示)。
如图7所示，接着，将载体500的上表面、半导体晶粒110的上表面110a、导电接线116及118与导电接垫216及218以模封材200包覆住。例如，模封材200可以包含成型模料，包含但不限于，环氧树脂或树脂。
如图8所示，接着将载体500去除，以显露出模封材200的下表面200b、半导体晶粒110的下表面110b，以及导电接垫216及218。为方便进一步连接，在导电接垫216及218上可以形成有多个连接件230，例如，导电凸块(如C4凸块或铜柱)或者导电锡球(如BGA锡球)。尽管图中未绘示，应理解在模封材200的下表面200b与半导体晶粒110的下表面110b可以另形成有钝化层。
如图9所示，在形成连接件230之后，随后进行晶圆切割工艺，以将个别的半导体封装1彼此分离开来。在上述晶圆切割工艺过程中，可以使用切割胶带(图未示)，以提供临时的支撑。
图10至图12为依据本发明另一实施例所绘示的制作半导体封装1的例示性方法示意图，其中相同的区域、层或组件能沿用相同的符号来表示。
如图10所示，在载板500上安装好半导体晶粒110及无源组件210之后，接着以3D打印形成临时内连结构510’。根据本发明实施例，上述临时内连结构510’可以是由非导电材料或可灰化(ashable)材料所构成。为简化说明，在载板500上仅显示出一个半导体晶粒110。
接着，以模封材200包覆载板500的上表面、半导体晶粒110的上表面110a，及上述临时内连结构510’。例如，模封材200可以包含环氧树脂成型模料。
如图11所示，接着将载板500去除，以显露出模封材200的下表面200b、半导体晶粒110的下表面110b，及部分的临时内连结构510’。接着，将临时内连结构510’完全去除，如此在模封材200内形成凹穴530。
如图12所示，接着以导电材料将凹穴530填满，形成内连结构510，该内连结构510包括但不限于，导电接垫216及218与导电接线116及118。导电接线116及118分别是与导电接垫216及218一体成型的。无源组件210可以具有两个端子210a及210b，分别电连接至导电接线116a及118a。
例如，内连结构510可以包含银、金、铜、纳米碳管、石墨烯或纳米金属颗粒，但不限于此。在形成内连结构510之后，可选择进行固化工艺、回焊工艺或干燥工艺。
图13为依据本发明又另一实施例所绘示的半导体封装的侧视示意图，其中相同的区域、层或组件沿用相同的符号来表示。如图13所示，半导体封装4可以是多晶粒封装。半导体封装4可以包含基板101，具有上表面101a及下表面101b，其中上表面101a与下表面101b是相反的两个面。基板101可以是封装基板或印刷电路板，但不限于此。沿着基板101的上表面101a的周缘，设有多个接合手指(又称”金手指”)102。在基板101的下表面101b上，设有多个锡球103。
半导体封装4包含下半导体晶粒110以及上半导体晶粒410，其中上半导体晶粒410直接堆叠在下半导体晶粒110上。上半导体晶粒410可以利用黏合的方式固定在下半导体晶粒110的上表面110a。在下半导体晶粒110的主动面110a上分布有多个接合垫或I/O垫121，在上半导体晶粒410的主动面410a上分布有多个接合垫或I/O垫421。根据本发明实施例，当从上往下看时，上半导体晶粒410部分重叠于下半导体晶粒110。因此，上半导体晶粒410具有悬突的侧边412。根据本发明实施例，所述悬突的侧边412与上半导体晶粒410超出下半导体晶粒110的边缘的下表面被模封材(图未示)所包覆。
根据本发明实施例，在上半导体晶粒410的主动面410a上与下半导体晶粒110的主动面110a上，形成有3D打印结构600，该3D打印结构包括但不限于，导电接线610、电源管理单元(Power Management Unit，PMU)热管620、电感630及电源柱(power bar)640等。根据本发明实施例，所述导电接线610可以内连I/O垫421、I/O垫121及/或接合手指102。例如，其中导电接线610可以透过次接线610a电连接至多个接合指102，其中次接线610a与此导电接线610一体成型。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (25)

1.一种半导体封装，其特征在于，包含：
第一半导体晶粒，具有主动面及相对于该主动面的下表面；
多个输入/输出垫，分布在该第一半导体晶粒的主动面上；
模封材，覆盖该第一半导体晶粒的主动面，其中该模封材包含下表面，其与该第一半导体晶粒的下表面齐平；以及
多个打印的内连结构，嵌入于该模封材中，用以电连接该多个I/O垫，其中各该打印的内连结构包含导电接线以及导电接垫，其中该导电接线与该导电接垫是一体成型的。
2.如权利要求1所述的半导体封装，其特征在于，该导电接垫设置在该第一半导体晶粒周围的该模封材的下表面，其中该导电接垫的显露出的下表面与该模封材的下表面齐平。
3.如权利要求1所述的半导体封装，其特征在于，该导电接线与该导电接垫以3D打印而一体成型。
4.如权利要求1所述的半导体封装，其特征在于，该打印的内连结构包含：银、金、铜、纳米碳管、石墨烯、纳米金属颗粒中至少一种；和/或，
该模封材包含环氧树脂、树脂、可模塑的聚合物中至少一种。
5.如权利要求1所述的半导体封装，其特征在于，该第一半导体晶粒的下表面未被该模封材所覆盖。
6.如权利要求1所述的半导体封装，其特征在于，该导电接线包含增宽的延伸部，设置在接近该模封材的上表面的位置。
7.如权利要求6所述的半导体封装，其特征在于，该增宽的延伸部为接垫。
8.如权利要求7所述的半导体封装，其特征在于，在该模封材的上表面中另设有开孔，显露出该接垫。
9.如权利要求8所述的半导体封装，其特征在于，在该开孔内及该接垫上，设有导电组件。
10.如权利要求9所述的半导体封装，其特征在于，在该模封材的上表面安装有晶粒封装，该晶粒封装电连接于该导电组件。
11.如权利要求1所述的半导体封装，其特征在于，另包含无源组件，嵌入于该模封料中，并电连接该打印的内连结构。
12.如权利要求1所述的半导体封装，其特征在于，另包含第二半导体晶粒，以黏合的方式固定在该第一半导体晶粒的上表面。
13.如权利要求12所述的半导体封装，其特征在于，当从上往下看时，该第二半导体晶粒部分重叠于该第一半导体晶粒。
14.一种半导体封装，其特征在于，包含：
半导体晶粒，具有主动面及相对该主动面的下表面；
多个输入/输出垫，分布在该半导体晶粒的主动面上；
模封材，覆盖该半导体晶粒的主动面，其中该模封材包含下表面，其与该半导体晶粒的下表面齐平；以及
多个打印的导电接线，嵌入于该模封材中，用以电连接该多个I/O垫，其中各打印的导电接线包含直角弯折部。
15.如权利要求14所述的半导体封装，其特征在于，另包含多个导电接垫，设置在该半导体晶粒周围的该模封材的下表面，其中该导电接垫的显露出的下表面与该模封材的下表面齐平。
16.一种半导体封装的制作方法，其特征在于，包含：
提供载体；
将多个半导体晶粒设置在该载体上，其中各该半导体晶粒具有一主动面，以及相对于该主动面的下表面，其中在该主动面上分布有多个输入/输出垫；
于该载体上与该半导体晶粒的主动面上打印出内连结构，该内连结构包含导电接垫及导电接线；
将该载体的上表面、该半导体晶粒的上表面、该导电接线与该导电接垫以一模封材包覆住；以及
移除该载体。
17.如权利要求16所述的半导体封装的制作方法，其特征在于，该载体包含玻璃载板、硅载板或金属载板。
18.如权利要求16所述的半导体封装的制作方法，其特征在于，该导电接线与该导电接垫是一体成型的。
19.如权利要求16所述的半导体封装的制作方法，其特征在于，该内连结构包含银、金、铜、纳米碳管、石墨烯或纳米金属颗粒。
20.如权利要求16所述的半导体封装的制作方法，其特征在于，该导电接线与该导电接垫是利用3D打印机或具有3D打印功能的打线机形成。
21.如权利要求16所述的半导体封装的制作方法，其特征在于，在移除该载体之后，在该导电接垫上形成连接件，并在形成该连接件之后，接着进行切割工艺，将各个半导体封装彼此分离开来。
22.一种半导体封装的制作方法，其特征在于，包含：
提供载体；
将多个半导体晶粒设置在该载体上；
于该载板上与该多个半导体晶粒的上表面打印出临时内连结构；
将该载板的上表面、该多个半导体晶粒的上表面，与该临时内连结构以一模封材包覆住；
移除该载体；
去除该临时内连结构，从而于该模封材内形成凹穴；以及
将该凹穴以导电材料填满，形成内连结构。
23.如权利要求22所述的半导体封装的制作方法，其特征在于，该内连结构包含导电接垫与导电接线，其中该导电接线与该导电接垫是一体成型的。
24.如权利要求22所述的半导体封装的制作方法，其特征在于，该临时内连结构是由非导电材料或可灰化材料所构成。
25.如权利要求22所述的半导体封装的制作方法，其特征在于，该内连结构包含银、金、铜、纳米碳管、石墨烯或纳米金属颗粒。
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US9842831B2 (en) 2017-12-12

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