CN109003958A - 矩形半导体封装及其方法 - Google Patents

矩形半导体封装及其方法 Download PDF

Info

Publication number
CN109003958A
CN109003958A CN201710669623.1A CN201710669623A CN109003958A CN 109003958 A CN109003958 A CN 109003958A CN 201710669623 A CN201710669623 A CN 201710669623A CN 109003958 A CN109003958 A CN 109003958A
Authority
CN
China
Prior art keywords
crystal grain
routing layer
conductive
rectangular shaped
shaped semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710669623.1A
Other languages
English (en)
Inventor
于鸿祺
林俊荣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Walton Advanced Engineering Inc
Original Assignee
Walton Advanced Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Walton Advanced Engineering Inc filed Critical Walton Advanced Engineering Inc
Publication of CN109003958A publication Critical patent/CN109003958A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及一种矩形半导体封装及其方法，其为晶圆切割为晶粒后封装而不具备载板；其包含，一导电路由层；所述导电路由层的一顶面上有一第一晶粒；所述第一晶粒通过复数条第一金属线与所述导电路由层电性连接；复数个导电球体，其位于所述导电路由层的一底面上；一模制化合物，其囊封所述导电路由层上的所述第一晶粒。由此，本发明利用导电路由层取代电路板，通过移除载板以降低封装厚度及成本，并凭借在晶圆厂外实行扇出型封装加工增进堆叠式封装变化性。

Description

矩形半导体封装及其方法
技术领域
本发明涉及一种半导体封装件及其制法，特别在于扇出型封装应用于晶圆切割下的晶粒，不具备载板，而依线路重布局技术产生的导电路由层为基底。
背景技术
现今在集成电路的封装技术中，多会先将集成电路晶粒囊封于囊封材料中，尔后利用基板上的电路或基板上的构建晶圆重布层达成产生扇出区域，通过扇出型区域增加更多空间以用于增设更多输出/输入点。
随着电子产品的功能越趋复杂，导致上游零件的晶粒须具备较多的输出/输入连接，配合的封装跟着需在限制空间内引出更多的连接点，同时对很流行的堆叠式封装(package on package，POP)应用产生挑战，需在更小的空间内布置更多的输出/输入点。
从2016年iPhone7的A10处理器和天线开关模块使用扇出型晶圆级封装(Fan-outWafer Level Packaging，FoWLP)技术取代传统PCB基板，通过此制程可使封装后更薄成本更低，使得此封装技术未来将被更多芯片厂商采纳。
关于扇出型封装的文献，有多个专利如下：
美国专利号US 62/082,557揭示一种散出型晶圆级封装及形成方法。在一实施例中，一封装包括一第一路由层、该第一路由层的一顶面上的一第一晶粒及囊封该第一路由层上的该第一晶粒的一第一模制化合物。第一复数个导电柱自该第一路由层的一底面延伸。一第二晶粒位于一第二路由层的一顶面上，且该第一复数个导电柱位于该路由层的该顶面上。一第二模制化合物囊封该第一模制化合物、该第一路由层、该第一复数个导电柱及该第二路由层上的该第二晶粒。在一实施例中，复数个导电凸块(例如，焊球)自该第二路由层的一底面延伸。
中国台湾专利TW I351088揭示一种晶圆级芯片封装结构，包括：一晶粒其主动面上配置有复数个焊垫，一封胶体包覆晶粒的五个面、一图案化的高分子材料层以及复数个图案化的金属线段覆盖部份图案化的高分子材料层，通过复数个图案化的金属线段电性连接至每一晶粒的主动面上的复数个焊垫，其特征在于：图案化的高分子材料层，是在晶粒的主动面上及其外侧一部份区域形成一向外延伸(fan out)的一阶梯状结构，其中向外延伸的端点处其阶梯结构中具有较高的结构且在相对于晶粒的主动面的复数个焊垫处形成一孔洞，以曝露出每一焊垫；复数个图案化的金属线段形成于图案化的高分子材料层上，以使每一晶粒的主动面上的复数个焊垫与阶梯状结构的高分子材料层上的复数个图案化的金属线段电性连接；一保护层，以覆盖复数个图案化的金属线段及部份图案化的高分子材料层，并曝露出阶梯结构中位于较高处的图案化的高分子材料层上的复数个图案化的金属线段的一表面。
中国台湾专利TW 104139373揭示具有虚设晶粒的扇出堆叠系统级封装(SIP)及其制造方法。一例示性封装包含第一扇出层、该第一扇出层上方的扇出重布层(RDL)、以及该扇出RDL上方的第二扇出层。该第一扇出层包含一或复数第一装置晶粒、及沿着该一或复数第一装置晶粒的侧壁延伸的第一模塑料。该第二扇出层包含接合至扇出RDL的一或复数个装置晶粒、接合至该扇出RDL的虚设晶粒、及沿着该一或复数第二装置晶粒与该虚设晶粒的侧壁延伸的第二模塑料。该扇出RDL将该一或复数第一装置晶粒电性连接至该一或复数第二装置晶粒，且该虚设晶粒质质上不具有任何有源装置；依以上改善因质材不同产生的封装翘曲。
中国台湾专利TW I298193揭示一种半导体构装组件，包括具有一凹槽(cavity)或沟槽(slot)于一载板上。至少一具有背面(back surface)及包括第一焊垫(bonding pads)的主动面(active surface)的芯片，此芯片固定于凹槽中，并暴露出其主动面。一第一绝缘层于载板与主动面上，其包括第一导电通孔穿透其中，并连接第一焊垫。一多层结构于第一绝缘层上，其包含布局导线、第二导电通孔于其中，及至少一第二绝缘层于其上，并暴露出锡球焊垫(ball pad)于多层结构上。其中布局导线、第二导电通孔及锡球焊垫与第一导电通孔有电性上的连接。锡球(solder ball)则是固定于锡球焊垫上。如此的架构整合一般覆晶构装制程中的重新分布与接脚间距扩散(fan-out)制程，简化了覆晶球栅阵列现有制程。
美国专利US 6770959B2揭示无载板的半导体封装及其制造方法包括提供在选定位置具有被焊接区域的前表面的临时载板。未被焊接区域覆盖的前表面形成有多个引线层和管芯焊盘层。芯片焊盘层的顶侧附着在芯片上。芯片和引线层通过多根接合线电连接。芯片、接合线、焊接区域、引线层和芯片焊盘层被模制树脂覆盖。在封装被单独化之后，通过蚀刻去除临时载板以形成没有载板的半导体封装。
然而，此扇出型晶圆级封装技术因需在晶圆型态下加工制作，使后段封装业者面临巨大压力，且在晶粒元件下如何达成类似效果也需考虑未来各种可能。
发明内容
针对上述问题，本发明的主要目的在于提供一种矩形半导体封装及其方法，主要利用现今扇出型封装应用于晶圆切割下的晶粒，以达成扇出型晶圆级封装特性，并具备不需要载板以降低封装厚度及成本的特性。
本发明再一目的在于提供一种矩形半导体封装及其方法，其将现今扇出型晶圆级制程转化为扇出型晶粒级制程。
本发明再一目的在于提供一种矩形半导体封装及其方法，其可依扇出型封装来提高晶粒封装后的导通输出输入点。
本发明再一目的在于提供一种矩形半导体封装及其方法，因封装后变薄，在现今内存产品中更可增加多层堆加转而增加容量。
本发明再一目的在于提供一种矩形半导体封装及其方法，其凭借晶粒级后加工封装，可提升小厂采购及制程变化性。
为达到上述目的，本发明所提供的一种矩形半导体封装，其为晶圆切割为晶粒后封装而不具备载板，其特征在于包含：一导电路由层；所述导电路由层的一顶面上有一第一晶粒；所述第一晶粒通过复数条第一金属线与所述导电路由层电性连接；复数个导电球体，其位于所述导电路由层的一底面上；一模制化合物，其囊封所述导电路由层上的所述第一晶粒。
上述本发明的技术方案中，所述导电路由层的所述顶面上延伸复数个导电凸块。
所述导电路由层包含一第二晶粒，所述第二晶粒位于所述第一晶粒上方或一侧。
所述复数个导电凸块显露于所述模制化合物表面，为凹槽或平面显露。
所述第二晶粒通过所述复数个导电凸块与所述导电路由层电性连接。
所述第二晶粒通过复数条第二金属线与所述导电路由层电性连接。
所述模制化合物囊封所述第二晶粒。
所述模制化合物并不覆盖所述第二晶粒的一顶面。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现：
一种矩形半导体封装方法，其为晶圆切割为晶粒后封装而不具备载板，其步骤包含：
步骤1：将一载体上通过线路重布技术制作一导电路由层；
步骤2：将一第一晶粒与所述导电路由层黏合固定，再通过复数条第一金属线将所述第一晶粒与所述导电路由层电性连接；
步骤3：将一模制化合物囊封所述第一晶粒；
步骤4：移除所述载体；
步骤5：将复数个导电球体与所述导电路由层接合。
上述矩形半导体封装方法，步骤1时，将一载体上通过线路重布技术制作复数个导电凸块。
步骤1后，将一第二晶粒堆放于所述第一晶粒上方。
步骤1后，将一第二晶粒设置于所述第一晶粒一侧。
步骤3后，加工将所述复数个导电凸块显露于所述模制化合物表面。
在步骤3前，再通过复数条第二金属线将所述第二晶粒与所述导电路由层电性连接。
在步骤3时，将所述模制化合物囊封所述第二晶粒。
在步骤3后，一封装件堆叠于所述模制化合物上，且电性连接于所述复数个导电凸块。
采用上述技术方案，本发明相较于习知技术具有的功效在于：(1)利用导电路由层取代电路板；(2)通过移除载板以降低封装厚度及成本；(3)凭借在晶圆厂外实行扇出型封装加工增进堆叠式封装变化性。
附图说明
图1是本发明最佳实施型态的载体示意图；
图2a是本发明最佳实施型态的第一增生导电路由层示意图；
图2b是本发明最佳实施型态的第二增生导电路由层示意图；
图3a是本发明最佳实施型态的第一金属线连接晶粒示意图；
图3b是本发明最佳实施型态的第二金属线连接晶粒示意图；
图3c是本发明最佳实施型态的第三金属线连接晶粒示意图；
图3d是本发明最佳实施型态的第四金属线连接晶粒示意图；
图3e是本发明最佳实施型态的第五金属线连接晶粒示意图；
图4a是本发明最佳实施型态的第一封装示意图；
图4b是本发明最佳实施型态的第二封装示意图；
图4c是本发明最佳实施型态的第三封装示意图；
图4d是本发明最佳实施型态的第四封装示意图；
图4e是本发明最佳实施型态的第五封装示意图；
图5a是本发明最佳实施型态的第一移除载体示意图；
图5b是本发明最佳实施型态的第二移除载体示意图；
图5c是本发明最佳实施型态的第三移除载体示意图；
图6a是本发明最佳实施型态的第一增加导电球体示意图；
图6b是本发明最佳实施型态的第一加工示意图；
图6c是本发明最佳实施型态的第二增加导电球体示意图；
图6d是本发明最佳实施型态的第二加工示意图；
图6e是本发明最佳实施型态的第三增加导电球体示意图；
图7a是本发明最佳实施型态的第一封装堆叠示意图；
图7b是本发明最佳实施型态的第二封装堆叠示意图；
图8a是本发明最佳实施型态的第一结构示意图；
图8b是本发明最佳实施型态的第二结构示意图；
图8c是本发明最佳实施型态的第三结构示意图；
图8d是本发明最佳实施型态的第四结构示意图；
图9是本发明最佳实施型态的第一流程图；
图10a是本发明最佳实施型态的第二流程图；
图10b是本发明最佳实施型态的第三流程图；
图11是本发明最佳实施型态的第四流程图；
图12是本发明最佳实施型态的第五流程图。
具体实施方式
为了让本发明的目的、特征与功效更明显易懂，以下特别列举本发明的较佳实施例并结合附图进行详细说明。
如图1、2a、3a、4a、5a、6a、8a及图9所示，是本发明一种矩形半导体封装及其方法的第一实施型态；先如图8a所示，一导电路由层10；导电路由层10的一顶面11上的一第一晶粒20；第一晶粒20通过复数条第一金属线14与导电路由层10电性连接；复数个导电球体15，其位于导电路由层10的一底面13上；一模制化合物40，其囊封导电路由层10上的第一晶粒20。
具体而言，导电路由层10指通过重分布制程(Redistribution Layer，RDL)将原设计的IC线路接点位置(I/O pad)，通过晶圆级金属布线制程或凸块制程来改变其接点位置，使IC能应用于不同的元件模块，在此强调由金属建构的导电层；第一晶粒20指晶粒(Die)是以半导体材料制作而成未经封装的一小块集成电路本体，主要来源是由晶圆切割分离；其中，第一金属线14实为打线接合(Wire bonding)的金属线材，是利用线径15-50微米的金属线材将晶粒(Chip)及导线架(Lead Frame)连接起来的技术，使微小的芯片得以与外面的电路做沟通，而不需要增加太多的面积；另，导电球体15现今实务上是锡球(Solder Ball)，其功效是提供导电路由层10与外界的电性连接；模制化合物40为半导体封装材料，一般使用高分子树脂作为电子元件及晶粒(Chip)的封装材料。
再如图9所示，其中步骤1(51)是将一载体1上通过线路重布技术制作一导电路由层10；如图1及图2a所示，在图1中是单纯的载体1，经由重分布制程(RedistributionLayer，RDL)在图2b中生成导电路由层10。
跟着，再如图9所示，其中步骤2(52)是将一第一晶粒20与导电路由层10黏合固定，再通过复数条第一金属线14将第一晶粒20与导电路由层10电性连接；再如图2a及图3a所示，先将第一晶粒20通过黏合固定在导电路由层10上，再通过打线接合技术将复数条第一金属线14固定于导电路由层10的顶面11和第一晶粒20间，达成两者电性导通。
再如图9所示，其中步骤3(53)是将一模制化合物40囊封第一晶粒20；如图3a及图4a所示，使用模具将高分子树脂贯注于导电路由层10上，将第一金属线14与第一晶粒20包覆。
接着，如图9所示，其中步骤4(54)是移除载体1；如图4a及图5a所示，经由制具将载体1移除，使导电路由层10底层显露于外。
最后，如图9所示，其中步骤5(55)是并将复数个导电球体15与导电路由层10接合；如图5a及图6a所示，将导电球体15黏接于导电路由层10底层，以便后续制程电性连接第一晶粒20。
再如图1、2a、3c、4c、5b、6c、8b及图10a所示，是本发明一种矩形半导体封装及其方法的第二实施型态；第二实施型态与第一实施型态的主要差异在于本实施型态增加第二金属线141及第二晶粒30；先如图8b所示，在第一晶粒20上方具有一第二晶粒30，第二晶粒30，通过复数条第二金属线141与导电路由层10电性连接。
具体而言，第二晶粒30指晶粒(Die)是以半导体材料制作而成未经封装的一小块集成电路本体，主要来源是由晶圆切割分离；其中，第二金属线141是打线接合(Wirebonding)的金属线材，是利用线径15-50微米的金属线材将晶粒(Chip)及导线架(LeadFrame)连接起来的技术，使微小的芯片得以与外面的电路做沟通，而不需要增加太多的面积。
再如图10a所示，其中步骤1(51)至步骤2(52)与第一实施型态完全一致；接着，图10a的步骤2-1(521)是将一第二晶粒30堆放于第一晶粒20上方；接续步骤2-2(522)是再通过复数条第二金属线141将第二晶粒30与导电路由层10电性连接；如图3c所示，将第二晶粒30黏贴固定于第一晶粒20上方，再通过打线接合技术将复数条第二金属线141固定于导电路由层10的顶面11和第二晶粒30间，达成两者电性导通；其中，步骤2(52)、步骤2-1(521)及步骤2-2(522)三者，可先堆叠第一晶粒20及第二晶粒30，再打线；步骤2(52)、步骤2-1(521)及步骤2-2(522)三者，可先堆叠第一晶粒20及打线后，再堆叠第二晶粒30及打线。
再如图10a所示，其中步骤3(53)同时实行步骤3-2(532)是将一模制化合物40囊封第二晶粒20；如图3c及图4c所示，使用模具将高分子树脂贯注于导电路由层10上，将第一金属线14、第一晶粒20、第二金属线141与第二晶粒30包覆。
最后，再参阅图10a所示，其中步骤4(54)至步骤5(55)与第一实施型态完全一致。
本第二实施型态，另可如图8d所示，不具备步骤2-2(522)的复数条第二金属线141，并使模制化合物40并不覆盖第二晶粒30的一顶面；具体而言，此时第二晶粒30不具电子功能，主要功效是防止封装后变形的辅助封装材料。
请再如图1、2a、3e、4e、5c、6e及图10b所示，是本发明一种矩形半导体封装及其方法的第三实施型态；第三实施型态与第二实施型态的主要差异在于本实施型态第二晶粒30位于第一晶粒20一侧，而非上方；请先参考图6e所示，在第一晶粒20一侧具有一第二晶粒30，第二晶粒30，通过复数条第二金属线141与导电路由层10电性连接。
请再如图10b所示，其中步骤1(51)至步骤2(52)与第二实施型态完全一致；接着，图10b的步骤2-1a(521a)是将一第二晶粒30设置于第一晶粒20一侧；接续步骤2-2(522)是再通过复数条第二金属线141将第二晶粒30与导电路由层10电性连接；如图3e所示，将第二晶粒30黏贴固定于第一晶粒20一侧，再通过打线接合技术将复数第二金属线141固定于导电路由层10的顶面11和第二晶粒30间，达成两者电性导通；其中，步骤2(52)、步骤2-1a(521a)及步骤2-2(522)三者，可先分别设置第一晶粒20及第二晶粒30，再打线；步骤2(52)、步骤2-1a(521a)及步骤2-2(522)三者，可先设置第一晶粒20及打线后，再设置第二晶粒30及打线。
再如图10b所示，其中步骤3(53)同时实行步骤3-2(532)是将一模制化合物40囊封第二晶粒20；如图3e及图4e表示，使用模具将高分子树脂贯注于导电路由层10上，将第一金属线14、第一晶粒20、第二金属线141与第二晶粒30包覆。
最后，再如图10b所示，其中步骤4(54)至步骤5(55)与第二实施型态完全一致。
再如图1、2b、3b、4b、6b、7a及图11所示，是本发明一种矩形半导体封装及其方法的第四实施型态；第四实施型态与第一实施型态的主要差异在于本实施型态增加导电凸块12及另一封装件；如图7a所示，在模制化合物40上方堆叠另一封装件。
再如图11所示，其中步骤1(51)至步骤3(53)与第一实施型态完全一致；首先，图11的步骤1(51)同时实行步骤1-1(511)，步骤1-1(511)是将一载体1上通过线路重布技术制作复数个导电凸块12，呈现如图2b所示；步骤2(52)时呈现如图3b所示；步骤3(53)时呈现如图4b所示。
接着，参阅图11所示，在步骤3(53)后实行步骤3-1(531)，步骤3-1(531)与图6b是加工将复数个导电凸块12显露于模制化合物40表面；此步骤3-1(531)目的是将可再电性连接导电路由层10的导电凸块12显露于外，以方便后续加工。
再如图11所示，在步骤3-1(531)后实行步骤3-3(533)，步骤3-3(533)与图7a是一封装件堆叠于模制化合物40上，且电性连接于复数个导电凸块12；此步骤3-3(533)目的是将封装具备其他功能的晶粒通过导电路由层10电性连接外部。
本第四实施型态，另可如图8c所示，第二晶粒30，通过复数个导电凸块12与导电路由层10电性连接。
再如图1、2b、3b、4d、6d、7b及图12所示，是本发明一种矩形半导体封装及其方法的第五实施型态；第五实施型态是第二实施型态及第四实施型态整合后型态。
再如图12所示，其中步骤1(51)是将一载体1上通过线路重布技术制作一导电路由层10；如图1及图2b所示，在图1中是单纯的载体1，经由重分布制程(RedistributionLayer，RDL)在图2b中生成导电路由层10。
同时，实行图12的步骤1-1(511)，步骤1-1(511)是将一载体1上通过线路重布技术制作复数个导电凸块12，呈现如图2b所示。
跟着，再如图12所示，其中步骤2(52)是将一第一晶粒20与导电路由层10黏合固定，再通过复数条第一金属线14将第一晶粒20与导电路由层10电性连接；如图2b及图3b所示，先将第一晶粒20黏合固定在导电路由层10上，再利用打线接合技术将复数条第一金属线14固定于导电路由层10的顶面11和第一晶粒20间，达成两者电性导通。
接着，如图12的步骤2-1(521)所示，将一第二晶粒30堆放于第一晶粒20上方；接续步骤2-2(522)，再通过复数条第二金属线141将第二晶粒30与导电路由层10电性连接；如图3d所示，将第二晶粒30黏贴固定于第一晶粒20上方，再利用打线接合技术将复数条第二金属线141固定于导电路由层10的顶面11和第二晶粒30间，达成两者电性导通；其中，步骤2(52)、步骤2-1(521)及步骤2-2(522)三者，可先堆叠第一晶粒20及第二晶粒30，再打线；步骤2(52)、步骤2-1(521)及步骤2-2(522)三者，可先堆叠第一晶粒20及打线后，再堆叠第二晶粒30及打线。
再如图12所示，其中步骤3(53)同时实行步骤3-2(532)，将一模制化合物40囊封第二晶粒20；如图3d及图4d所示，使用模具将高分子树脂贯注于导电路由层10上，将第一金属线14、第一晶粒20、第二金属线141与第二晶粒30包覆。
跟着，如图12所示，在步骤3(53)后实行步骤3-1(531)，步骤3-1(531)与图6d是加工将复数个导电凸块12显露于模制化合物40表面；此步骤3-1(531)的目的是将可再电性连接导电路由层10的导电凸块12显露于外，以方便后加工。
如图12所示，在步骤3-1(531)后实行步骤3-3(533)，步骤3-3(533)与图7b是一封装件堆叠于模制化合物40上，且电性连接于复数个导电凸块12；此步骤3-3(533)目的是将封装具备其他功能的晶粒透过导电路由层10电性连接外部。
接着，如图12所示，其中步骤4(54)是移除载体1；如图4d所示，经由制具将载体1移除，使导电路由层10底层显露于外。
最后，如图12所示，其中步骤5(55)是将复数个导电球体15与导电路由层10接合；如图6d所示，将导电球体15黏接于导电路由层10底层，以便后续制程电性连接第一晶粒20。
因此本发明的功效有别于一般半导体封装结构，在半导体封装当中实属首创，符合发明专利要件。
需再次重申，以上所述仅是本发明的较佳实施型态，凡应用本发明说明书、权利要求书或附图所做的等效变化，仍属本发明所保护的技术范畴，因此本发明的专利保护范围当以后附的权利要求书所界定的范围为准。

Claims (16)

1.一种矩形半导体封装，其为晶圆切割为晶粒后封装而不具备载板，其特征在于包含：一导电路由层；所述导电路由层的一顶面上有一第一晶粒；所述第一晶粒通过复数条第一金属线与所述导电路由层电性连接；复数个导电球体，其位于所述导电路由层的一底面上；一模制化合物，其囊封所述导电路由层上的所述第一晶粒。
2.如权利要求1所述的矩形半导体封装，其特征在于：所述导电路由层的所述顶面上延伸复数个导电凸块。
3.如权利要求1所述的矩形半导体封装，其特征在于：所述导电路由层包含一第二晶粒，所述第二晶粒位于所述第一晶粒上方或一侧。
4.如权利要求2所述的矩形半导体封装，其特征在于：所述复数个导电凸块显露于所述模制化合物表面，为凹槽或平面显露。
5.如权利要求3所述的矩形半导体封装，其特征在于：所述第二晶粒通过所述复数个导电凸块与所述导电路由层电性连接。
6.如权利要求4所述的矩形半导体封装，其特征在于：所述第二晶粒通过复数条第二金属线与所述导电路由层电性连接。
7.如权利要求4所述的矩形半导体封装，其特征在于：所述模制化合物囊封所述第二晶粒。
8.如权利要求7所述的矩形半导体封装，其特征在于：所述模制化合物并不覆盖所述第二晶粒的一顶面。
9.一种矩形半导体封装方法，其为晶圆切割为晶粒后封装而不具备载板，其步骤包含：
步骤1：将一载体上通过线路重布技术制作一导电路由层；
步骤2：将一第一晶粒与所述导电路由层黏合固定，再通过复数条第一金属线将所述第一晶粒与所述导电路由层电性连接；
步骤3：将一模制化合物囊封所述第一晶粒；
步骤4：移除所述载体；
步骤5：将复数个导电球体与所述导电路由层接合。
10.如权利要求9所述的矩形半导体封装方法，其特征在于：步骤1时，将一载体上通过线路重布技术制作复数个导电凸块。
11.如权利要求9所述的矩形半导体封装方法，其特征在于：步骤1后，将一第二晶粒堆放于所述第一晶粒上方。
12.如权利要求9所述的矩形半导体封装方法，其特征在于：步骤1后，将一第二晶粒设置于所述第一晶粒一侧。
13.如权利要求9所述的矩形半导体封装方法，其特征在于：步骤3后，加工将所述复数个导电凸块显露于所述模制化合物表面。
14.如权利要求11或12所述的矩形半导体封装方法，其特征在于：在步骤3前，再通过复数条第二金属线将所述第二晶粒与所述导电路由层电性连接。
15.如权利要求11或12所述的矩形半导体封装方法，其特征在于：在步骤3时，将所述模制化合物囊封所述第二晶粒。
16.如权利要求13所述的矩形半导体封装方法，其特征在于：在步骤3后，一封装件堆叠于所述模制化合物上，且电性连接于所述复数个导电凸块。
CN201710669623.1A 2017-06-06 2017-08-08 矩形半导体封装及其方法 Pending CN109003958A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW106118729A TWI673839B (zh) 2017-06-06 2017-06-06 矩形半導體封裝及其方法
TW106118729 2017-06-06

Publications (1)

Publication Number Publication Date
CN109003958A true CN109003958A (zh) 2018-12-14

Family

ID=64458365

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710669623.1A Pending CN109003958A (zh) 2017-06-06 2017-08-08 矩形半导体封装及其方法

Country Status (3)

Country Link
US (1) US10269718B2 (zh)
CN (1) CN109003958A (zh)
TW (1) TWI673839B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI817496B (zh) * 2022-05-11 2023-10-01 華東科技股份有限公司 一種具絕緣板之整合封裝

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1753175A (zh) * 2004-09-24 2006-03-29 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
CN103633076A (zh) * 2013-11-21 2014-03-12 三星半导体(中国)研究开发有限公司 包封件上芯片型封装件
CN106449611A (zh) * 2015-08-11 2017-02-22 艾马克科技公司 半导体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7829984B2 (en) * 2008-06-25 2010-11-09 Stats Chippac Ltd. Integrated circuit package system stackable devices
US7799602B2 (en) * 2008-12-10 2010-09-21 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure
KR20100114421A (ko) * 2009-04-15 2010-10-25 삼성전자주식회사 적층 패키지
US8384227B2 (en) * 2010-11-16 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1753175A (zh) * 2004-09-24 2006-03-29 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
CN103633076A (zh) * 2013-11-21 2014-03-12 三星半导体(中国)研究开发有限公司 包封件上芯片型封装件
CN106449611A (zh) * 2015-08-11 2017-02-22 艾马克科技公司 半导体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI817496B (zh) * 2022-05-11 2023-10-01 華東科技股份有限公司 一種具絕緣板之整合封裝

Also Published As

Publication number Publication date
TWI673839B (zh) 2019-10-01
US20180350746A1 (en) 2018-12-06
TW201903990A (zh) 2019-01-16
US10269718B2 (en) 2019-04-23

Similar Documents

Publication Publication Date Title
CN108766940B (zh) 用于3d封装的应力补偿层
CN104520987B (zh) 具有引线键合互连且基板少的堆叠封装
US7215018B2 (en) Stacked die BGA or LGA component assembly
US7344917B2 (en) Method for packaging a semiconductor device
KR102664356B1 (ko) 칩 패키지 구조체 및 그 제조 방법
CN106169466A (zh) 半导体封装组件及其制造方法
KR20100050511A (ko) 몸체-관통 전도성 비아를 갖는 패키징된 집적 회로 장치 및 그 제조 방법
CN105261609A (zh) 半导体器件封装件、封装方法和封装的半导体器件
CN104025288A (zh) 半导体封装及其制造方法
CN108962840B (zh) 电子封装件及其制法
CN1937194A (zh) 制作叠层小片封装的方法
CN107785277B (zh) 电子封装结构及其制法
CN108074904B (zh) 电子封装件及其制法
JP2005535103A (ja) 半導体パッケージ装置ならびに製作および試験方法
US20080237833A1 (en) Multi-chip semiconductor package structure
CN109727876A (zh) 芯片封装及其形成方法
CN103107099A (zh) 半导体封装以及封装半导体器件的方法
CN104685624B (zh) 重组晶圆级微电子封装
TWI622143B (zh) 電子封裝件及其製法
KR101474189B1 (ko) 집적회로 패키지
KR101685068B1 (ko) 시스템 인 패키지 및 이의 제조방법
CN107895717A (zh) 电子封装件及其制法
CN109003958A (zh) 矩形半导体封装及其方法
US9312243B2 (en) Semiconductor packages
US20080237831A1 (en) Multi-chip semiconductor package structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20181214

RJ01 Rejection of invention patent application after publication