TW201903990A - 矩形半導體封裝及其方法 - Google Patents

矩形半導體封裝及其方法 Download PDF

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Publication number
TW201903990A
TW201903990A TW106118729A TW106118729A TW201903990A TW 201903990 A TW201903990 A TW 201903990A TW 106118729 A TW106118729 A TW 106118729A TW 106118729 A TW106118729 A TW 106118729A TW 201903990 A TW201903990 A TW 201903990A
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Taiwan
Prior art keywords
die
conductive
routing layer
package
conductive routing
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TW106118729A
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English (en)
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TWI673839B (zh
Inventor
于鴻祺
林俊榮
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華東科技股份有限公司
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Priority to TW106118729A priority Critical patent/TWI673839B/zh
Priority to US15/652,373 priority patent/US10269718B2/en
Priority to CN201710669623.1A priority patent/CN109003958A/zh
Publication of TW201903990A publication Critical patent/TW201903990A/zh
Application granted granted Critical
Publication of TWI673839B publication Critical patent/TWI673839B/zh

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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    • H01L2225/1047—Details of electrical connections between containers
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Abstract

本發明描述一種矩形半導體封裝及其方法，其為晶圓切割為晶粒後封裝不具備載板者；在一實施例中，一導電路由層之一頂面上之一第一晶粒，該第一晶粒透過複數第一金屬線與該導電路由層電性連接，複數導電球體，其位於該導電路由層之一底面上，一模製化合物，其囊封該導電路由層上之該第一晶粒；另一實施例中，由上實施例結構中增加一第二晶粒，該第二晶粒可與該第一晶粒一起囊封於該模製化合物中；又或在該模製化合物加工使包含該第二晶粒之封裝體可堆疊在該模製化合物上，並電性連接於該導電路由層。

Description

矩形半導體封裝及其方法
本發明係關於一種半導體封裝件及其製法，特別在於扇出型封裝應用於晶圓切割下之晶粒，不具備載板，而依線路重布局技術產生之導電路由層為基底。
現今在積體電路之封裝技術中，多會先將積體電路晶粒囊封於囊封材料中，爾後利用基板上之電路或基板上之構建晶圓重佈層達成產生扇出區域，藉由扇出型區域增加更多空間以用於增設更多輸出/輸入點。
隨著電子產品的功能越趨複雜，導致上游零件的晶粒須具備較多的輸出/輸入連接，配合的封裝跟著需在限制空間內引出更多的連接點，同時對很流行的堆疊式封裝(package on package，POP)應用產生挑戰，需在更小的空間內布置更多的輸出/輸入點。
從2016年iPhone7的A10處理器和天線開關模組使用扇出型晶圓級封裝(Fan-out Wafer Level Packaging，FoWLP)技術取代傳統PCB基板，透過此製程可使封裝後更薄成本更低，使得此封裝技術未來將被更多蕊片廠商採納。
關於扇出型封裝之文獻，多個專利如下：US 62/082,557揭示一種散出型晶圓級封裝及形成方法。在一實施例中，一封裝包括一第一路由層、該第一路由層之一頂面上之一第 一晶粒及囊封該第一路由層上之該第一晶粒的一第一模製化合物。第一複數個導電柱自該第一路由層之一底面延伸。一第二晶粒位於一第二路由層之一頂面上，且該第一複數個導電柱位於該路由層之該頂面上。一第二模製化合物囊封該第一模製化合物、該第一路由層、該第一複數個導電柱及該第二路由層上之該第二晶粒。在一實施例中，複數個導電凸塊(例如，焊球)自該第二路由層之一底面延伸。
TW I351088揭示一種晶圓級晶片封裝結構，包括：一晶粒其主動面上配置有複數個焊墊，一封膠體包覆晶粒之五個面、一圖案化之高分子材料層以及複數個圖案化之金屬線段覆蓋部份圖案化之高分子材料層，藉由複數個圖案化之金屬線段電性連接至每一晶粒之主動面上之複數個焊墊，其特徵在於：圖案化之高分子材料層，係於晶粒之主動面上及其外側一部份區域形成一向外延伸(fan out)之一階梯狀結構，其中向外延伸之端點處其階梯結構中具有較高之結構且在相對於晶粒之主動面之複數個焊墊處形成一孔洞，以曝露出每一焊墊；複數個圖案化之金屬線段係形成於圖案化之高分子材料層上，以使每一晶粒之主動面上之複數個焊墊與階梯狀結構之高分子材料層上之複數個圖案化之金屬線段電性連接；及一保護層，以覆蓋複數個圖案化之金屬線段及部份圖案化之高分子材料層，並曝露出階梯結構中位於較高處之圖案化之高分子材料層上之複數個圖案化之金屬線段之一表面。
TW 104139373揭示具有虛設晶粒之扇出堆疊系統級封裝(SIP)及其製造方法。一例示性封裝包含第一扇出層、該第一扇出層上方的扇出重佈層(RDL)、以及該扇出RDL上方的第二扇出層。該第一扇出層包含 一或複數第一裝置晶粒、及沿著該一或複數第一裝置晶粒的側壁延伸的第一模塑料。該第二扇出層包含接合至扇出RDL的一或複數個裝置晶粒、接合至該扇出RDL的虛設晶粒、及沿著該一或複數第二裝置晶粒與該虛設晶粒之側壁延伸的第二模塑料。該扇出RDL將該一或複數第一裝置晶粒電性連接至該一或複數第二裝置晶粒，且該虛設晶粒質質上未具有任何有源裝置；依以上改善因質材不同產生的封裝翹曲。
TW I298193揭示一種半導體構裝元件，包括具有一凹槽(cavity)或溝槽(slot)於一載板上。至少一具有背面(back surface)及包括第一銲墊(bonding pads)之主動面(active surface)的晶片，此晶片固定於凹槽中，並暴露出其主動面。一第一絕緣層於載板與主動面上，其包括第一導電通孔穿透其中，並連接第一銲墊。一多層結構於第一絕緣層上，其包含佈局導線、第二導電通孔於其中，及至少一第二絕緣層於其上，並暴露出錫球銲墊(ball pad)於多層結構上。其中佈局導線、第二導電通孔及錫球銲墊與第一導電通孔有電性上的連接。錫球(solder ball)則是固定於錫球銲墊上。如此的架構整合一般覆晶構裝製程中的重新分布與接腳間距擴散(fan-out)製程，簡化了覆晶球柵陣列現有製程。
US 6770959B2揭示無載板的半導體封裝及其製造方法包括提供在選定位置具有被焊接區域的前表面的臨時載板。未被焊接區域覆蓋的前表面形成有多個引線層和管芯焊盤層。芯片焊盤層的頂側附著在芯片上。芯片和引線層通過多根接合線電連接。芯片、接合線、焊接區域、引線層和芯片焊盤層被模製樹脂覆蓋。在封裝被單獨化之後，通過蝕刻去除臨時載板以形成沒有載板的半導體封裝。
然而，此扇出型晶圓級封裝技術因需在晶圓型態下加工製作，使後段封裝業者面臨巨大壓力，且在晶粒元件下如何達成類似效果也需考慮未來各種可能。
有鑑於以上問題，本發明提供一種矩形半導體封裝及其方法，主要利用現今扇出型封裝應用於晶圓切割下之晶粒，以達成扇出型晶圓級封裝特性。
因此，本發明之主要目的係在提供一種矩形半導體封裝及其方法，具備不需要載板以降低封裝厚度及成本之特性。
本發明再一目的係在提供一種矩形半導體封裝及其方法，將現今扇出型晶圓級製程轉化為扇出型晶粒級製程。
本發明再一目的係在提供一種矩形半導體封裝及其方法，可依扇出型封裝來提高晶粒封裝後之導通輸出輸入點。
本發明再一目的係在提供一種矩形半導體封裝及其方法，因封裝後變薄，在現今記憶體產品中更可增加多層堆加轉而增加容量。
本發明再一目的係在提供一種矩形半導體封裝及其方法，憑藉晶粒級後加工封裝，可提升小廠採購及製程變化性。
為達成上述目地，本發明所使用的主要技術手段是採用以下技術方案來實現的。本發明為一種矩形半導體封裝，其為晶圓切割為晶粒後封裝不具備載板者，其包含：一導電路由層；該導電路由層之一頂面上之一第一晶粒；該第一晶粒透過複數第一金屬線與該導電路由層電性連接；複數導電球體，其位於該導電路由層之一底面上；一模製化合物，其 囊封該導電路由層上之該第一晶粒。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
前述的封裝，其中該導電路由層之該頂面上延伸複數導電凸塊。
前述的封裝，其包含一第二晶粒，其位於該第一晶粒上方或一側。
前述的封裝，其中該複數導電凸塊顯露模製化合物表面，可為凹槽或平面顯露。
前述的封裝，其中該第二晶粒，透過該複數導電凸塊與該導電路由層電性連接。
前述的封裝，其中該第二晶粒，透過複數第二金屬線與該導電路由層電性連接。
前述的封裝，其中該模製化合物囊封該第二晶粒。
前述的封裝，其中該模製化合物並不覆蓋該第二晶粒之一頂面。
為達成上述目地，本發明所使用的再依主要技術手段是採用以下技術方案來實現的。本發明為一種矩形半導體封裝方法，其為晶圓切割為晶粒後封裝不具備載板者，其步驟包含：步驟1：將一載體上透過線路重佈技術製作一導電路由層；步驟2：將一第一晶粒與該導電路由層黏合固定，再透過複數第一金屬線將該第一晶粒與該導電路由層電性連接；步驟3：將一模製化合物囊封該第一晶粒；步驟4：移除該載體；步驟5：並將複 數導電球體與該導電路由層接合。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
前述的方法，其中步驟1時，將一載體上透過線路重佈技術製作複數導電凸塊。
前述的方法，其中步驟1後，將一第二晶粒堆放於該第一晶粒上方。
前述的方法，其中步驟1後，將一第二晶粒設置於該第一晶粒一側。
前述的方法，其中步驟3後，加工將該複數導電凸塊顯露於該模製化合物表面。
前述的方法，其中步驟3前，再透過複數第二金屬線將該第二晶粒與該導電路由層電性連接。
前述的方法，其中步驟3時，將該模製化合物囊封該第二晶粒。
前述的方法，其中步驟3後，一封裝件堆疊於該模製化合物上，且電性連接於該複數導電凸塊。
相較於習知技術，本發明具有功效在於：(1)利用導電路由層取代電路板；(2)藉由移除載板以降低封裝厚度及成本；(3)憑藉在晶圓廠外實行扇出型封裝加工增進堆疊式封裝變化性。
1‧‧‧載體
10‧‧‧導電路由層
11‧‧‧頂面
12‧‧‧導電凸塊
13‧‧‧底面
14‧‧‧第一金屬線
141‧‧‧第二金屬線
15‧‧‧導電球體
20‧‧‧第一晶粒
30‧‧‧第二晶粒
40‧‧‧模製化合物
51‧‧‧步驟1
511‧‧‧步驟1-1
52‧‧‧步驟2
521‧‧‧步驟2-1
521a‧‧‧步驟2-1a
522‧‧‧步驟2-2
53‧‧‧步驟3
531‧‧‧步驟3-1
532‧‧‧步驟3-2
533‧‧‧步驟3-3
54‧‧‧步驟4
55‧‧‧步驟5
第1圖為本發明最佳實施型態之載體示意圖； 第2a圖為本發明最佳實施型態之第一增生導電路由層示意圖；第2b圖為本發明最佳實施型態之第二增生導電路由層示意圖；第3a圖為本發明最佳實施型態之第一金屬線連接晶粒示意圖；第3b圖為本發明最佳實施型態之第二金屬線連接晶粒示意圖；第3c圖為本發明最佳實施型態之第三金屬線連接晶粒示意圖；第3d圖為本發明最佳實施型態之第四金屬線連接晶粒示意圖；第3e圖為本發明最佳實施型態之第五金屬線連接晶粒示意圖；第4a圖為本發明最佳實施型態之第一封裝示意圖；第4b圖為本發明最佳實施型態之第二封裝示意圖；第4c圖為本發明最佳實施型態之第三封裝示意圖；第4d圖為本發明最佳實施型態之第四封裝示意圖；第4e圖為本發明最佳實施型態之第五封裝示意圖；第5a圖為本發明最佳實施型態之第一移除載體示意圖；第5b圖為本發明最佳實施型態之第二移除載體示意圖；第5c圖為本發明最佳實施型態之第三移除載體示意圖； 第6a圖為本發明最佳實施型態之第一增加導電球體示意圖；第6b圖為本發明最佳實施型態之第一加工示意圖；第6c圖為本發明最佳實施型態之第二增加導電球體示意圖；第6d圖為本發明最佳實施型態之第二加工示意圖；第6e圖為本發明最佳實施型態之第三增加導電球體示意圖；第7a圖為本發明最佳實施型態之第一封裝堆疊示意圖；第7b圖為本發明最佳實施型態之第二封裝堆疊示意圖；第8a圖為本發明最佳實施型態之第一結構示意圖；第8b圖為本發明最佳實施型態之第二結構示意圖；第8c圖為本發明最佳實施型態之第三結構示意圖；第8d圖為本發明最佳實施型態之第四結構示意圖；第9圖為本發明最佳實施型態之第一流程圖；第10a圖為本發明最佳實施型態之第二流程圖；第10b圖為本發明最佳實施型態之第三流程圖；第11圖為本發明最佳實施型態之第四流程圖；第12圖為本發明最佳實施型態之第五流程圖。
為了讓本發明之目的、特徵與功效更明顯易懂，以下特別列舉本發明之較佳實施型態： 如第1、2a、3a、4a、5a、6a、8a及9圖所示，為本發明一種矩形半導體封裝及其方法之第一實施型態；請先參考第8a圖所示，一導電路由層(10)；該導電路由層(10)之一頂面(11)上之一第一晶粒(20)；該第一晶粒(20)透過複數第一金屬線(14)與該導電路由層(10)電性連接；複數導電球體(15)，其位於該導電路由層(10)之一底面(13)上；一模製化合物(40)，其囊封該導電路由層(10)上之該第一晶粒(20)。
具體而言，該導電路由層(10)係指藉由重分佈製程(Redistribution Layer，RDL)是將原設計的IC線路接點位置(I/O pad)，透過晶圓級金屬佈線製程或凸塊製程來改變其接點位置，使IC能應用於不同的元件模組，在此強調由金屬建構的導電層；該第一晶粒(20)是指晶粒(Die)是以半導體材料製作而成未經封裝的一小塊積體電路本體，主要來源為由晶圓切割分離；其中，第一金屬線(14)實為打線接合(Wire bonding)的金屬線材，是利用線徑15-50微米的金屬線材將晶粒(Chip)及導線架(Lead Frame)連接起來的技術，使微小的晶片得以與外面的電路做溝通，而不需要增加太多的面積；另，導電球體(15)現今實務上為錫球(Solder Ball)功效為提供該導電路由層(10)與外界的電性連接；該模製化合物(40)為半導體封裝材料，一般使用高分子樹脂作為電子元件及晶粒(Chip)的封裝材料。
請再參閱第9圖所示，其中步驟1(51)為將一載體(1)上透過線路重佈技術製作一導電路由層(10)；請看第1及2a圖，在第1圖中為單純的載體(1)，經由重分佈製程(Redistribution Layer，RDL)在第2b圖中生成導電路由層(10)。
跟著，再參閱第9圖所示，其中步驟2(52)為將一第一晶粒(20)與該導電路由層(10)黏合固定，再透過複數第一金屬線(14)將該第一晶粒(20)與該導電路由層(10)電性連接；請看2a及3a圖表示，先將第一晶粒(20)透過黏合固定在導電路由層(10)上，再透過打線接合技術將複數第一金屬線(14)固定於導電路由層(10)之頂面(11)和第一晶粒(20)間，達成兩者電性導通。
再，參閱第9圖所示，其中步驟3(53)為將一模製化合物(40)囊封該第一晶粒(20)；請看3a及4a圖表示，使用模具將高分子樹脂貫注於導電路由層(10)上，將第一金屬線(14)與第一晶粒(20)包覆。
接著，參閱第9圖所示，其中步驟4(54)為移除該載體(1)；請看4a及5a圖表示，經由製具將載體(1)移除，使導電路由層(10)底層顯露於外。
最後，參閱第9圖所示，其中步驟5(55)為並將複數導電球體(15)與該導電路由層(10)接合；請看5a及6a圖表示，將導電球體(15)黏接於導電路由層(10)底層，以便後續製程電性連接該第一晶粒(20)。
請再參照第第1、2a、3c、4c、5b、6c、8b及10a圖所示，為本發明一種矩形半導體封裝及其方法之第二實施型態；第二實施型態與第一實施型態的主要差異在於本實施型態增加第二金屬線(141)及第二晶粒(30)；請先參考第8b圖所示，在該第一晶粒(20)上方具有一第二晶粒(30)，該第二晶粒(30)，透過複數第二金屬線(141)與該導電路由層(10)電性連接。
具體而言，該第二晶粒(30)是指晶粒(Die)是以半導體 材料製作而成未經封裝的一小塊積體電路本體，主要來源為由晶圓切割分離；其中，第二金屬線(141)實為打線接合(Wire bonding)的金屬線材，是利用線徑15-50微米的金屬線材將晶粒(Chip)及導線架(Lead Frame)連接起來的技術，使微小的晶片得以與外面的電路做溝通，而不需要增加太多的面積。
請再參閱第10a圖所示，其中步驟1(51)至步驟2(52)與第一實施型態完全一致；接著，第10a圖之步驟2-1(521)為將一第二晶粒(30)堆放於該第一晶粒(20)上方；接續步驟2-2(522)為再透過複數第二金屬線(141)將該第二晶粒(30)與該導電路由層(10)電性連接；見第3c圖所示，將第二晶粒(30)黏貼固定於第一晶粒(20)上方，再透過打線接合技術將複數第二金屬線(141)固定於導電路由層(10)之頂面(11)和第二晶粒(30)間，達成兩者電性導通；其中，步驟2(52)、步驟2-1(521)及步驟2-2(522)三者，可先堆疊第一晶粒(20)及第二晶粒(30)，再打線；再，步驟2(52)、步驟2-1(521)及步驟2-2(522)三者，可先堆疊第一晶粒(20)及打線後，再堆疊第二晶粒(30)及打線。
再，參閱第10a圖所示，其中步驟3(53)同時實行步驟3-2(532)將為將一模製化合物(40)囊封該第二晶粒(20)；請看3c及4c圖表示，使用模具將高分子樹脂貫注於導電路由層(10)上，將第一金屬線(14)、第一晶粒(20)、第二金屬線(141)與第二晶粒(30)包覆。
最後，再參閱第10a圖所示，其中步驟4(54)至步驟5(55)與第一實施型態完全一致。
本第二實施型態，另可如第8d圖所示，不具備步驟2-2(522) 之複數第二金屬線(141)，並使該模製化合物(40)並不覆蓋該第二晶粒(30)之一頂面；具體而言，此時該第二晶粒(30)為不具電子功能，主要功效防止封裝後變形的扶助封裝材料。
請再參照第1、2a、3e、4e、5c、6e及10b圖所示，為本發明一種矩形半導體封裝及其方法之第三實施型態；第三實施型態與第二實施型態的主要差異在於本實施型態第二晶粒(30)位於第一晶粒(20)一側，而非上方；請先參考第6e圖所示，在該第一晶粒(20)一側具有一第二晶粒(30)，該第二晶粒(30)，透過複數第二金屬線(141)與該導電路由層(10)電性連接。
請再參閱第10b圖所示，其中步驟1(51)至步驟2(52)與第二實施型態完全一致；接著，第10b圖之步驟2-1a(521a)為將一第二晶粒(30)設置於該第一晶粒(20)一側；接續步驟2-2(522)為再透過複數第二金屬線(141)將該第二晶粒(30)與該導電路由層(10)電性連接；見第3e圖所示，將第二晶粒(30)黏貼固定於第一晶粒(20)一側，再透過打線接合技術將複數第二金屬線(141)固定於導電路由層(10)之頂面(11)和第二晶粒(30)間，達成兩者電性導通；其中，步驟2(52)、步驟2-1a(521a)及步驟2-2(522)三者，可先分別設置第一晶粒(20)及第二晶粒(30)，再打線；再，步驟2(52)、步驟2-1a(521a)及步驟2-2(522)三者，可先設置第一晶粒(20)及打線後，再設置第二晶粒(30)及打線。
再，參閱第10b圖所示，其中步驟3(53)同時實行步驟3-2(532)將為將一模製化合物(40)囊封該第二晶粒(20)；請看3e及4e圖表示，使用模具將高分子樹脂貫注於導電路由層(10)上，將第一金屬線(14)、 第一晶粒(20)、第二金屬線(141)與第二晶粒(30)包覆。
最後，再參閱第10b圖所示，其中步驟4(54)至步驟5(55)與第二實施型態完全一致。
請再參照第1、2b、3b、4b、6b、7a及11圖所示，為本發明一種矩形半導體封裝及其方法之第四實施型態；第四實施型態與第一實施型態的主要差異在於本實施型態增加導電凸塊(12)及另一封裝件；請先參考第7a圖所示，在模製化合物(40)上方堆疊另一封裝件。
請再參閱第11圖所示，其中步驟1(51)至步驟3(53)與第一實施型態完全一致；首先，第11圖之步驟1(51)同時實行步驟1-1(511)，步驟1-1(511)為將一載體(1)上透過線路重佈技術製作複數導電凸塊(12)，呈現如第2b圖所示；步驟2(52)時呈現如第3b圖所示；步驟3(53)時呈現如第4b圖所示。
接著，參閱第11圖所示，在步驟3(53)後實行步驟3-1(531)，該步驟3-1(531)與第6b圖為加工將該複數導電凸塊(12)顯露於該模製化合物(40)表面；此步驟3-1(531)目的為將可再電性連接導電路由層(10)的導電凸塊(12)顯露於外，以方便後加工。
再，參閱第11圖所示，在步驟3-1(531)後實行步驟3-3(533)，該步驟3-3(533)與第7a圖為一封裝件堆疊於該模製化合物(40)上，且電性連接於該複數導電凸塊(12)；此步驟3-3(533)目的為將封裝具備其他功能之晶粒透過導電路由層(10)電性連接外部。
本第四實施型態，另可如第8c圖所示，該第二晶粒(30)，透過該複數導電凸塊(12)與該導電路由層(10)電性連接。
請再參照第1、2b、3b、4d、6d、7b及12圖所示，為本發明一種矩形半導體封裝及其方法之第五實施型態；第五實施型態為第二實施型態及第四實施型態整合後型態。
請再參閱第12圖所示，其中步驟1(51)為將一載體(1)上透過線路重佈技術製作一導電路由層(10)；請看第1及2b圖，在第1圖中為單純的載體(1)，經由重分佈製程(Redistribution Layer，RDL)在第2b圖中生成導電路由層(10)。
同時，實行第12圖之步驟1-1(511)，步驟1-1(511)為將一載體(1)上透過線路重佈技術製作複數導電凸塊(12)，呈現如第2b圖所示。
跟著，再參閱第12圖所示，其中步驟2(52)為將一第一晶粒(20)與該導電路由層(10)黏合固定，再透過複數第一金屬線(14)將該第一晶粒(20)與該導電路由層(10)電性連接；請看2b及3b圖表示，先將第一晶粒(20)透過黏合固定在導電路由層(10)上，再透過打線接合技術將複數第一金屬線(14)固定於導電路由層(10)之頂面(11)和第一晶粒(20)間，達成兩者電性導通。
接著，第12圖之步驟2-1(521)為將一第二晶粒(30)堆放於該第一晶粒(20)上方；接續步驟2-2(522)為再透過複數第二金屬線(141)將該第二晶粒(30)與該導電路由層(10)電性連接；見第3d圖所示，將第二晶粒(30)黏貼固定於第一晶粒(20)上方，再透過打線接合技術將複數第二金屬線(141)固定於導電路由層(10)之頂面(11)和第二晶粒(30)間，達成兩者電性導通；其中，步驟2(52)、步驟2-1(521)及步驟 2-2(522)三者，可先堆疊第一晶粒(20)及第二晶粒(30)，再打線；再，步驟2(52)、步驟2-1(521)及步驟2-2(522)三者，可先堆疊第一晶粒(20)及打線後，再堆疊第二晶粒(30)及打線。
再，參閱第12圖所示，其中步驟3(53)同時實行步驟3-2(532)將為將一模製化合物(40)囊封該第二晶粒(20)；請看3d及4d圖表示，使用模具將高分子樹脂貫注於導電路由層(10)上，將第一金屬線(14)、第一晶粒(20)、第二金屬線(141)與第二晶粒(30)包覆。
跟著，參閱第12圖所示，在步驟3(53)後實行步驟3-1(531)，該步驟3-1(531)與第6d圖為加工將該複數導電凸塊(12)顯露於該模製化合物(40)表面；此步驟3-1(531)目的為將可再電性連接導電路由層(10)的導電凸塊(12)顯露於外，以方便後加工。
又，參閱第12圖所示，在步驟3-1(531)後實行步驟3-3(533)，該步驟3-3(533)與第7b圖為一封裝件堆疊於該模製化合物(40)上，且電性連接於該複數導電凸塊(12)；此步驟3-3(533)目的為將封裝具備其他功能之晶粒透過導電路由層(10)電性連接外部。
接著，參閱第12圖所示，其中步驟4(54)為移除該載體(1)；請看4d圖表示，經由製具將載體(1)移除，使導電路由層(10)底層顯露於外。
最後，參閱第12圖所示，其中步驟5(55)為並將複數導電球體(15)與該導電路由層(10)接合；請看6d圖表示，將導電球體(15)黏接於導電路由層(10)底層，以便後續製程電性連接該第一晶粒(20)。
因此本發明之功效有別一般半導體封裝結構，此於半導體封 裝當中實屬首創，符合發明專利要件，爰依法俱文提出申請。
惟，需再次重申，以上所述者僅為本發明之較佳實施型態，舉凡應用本發明說明書、申請專利範圍或圖式所為之等效變化，仍屬本發明所保護之技術範疇，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (16)

  1. 一種矩形半導體封裝，其為晶圓切割為晶粒後封裝不具備載板者，其包含：一導電路由層；該導電路由層之一頂面上之一第一晶粒；該第一晶粒透過複數第一金屬線與該導電路由層電性連接；複數導電球體，其位於該導電路由層之一底面上；一模製化合物，其囊封該導電路由層上之該第一晶粒。
  2. 如請求項1之封裝，其中該導電路由層之該頂面上延伸複數導電凸塊
  3. 如請求項1之封裝，其包含一第二晶粒，其位於該第一晶粒上方或一側。
  4. 如請求項2之封裝，其中該複數導電凸塊顯露模製化合物表面，可為凹槽或平面顯露。
  5. 如請求項3之封裝，其中該第二晶粒，透過該複數導電凸塊與該導電路由層電性連接。
  6. 如請求項4之封裝，其中該第二晶粒，透過複數第二金屬線與該導電路由層電性連接。
  7. 如請求項4之封裝，其中該模製化合物囊封該第二晶粒。
  8. 如請求項7之封裝，其中該模製化合物並不覆蓋該第二晶粒之一頂面。
  9. 一種矩形半導體封裝方法，其為晶圓切割為晶粒後封裝不具備載板者，其步驟包含：步驟1：將一載體上透過線路重佈技術製作一導電路由層；步驟2：將一第一晶粒與該導電路由層黏合固定，再透過複數第一金 屬線將該第一晶粒與該導電路由層電性連接；步驟3：將一模製化合物囊封該第一晶粒；步驟4：移除該載體；步驟5：並將複數導電球體與該導電路由層接合。
  10. 如請求項9之方法，其中步驟1時，將一載體上透過線路重佈技術製作複數導電凸塊
  11. 如請求項9之方法，其中步驟1後，將一第二晶粒堆放於該第一晶粒上方。
  12. 如請求項9之方法，其中步驟1後，將一第二晶粒設置於該第一晶粒一側。
  13. 如請求項9之方法，其中步驟3後，加工將該複數導電凸塊顯露於該模製化合物表面。
  14. 如請求項11或12之方法，其中步驟3前，再透過複數第二金屬線將該第二晶粒與該導電路由層電性連接。
  15. 如請求項11或12之方法，其中步驟3時，將該模製化合物囊封該第二晶粒。
  16. 如請求項13之方法，其中步驟3後，一封裝件堆疊於該模製化合物上，且電性連接於該複數導電凸塊。
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