TWI464812B - 具有倒裝晶片之積體電路封裝件系統 - Google Patents

具有倒裝晶片之積體電路封裝件系統 Download PDF

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Publication number
TWI464812B
TWI464812B TW097144814A TW97144814A TWI464812B TW I464812 B TWI464812 B TW I464812B TW 097144814 A TW097144814 A TW 097144814A TW 97144814 A TW97144814 A TW 97144814A TW I464812 B TWI464812 B TW I464812B
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Taiwan
Prior art keywords
flip chip
carrier
substrate
integrated circuit
attached
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TW097144814A
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English (en)
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TW200933766A (en
Inventor
Soo-San Park
Bumjoon Hong
Sang-Ho Lee
Jong-Woo Ha
Daesik Choi
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Stats Chippac Ltd
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Publication of TW200933766A publication Critical patent/TW200933766A/zh
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Publication of TWI464812B publication Critical patent/TWI464812B/zh

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Description

具有倒裝晶片之積體電路封裝件系統
本發明係關於一種積體電路封裝件系統，且詳言之，係關於一種具有倒裝晶片之積體電路封裝件系統。
元件之更加小型化(miniaturization)、積體電路(IC)之更大封裝密度、高效率與低成本為電腦工業之持續的目標。半導體封裝件結構持續進展到朝向小型化、增加在此封裝之元件密度，且同時降低從其製造出的產品尺寸。這對於資訊和通訊產品之持續增加的需求之回應而持續增加效率之外更持續降低尺寸、厚度以及成本。
對於小型化的日增需要尤其值得注意，例如為行動電話、免持行動電話聽筒、個人資料助理(PDA)、攝錄影機、筆記型電腦等之可攜式資訊和通訊裝置。所有這些裝置持續製造的更小和更薄以改善其可攜性。因此，被納入在這些裝置中的大型積體電路(LSI)封裝件需要製造的更小和更薄。包覆並保護LSI的封裝件組態也需要製造的更小和更薄。
許多習知的半導體(或晶片)封裝件為半導體晶粒(die)被模製為具有樹脂(如環氧模製化合物)之封裝件的類型。封裝件具有導線架(lead frame)，其導腳(lead)從封裝件本體突伸以提供在晶粒和外部裝置之間的訊號傳送路徑。其它習知封裝件組態為具有接觸終端或接觸墊直接形成在封裝件的表面上。這樣的習知半導體封裝件係透過以下過程所製造：晶粒接合(die-bonding)製程(將半導體晶粒安置在導線架的晶墊(paddle)上)、打線接合(wire-bonding)製程(使用導線架焊線將在晶墊上的半導體晶粒電性連接到內部導腳)、模製(molding)製程(以環氧樹脂包覆(encapsulate)組件的預定部分，包含晶粒、內部導腳以及導線架焊線，以形成封裝件本體)以及修整(trimming)製程(完成作為個別獨立的封裝件之各組件)。
因此，已製造的半導體封裝件隨後藉由匹配和焊接其外部導腳或接觸墊而安置至電路板上之匹配圖案，藉此致能於封裝件中的半導體裝置和電路板之間的電源和訊號輸入/輸出(I/O)操作。
對於改善封裝需求之回應，許多創新的封裝件設計已被構想出且帶來市場。多晶片模組已達成在減少由現代電子學所用的板空間中之重要角色。然而，無論是垂直或水平排列之多晶片模組也存有問題，因為他們通常必須在元件晶片和晶片連接可被測試前進行組合。即是，因為在晶粒上之電子接合墊太小，於是將組件放在基材上之前測試晶粒是困難的。因此，當晶粒個別安置或連接時，晶粒和連接可以各自被測試，且僅已知良好晶粒(known-good-die,KGD)為無缺陷且隨後被組合為較大電路。使用KGD之製造製程因此更為可靠且較少會因壞晶粒而導致組件缺陷。然而，在習知多晶片模組中，在最終組合之前，晶粒不能單獨地被辨識為KGD，因而導致KGD無效率和組合製程產量問題。
許多的封裝件方法係堆疊多積體電路封裝件晶粒或內嵌封裝件(package inpackage；PIP)或其組合。其他方法包含封裝件層級堆疊或是層疊封裝件(package on package；POP)。兩者概念包含兩個或更多封裝件之堆疊。由於每個封裝件可以在組合前測試，允許KGD用在組合堆疊，因此KGD和組合製程產量並非為問題。在這些方法之中，倒裝晶片已經為工業之重要標的，因為其通常需要小空間與少量的處理步驟。然而，所有目前的封裝件方法仍是未能提供彈性支援不同整合和前揭以一個或更多個倒裝晶片所包含之堆疊選擇。
因此，仍然具有對積體電路封裝件系統提供低成本製造、改善產量、降低積體電路封裝件尺寸以及彈性堆疊與整合組態之需求。有鑑於節省成本與改善效率之日益增加的需求，察覺這些問題之解答變得越來越關鍵。
對於這些問題的解決方案已經經過長久的尋找，但先前的發展並未教示或建議任何解決方案，且因此對於這些問題的解決方案已長久的困惑所屬技術領域中具有通常知識者。
一種積體電路封裝方法，包含：於承載件之上設置倒裝晶片，且該倒裝晶片的非主動側係面對該承載件；於該倒裝晶片之上設置基材；於該倒裝晶片和該承載件之間連接內部互連；以及，於該承載件之上包覆該倒裝晶片和該內部互連，並露出該基材。
本發明的一些實施例具有除了上述的那些之外或取代上述的那些的其他態樣。所屬技術領域中具有通常知識者在參照所附圖式而閱讀下列詳細描述時，這些態樣將變得明顯。
以下實施例係充分詳細描述以使所屬技術領域中具通常知識者可製造及使用本發明。要理解的是，其他實施例依此揭露可明瞭，而且其系統、製程或機構上的改變可在未悖離本發明之範疇而製造。
於下列敘述中，係給定多個詳細說明以提供本發明之完整瞭解。然而，顯而易見的，本發明可不需要這些詳細說明而實施。為避免模糊本發明，一些已知的電路、系統組構及製程步驟未詳細地揭露。同樣地，該系統之實施例之該些圖式的顯示係為半概略的(semi-diagrammatic)且未依比例，且特別地，一些尺寸為清楚呈現本發明而誇大地顯示於圖式中。一般而言，本發明可以在任何方位操作。
另外，在多個實施例中揭露及描述某些共同特徵，為清楚及容易說明、描述及理解，彼此相似及相同特徵將一般以相同元件符號來描述。這些實施例被編號為第一實施例、第二實施例等以方便描述，而並非具有任何其他含意或是對本發明提供限制。
為說明的原因，在此使用的用語“水平(horizontal)”係定義為平行該積體電路的平面或表面之平面而不論其方位。用語“垂直(vertical)”係指垂直剛定義的“水平”之方向。例如“在…上面(above)”、“在…下面(below)”、“底部(bottom)”、“頂部(top)”、“側邊”(如在“側壁”)、“較高(higher)”、“較低(lower)”、“上面的(upper)”、“覆於…上(over)”以及“在…之下(under)”之用語，係相對該水平平面而定義。用語“在…上(on)”係指在元件間有直接接觸。在此使用的用語“處理(processing)”係包含材料的沉積、圖案化、曝光、顯影、蝕刻、清潔、模製，以及/或材料的移除或形成上述結構所需之要求。在此使用的用語“系統(system)”意指且係指依照使用該用語的上下文的本發明之方法及設備。
現參照第1圖，係顯示於本發明的第一實施例中之積體電路封裝件系統100的上視圖。該上視圖描繪出封裝件包覆體102(如環氧模製化合物)以及基材104(如層壓基材(laminated substrate))，而接觸墊106從該封裝件包覆體102中露出。
為了說明目的，該積體電路封裝件系統100係以具有相同間隔之該接觸墊106而顯示。雖然要瞭解到該積體電路封裝件系統100可以減少一些位置的東西以使該積體電路封裝件系統100可以具有非相同間隔的該接觸墊106。
現參照第2圖，係顯示沿著第1圖之2--2線之該積體電路封裝件系統100之剖面圖。該剖面圖描繪出倒裝晶片10藉著黏著劑(adhesive)214(如黏晶接著劑(die-attach adhesive))安置於承載件(carrier)212(如層壓基材)之上，且該基材104安置在該倒裝晶片210之上。該封裝件包覆體102覆蓋於該承載件212之上的該倒裝晶片210而露出該基材104。
該基材104包含於該基材104的頂部側216和該基材104的底部側218兩側處之該接觸墊106。於該基材104的該頂部側216處之該接觸墊106係從該封裝件包覆體102中露出。該封裝件包覆體102與該基材104的該頂部側216為共平面。該倒裝晶片210具有非主動側220及主動側222，其中，該主動側222包含在其上製造的主動電路。於此例子中，該非主動側220較佳為面對該承載件212。第一傳導凸塊(conductive bump)224連接到於該基材104的該底部側218處的該接觸墊106以及該倒裝晶片210的該主動側222。如黏著劑的填膠(underfill)226可以在該基材104和圍繞該第一傳導凸塊224的該主動側222之間。
內部互連228(如接合焊線或帶狀接合焊線)可以連接在於該倒裝晶片210的該主動側222上的接合墊230和該承載件212之間。該封裝件包覆體102亦會覆蓋該內部互連228。外部互連232(如錫球)可以附接至該承載件212下面以連接到如印刷電路板或另一積體電路封裝件系統之下一系統層級(未顯示)。
可發現到，本發明提供雙重連接為從該封裝件包覆體露出的基材並與於該封裝件包覆體中的該倒裝晶片連接。該倒裝晶片以該傳導凸塊連接至該基材並以該內部互連連接至該承載件而提供了低成本以及用以使其他積體電路裝置和電子組件安置在該基材上的可靠方法。
也可以發現到，於本發明中，在該積體電路封裝件系統之後續製造製程之前，該基材和該倒裝晶片可以組合並以封裝件測試。此項特徵可進一步減少製造成本和增加可靠度。
現參照第3圖，係顯示本發明之第二實施例中之沿著第1圖之2--2線的積體電路封裝件系統300之剖面圖。第1圖的積體電路封裝件系統100的上視圖也可以代表該積體電路封裝件系統300的上視圖。該剖面圖繪示第一倒裝晶片310安置在承載件312(如層壓基材)之上以及基材304(如層壓基材)安置在該第一倒裝晶片310之上。封裝件包覆體302(如環氧模製化合物)覆蓋於該承載件312之上的該第一倒裝晶片310而露出該基材304。
該基材304包含於該基材304的頂部側316和該基材304的底部側318兩側處之該接觸墊306。於該基材304的該頂部側316處之該接觸墊306從該封裝件包覆體302中露出。該封裝件包覆體302與該基材304的該頂部側316為共平面。該第一倒裝晶片310具有第一非主動側320及第一主動側322，其中，該第一主動側322包含在其上製造的主動電路。於此例子中，該第一非主動側320較佳為面對該承載件312。第一傳導凸塊324可連接到於該基材304的該底部側318處的該接觸墊306以及該第一倒裝晶片310的該第一主動側322。如黏著劑的填膠326可以在該基材304和圍繞該第一傳導凸塊324的該第一主動側322之間。
在該第一倒裝晶片310和該承載件312之間，第二倒裝晶片334安置在該承載件312之上。該第二倒裝晶片334具有第二非主動側336和第二主動側338，其中，該第二主動側338包含在其上製造的主動電路。於此例子中，該第二主動側338較佳為面對該承載件312。第二傳導凸塊340可連接到於該承載件312和該第二倒裝晶片334的該第二主動側338。
內部互連328(如接合焊線或帶狀接合焊線)連接在於該第一倒裝晶片310的該第一主動側322處的接合墊330與該承載件312之間。外部互連332(如錫球)可以附接至該承載件312下以連接到如印刷電路板或另一積體電路封裝件系統之下一系統層級(未顯示)。
現參照第4圖，係顯示本發明之第三實施例中之沿著第1圖之2--2線的積體電路封裝件系統400之剖面圖。第1圖的積體電路封裝件系統100的上視圖也可以代表該積體電路封裝件系統400的上視圖。該剖面圖繪示倒裝晶片410安置在承載件412(如層壓基材)之上以及基材404(如層壓基材)安置在該倒裝晶片410之上。封裝件包覆體402(如環氧模製化合物)覆蓋於該承載件412之上的該倒裝晶片410而露出該基材404。
該基材404包含於該基材404的頂部側416和該基材404的底部側418兩側處之該接觸墊406。於該基材404的該頂部側416處之該接觸墊406從該封裝件包覆體402中露出。該封裝件包覆體402與該基材404的該頂部側416為共平面。該倒裝晶片410包含第一非主動側420及第一主動側422，其中，該第一主動側422包含在其上製造的主動電路。於此例子中，該第一非主動側420較佳為面對該承載件412。第一傳導凸塊424連接到於該基材404的該底部側418處的該接觸墊406以及該倒裝晶片410的該第一主動側422。
在該倒裝晶片410和該承載件412之間，積體電路裝置(如積體電路晶粒)442可以安置在該承載件412之上。該積體電路裝置442包含第二非主動側436和第二主動側438，其中，該第二主動側438包含在其上製造的主動電路以及接合墊444。於此例子中，該第二非主動側436較佳為面對該承載件412。
內部互連428(如接合焊線或帶狀接合焊線)連接在該承載件412和該積體電路裝置442的該接合墊444之間。該內部互連428也連接到於該倒裝晶片410的該第一主動側422處的接合墊430與該承載件412之間。外部互連432(如錫球)附接至該承載件412下面以連接到如印刷電路板或另一積體電路封裝件系統之下一系統層級(未顯示)。
現參照第5圖，係顯示本發明之第四實施例中之沿著第1圖之2--2線的積體電路封裝件系統500之剖面圖。第1圖的積體電路封裝件系統100的上視圖也可以代表該積體電路封裝件系統500的上視圖。該剖面圖繪示倒裝晶片510安置在承載件512(如層壓基材)之上以及基材504(如層壓基材)安置在該倒裝晶片510之上。封裝件包覆體502(如環氧模製化合物)覆蓋於該承載件512之上的該倒裝晶片510而露出該基材504。
該基材504包含於該基材504的頂部側516和該基材504的底部側518兩側處之該接觸墊506。於該基材504的該頂部側516處之該接觸墊506從該封裝件包覆體502中露出。該封裝件包覆體502與該基材504的該頂部側516為共平面。該倒裝晶片510具有非主動側520及主動側522，其中，該主動側522包含在其上製造的主動電路。於此例子中，該非主動側520較佳為面對該承載件512。第一傳導凸塊524連接到於該基材504的該底部側518處的該接觸墊506以及該倒裝晶片510的該主動側522。
在該倒裝晶片510和該承載件512之間，傳導屏蔽(如電磁干擾(EMI)屏蔽)558可以安置在該承載件512之上。該傳導屏蔽558可以透過該承載件512連接到接地源(ground source)。該傳導屏蔽558可以在該倒裝晶片510和電子組件(未顯示)之間提供EMI屏蔽，該電子組件可以安置在該傳導屏蔽558之內與在該承載件512之上。該傳導屏蔽558包含孔洞(aperture)560以使該封裝件包覆體502流入該傳導屏蔽558，致使該傳導屏蔽558也可作用為模製鎖(mold lock)。
內部互連528(如接合焊線或帶狀接合焊線)連接在於該倒裝晶片510的該主動側522處的該接合墊530和該承載件512之間。外部互連532(如錫球)附接至該承載件512下面以連接到如印刷電路板或另一積體電路封裝件系統之下一系統層級(未顯示)。
現參照第6圖，係顯示於本發明的第五實施例中之積體電路封裝件系統600的上視圖。該積體電路封裝件系統600為該積體電路封裝件系統100之應用的積體電路層疊封裝件系統。該上視圖繪示該積體電路封裝件系統100之該封裝件包覆體102具有安置於其上之裝置608(如封裝之積體電路)。
現參照第7圖，係顯示沿著第6圖之7--7線之該積體電路封裝件系統600之剖面圖。該剖面圖描繪出該裝置608安置在該積體電路封裝件系統100的該基材104之上。例如：錫球706可以連接該裝置608和該基材104。該基材104具有雙重連接可作用為該裝置608和該倒裝晶片210之間、該承載件212以及到下一系統層級(未顯示)之重新分配功能。
現參照第8圖，係顯示於形成該倒裝晶片210之步驟中的第2圖之積體電路封裝件系統100之剖面圖。該剖面圖繪示具有該第一傳導凸塊224的該倒裝晶片210和該接合墊230形成於該主動側222之上。該第一傳導凸塊224可以藉由一些製程(如焊錫凸塊(solder bumping))而形成。於該主動側222的周圍處之該接合墊230並未凸出。為了說明目的，該倒裝晶片210係以單獨裝置來顯示，然其了解外在晶圓層級中可以進行包含一些倒裝晶片之製程。
現參照第9圖，係顯示於安置該基材104之步驟中的第8圖的結構。該剖面圖繪示該基材104以及具有該第一傳導凸塊224和該接合墊230的倒裝晶片210。該倒裝晶片210具有該非主動側220和該主動側222。該第一傳導凸塊224和該接合墊230係於該倒裝晶片210之該主動側222之上。該基材104安置於該倒裝晶片210之該主動側222之上。
該基材104在該基材104的該頂部側216和該基材104的該底部側218兩側處具有該接觸墊106。在該基材104的該底部側218處之該接觸墊106與該第一傳導凸塊224對準。回流製程(reflow process)可以在該基材104和該倒裝晶片210之間形成電子連接。
現參照第10圖，係顯示形成該填膠之步驟中的第9圖的結構。該剖面圖繪示該基材104和具有該第一傳導凸塊224和該接合墊230的倒裝晶片210。於本發明之積體電路封裝件系統之製造的中間步驟中，該填膠226係在該基材104與環繞該第一傳導凸塊224的該倒裝晶片210之間施用並固化。該填膠226可以於該基材104和該倒裝晶片210之間提供機械支持。
現參照第11圖，係顯示於形成該黏著劑之步驟中的第10圖的結構。該剖面圖繪示該基材104係藉由該第一傳導凸塊224安置在該倒裝晶片210之上以連接該基材104和該倒裝晶片210。該倒裝晶片210也包含該接合墊230。該填膠226係於該基材104和該倒裝晶片210之間。該倒裝晶片210具有該非主動側220和該主動側222。
該黏著劑(如環氧或多層黏著劑)210可以施用在該倒裝晶片210的該非主動側220。如虛線所示，該黏著劑214可以為晶圓背側層壓膜而使此步驟為可選擇的。
現參照第12圖，係顯示於附接該承載件之步驟中的第11圖的結構。該剖面圖繪示該基材104、該承載件212以及具有該第一傳導凸塊224和該接合墊230之該倒裝晶片210。該倒裝晶片210包含該非主動側220和該主動側222。該內部互連228連接在該倒裝晶片210的主動側22和該承載件212上的該接合墊230。該外部互連232附接於該承載件212下面以連接下一系統層級(未顯示)。第2圖之該封裝件包覆體102可以在該倒裝晶片210、該內部互連228以及該承載件212上形成而露出該基材104的該頂部側216以形成第2圖的該積體電路封裝件系統100。
現參照第13圖，係顯示本發明之實施例中之用以製造該積體電路封裝件系統100的積體電路封裝方法1300之流程圖。該方法1300包含在方塊1302中，於承載件之上設置倒裝晶片，且該倒裝晶片的非主動側係面對該承載件；在方塊1304中，於該倒裝晶片之上設置基材；在方塊1306中，於該倒裝晶片和該承載件之間連接內部互連；以及，在方塊1308中，於該承載件之上包覆該倒裝晶片和該內部互連，並露出該基材。
本發明的又另一重要態樣在於其有價值地支持與幫助降低成本、簡化系統與增加性能之歷史趨勢。
本發明的這些和其他有價值的態樣必然地促進科技狀態達到至少下一層級。
因此，已發現到本發明的積體電路封裝件系統提供了重要且迄今未知與未曾採用以對電路系統改善產量、增加可靠度與降低成本之解決方案、能力和功能性態樣。此產生的製程和組態為明確、節省成本、不繁複、高度多功能、精確、敏感與有效且可藉由適合已知元件而實施以迅速、有效且經濟之製造、應用與利用。
雖然本發明係結合特定的最佳模式而描述，但要了解到，有鑑於前述說明，對於所屬技術領域中具有通常知識者而言，眾多替代、修改及變化將是顯而易見的。據此，其係傾向包含所有落在本申請專利範圍之範疇內的此類替代、修改及變化。在此提出或顯示於附圖中的所有內容係為範例之說明而非用於限制。
100、300、400、500、600．．．積體電路封裝件系統
102、302、402、502．．．封裝件包覆體
104、304、404、504．．．基材
106、306、406、506．．．接觸墊
210、410、510．．．倒裝晶片
212、312、412、512承載件
214．．．黏著劑
216、316、416、516．．．頂部側
218、318、418、518．．．底部側
220、520．．．非主動側
222、522．．．主動側
224、324、424、524．．．第一傳導凸塊
226、326．．．填膠
228、328、428、528．．．內部互連
230、330、430、444、530．．．接合墊
232、332、432、532．．．外部互連
310．．．第一倒裝晶片
320、420．．．第一非主動側
322、422．．．第一主動側
336、436．．．第二非主動側
338、438．．．第二主動側
334．．．第二倒裝晶片
340．．．第二傳導凸塊
442．．．積體電路裝置
558．．．傳導屏蔽
608．．．裝置
706．．．錫球
1300．．．積體電路封裝方法
1302、1304、1306、1308．．．方塊
第1圖係為本發明之第一實施例中的積體電路封裝件系統之上視圖；
第2圖係為沿著第1圖之2--2線之積體電路封裝件系統之剖面圖；
第3圖係為本發明之第二實施例中之沿著第1圖之2--2線的積體電路封裝件系統之剖面圖；
第4圖係為本發明之第三實施例中之沿著第1圖之2--2線的積體電路封裝件系統之剖面圖；
第5圖係為本發明之第四實施例中之沿著第1圖之2--2線的積體電路封裝件系統之剖面圖；
第6圖係為本發明之第五實施例中的積體電路封裝件系統之上視圖；
第7圖係為沿著第6圖之7--7線之積體電路封裝件系統之剖面圖；
第8圖係為於形成倒裝晶片之步驟中的第2圖之積體電路封裝件系統之剖面圖；
第9圖係為於安置該基材之步驟中的第8圖的結構；
第10圖係為於形成該填膠之步驟中的第9圖的結構；
第11圖係為於形成該黏著劑之步驟中的第10圖的結構；
第12圖係為於附接該承載件之步驟中的第11圖的結構；以及
第13圖係為本發明之實施例中之用以製造該積體電路封裝件系統的積體電路封裝方法之流程圖。
100．．．積體電路封裝件系統
102．．．封裝件包覆體104基材
106．．．接觸墊
210．．．倒裝晶片
212．．．承載件
214．．．黏著劑
216．．．頂部側
218．．．底部側
220．．．非主動側
222．．．主動側
224．．．第一傳導凸塊
226．．．填膠
228．．．內部互連
230．．．接合墊
232．．．外部互連

Claims (10)

  1. 一種積體電路封裝方法，包括下列步驟：於承載件之上設置倒裝晶片，且該倒裝晶片的非主動側係面對該承載件；於 該倒裝晶片之上設置基材；於該倒裝晶片和該承載件之間連接內部互連；以及形成包覆體於該承載件之上包覆該倒裝晶片和該內部互連，並露出該基材，其中，該包覆體與該基材的頂部側共平面。
  2. 如申請專利範圍第1項之方法，復包括下列步驟：於該承載件之上設置積體電路裝置；以及其中，於該承載件之上設置該倒裝晶片的步驟包含：於該積體電路裝置之上設置該倒裝晶片。
  3. 如申請專利範圍第1項之方法，復包括下列步驟：於該承載件之上設置傳導屏蔽；以及其中，於該承載件之上設置該倒裝晶片的步驟包含：於該傳導屏蔽之上設置該倒裝晶片。
  4. 如申請專利範圍第1項之方法，其中，於該承載件之上設置該倒裝晶片的步驟包含將附接於該非主動側的背側層壓件面對於該承載件。
  5. 如申請專利範圍第1項之方法，其中，於該倒裝晶片之上設置該基材的步驟包含將傳導凸塊連接於該基材，且 該傳導凸塊係附接於該倒裝晶片的主動側。
  6. 一種積體電路封裝件系統，包括：承載件；倒裝晶片，係於該承載件之上，且該倒裝晶片的非主動側係面對該承載件；基材，係於該倒裝晶片之上；內部互連，係介於該倒裝晶片和該承載件之間；以及包覆體，係於該倒裝晶片、該內部互連和該承載件之上，並露出該基材，其中，該包覆體與該基材的頂部側共平面。
  7. 如申請專利範圍第6項之系統，復包括：積體電路裝置，係於該承載件之上；以及其中，該倒裝晶片係於該積體電路裝置之上。
  8. 如申請專利範圍第6項之系統，復包括：傳導屏蔽，係於該承載件之上；以及其中，該倒裝晶片係於該傳導屏蔽之上。
  9. 如申請專利範圍第6項之系統，其中，於該承載件之上的該倒裝晶片包含附接於該非主動側且面對於該承載件的背側層壓件。
  10. 如申請專利範圍第6項之系統，其中，該基材係連接有傳導凸塊，且該傳導凸塊係附接於該倒裝晶片的主動側。
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Publication number Priority date Publication date Assignee Title
US7919871B2 (en) * 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
US9559046B2 (en) * 2008-09-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-in package-on-package structure using through silicon vias
US7859094B2 (en) * 2008-09-25 2010-12-28 Stats Chippac Ltd. Integrated circuit package system for stackable devices
JP5543094B2 (ja) * 2008-10-10 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 低ノイズ半導体パッケージ
US9293350B2 (en) * 2008-10-28 2016-03-22 Stats Chippac Ltd. Semiconductor package system with cavity substrate and manufacturing method therefor
US7863109B2 (en) * 2008-12-05 2011-01-04 Stats Chippac Ltd. Integrated circuit packaging system with a protrusion on an inner stacking module and method of manufacture thereof
US9324672B2 (en) * 2009-08-21 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package
US8035235B2 (en) * 2009-09-15 2011-10-11 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US9093391B2 (en) * 2009-09-17 2015-07-28 Stats Chippac Ltd. Integrated circuit packaging system with fan-in package and method of manufacture thereof
US8225252B2 (en) * 2010-06-25 2012-07-17 Intel Corporation Systems, methods, apparatus and computer readable mediums for use in association with systems having interference
US8080445B1 (en) * 2010-09-07 2011-12-20 Stats Chippac, Ltd. Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
US20120061789A1 (en) * 2010-09-13 2012-03-15 Omnivision Technologies, Inc. Image sensor with improved noise shielding
US9070851B2 (en) 2010-09-24 2015-06-30 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
US9059160B1 (en) 2010-12-23 2015-06-16 Marvell International Ltd. Semiconductor package assembly
US9324659B2 (en) 2011-08-01 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die
US8623711B2 (en) 2011-12-15 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8629567B2 (en) 2011-12-15 2014-01-14 Stats Chippac Ltd. Integrated circuit packaging system with contacts and method of manufacture thereof
US9219029B2 (en) * 2011-12-15 2015-12-22 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
TWI517343B (zh) * 2014-03-25 2016-01-11 恆勁科技股份有限公司 覆晶堆疊封裝結構及其製作方法
CN205944139U (zh) 2016-03-30 2017-02-08 首尔伟傲世有限公司 紫外线发光二极管封装件以及包含此的发光二极管模块
JP7089999B2 (ja) * 2018-09-25 2022-06-23 新光電気工業株式会社 電子部品内蔵基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815254B2 (en) * 2003-03-10 2004-11-09 Freescale Semiconductor, Inc. Semiconductor package with multiple sides having package contacts
US7084487B1 (en) * 2003-12-09 2006-08-01 Xilinx, Inc. Shielded platform for die-bonding an analog die to an FPGA
TW200735301A (en) * 2006-02-17 2007-09-16 Stats Chippac Ltd Integrated circuit package system with die on base package

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04284661A (ja) * 1991-03-13 1992-10-09 Toshiba Corp 半導体装置
US6075710A (en) * 1998-02-11 2000-06-13 Express Packaging Systems, Inc. Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips
KR100266693B1 (ko) * 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
US6369448B1 (en) * 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US6424031B1 (en) * 2000-05-08 2002-07-23 Amkor Technology, Inc. Stackable package with heat sink
US6507114B2 (en) * 2001-01-30 2003-01-14 Micron Technology, Inc. BOC semiconductor package including a semiconductor die and a substrate bonded circuit side down to the die
KR100369907B1 (ko) * 2001-02-12 2003-01-30 삼성전자 주식회사 반도체 패키지와 그 반도체 패키지의 기판 실장 구조 및적층 구조
TW544901B (en) * 2001-06-13 2003-08-01 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
US6555917B1 (en) * 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
TWI268581B (en) * 2002-01-25 2006-12-11 Advanced Semiconductor Eng Stack type flip-chip package including a substrate board, a first chip, a second chip, multiple conductive wire, an underfill, and a packaging material
US7057269B2 (en) * 2002-10-08 2006-06-06 Chippac, Inc. Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package
TW567601B (en) * 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
US7056810B2 (en) * 2002-12-18 2006-06-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor apparatus, and semiconductor apparatus and electric appliance
TW556961U (en) * 2002-12-31 2003-10-01 Advanced Semiconductor Eng Multi-chip stack flip-chip package
TWI311353B (en) * 2003-04-18 2009-06-21 Advanced Semiconductor Eng Stacked chip package structure
KR100604821B1 (ko) * 2003-06-30 2006-07-26 삼성전자주식회사 적층형 볼 그리드 어레이 패키지 및 그 제조방법
KR100546374B1 (ko) * 2003-08-28 2006-01-26 삼성전자주식회사 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
US7279783B1 (en) * 2003-10-29 2007-10-09 Silicon Pipe, Inc. Partitioned integrated circuit package with central clock driver
DE10360708B4 (de) * 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
KR100573302B1 (ko) * 2004-10-07 2006-04-24 삼성전자주식회사 와이어 본딩을 이용한 패키지 스택 및 그 제조 방법
KR100626618B1 (ko) * 2004-12-10 2006-09-25 삼성전자주식회사 반도체 칩 적층 패키지 및 제조 방법
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
SG130055A1 (en) * 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
DE102006016345A1 (de) * 2006-04-05 2007-10-18 Infineon Technologies Ag Halbleitermodul mit diskreten Bauelementen und Verfahren zur Herstellung desselben
TWI309079B (en) * 2006-04-21 2009-04-21 Advanced Semiconductor Eng Stackable semiconductor package
TWI298198B (en) * 2006-05-30 2008-06-21 Advanced Semiconductor Eng Stackable semiconductor package
TWI317993B (en) * 2006-08-18 2009-12-01 Advanced Semiconductor Eng Stackable semiconductor package
TWI312569B (en) * 2006-10-12 2009-07-21 Siliconware Precision Industries Co Ltd Semiconductor package on which a semiconductor device is stacked and production method thereof
US7608921B2 (en) * 2006-12-07 2009-10-27 Stats Chippac, Inc. Multi-layer semiconductor package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815254B2 (en) * 2003-03-10 2004-11-09 Freescale Semiconductor, Inc. Semiconductor package with multiple sides having package contacts
US7084487B1 (en) * 2003-12-09 2006-08-01 Xilinx, Inc. Shielded platform for die-bonding an analog die to an FPGA
TW200735301A (en) * 2006-02-17 2007-09-16 Stats Chippac Ltd Integrated circuit package system with die on base package

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